JPH03290961A - Complementary type gate array - Google Patents
Complementary type gate arrayInfo
- Publication number
- JPH03290961A JPH03290961A JP2091620A JP9162090A JPH03290961A JP H03290961 A JPH03290961 A JP H03290961A JP 2091620 A JP2091620 A JP 2091620A JP 9162090 A JP9162090 A JP 9162090A JP H03290961 A JPH03290961 A JP H03290961A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- oxide film
- silicon oxide
- film
- element isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 title claims abstract description 6
- 238000002955 isolation Methods 0.000 claims abstract description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 13
- 239000010410 layer Substances 0.000 abstract description 11
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 230000010354 integration Effects 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 230000002265 prevention Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 238000003491 array Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は相補型ゲートアレーに利用する。[Detailed description of the invention] [Industrial application field] The present invention is utilized in complementary gate arrays.
本発明は、ＣＭＯＳゲートアレーにおいて、素子間分離
に溝分離を用いることにより、ラッチアップの防止と高
集積化とを図ったものである。The present invention aims to prevent latch-up and increase integration by using trench isolation for element isolation in a CMOS gate array.
従来、相補型ゲートアレー（以下、ＣＭＯＳゲートアレ
ーという。）においては、第３図に示すように、Ｎチャ
ネルＭＯＳトランジスタ（以下、ＮＭＯＳトランジスタ
という。）とＰチャネルＭＯＳトランジスタ （以下、
ＰＭＯＳトランジスタという。）の素子分離は、ＬＯＣ
Ｏ３法（酸化膜分離法）によるフィールド酸化膜５によ
り行っている。また、ラッチアップを防止する方法とし
て、チャネルストッパー４、ならびにＮ型ウェル２およ
びＰ型ウェル３からなるダブルウェルを用いている。Conventionally, in a complementary gate array (hereinafter referred to as CMOS gate array), as shown in FIG. 3, an N-channel MOS transistor (hereinafter referred to as NMOS transistor) and a P-channel MOS transistor (hereinafter referred to as
It is called a PMOS transistor. ) element isolation is LOC
The field oxide film 5 is formed using the O3 method (oxide film separation method). Further, as a method for preventing latch-up, a channel stopper 4 and a double well consisting of an N-type well 2 and a P-type well 3 are used.
また、ＮＭＯＳトランジスタとＮＭＯＳトランジスタ、
およびＰＭＯＳトランジスタとＰＭＯＳトランジスタの
素子分離も同様にＬＯＣＯ３法によるフィールド酸化膜
５で行っている。In addition, NMOS transistors and NMOS transistors,
Element isolation between the PMOS transistors is also performed using a field oxide film 5 using the LOCO3 method.
近年、ゲートアレーでは、高集積化が必要不可欠となっ
ている。高集積化の手段としては、トランジスタや配線
の超微細化も重要であるが、効率的に大きな期待はでき
ない。むしろ、不活性領域である素子分離領域を微細化
することで、大幅な高集積化が可能となる。In recent years, high integration has become essential for gate arrays. Ultra-miniaturization of transistors and wiring is also important as a means of achieving high integration, but it does not hold much promise for efficiency. Rather, by miniaturizing the element isolation region, which is an inactive region, it becomes possible to achieve a significantly higher degree of integration.
しかし、前述した従来の構造では素子分離をＬｏｃｏｓ
法により行っているため、ある程度の微細化が進むとウ
ェル濃度を濃くしても、第３図で示すＮ型拡散層９とＮ
型ウェル２の間や、Ｐ型拡散層１０とＰ型ウェル３の間
の耐圧が小さくなる等、いわゆるラッチアップ耐性は著
しく劣化する欠点がある。However, in the conventional structure mentioned above, element isolation is
Because this is done by the method, even if the well concentration is increased once the miniaturization progresses to a certain degree, the N-type diffusion layer 9 and the N-type diffusion layer 9 shown in FIG.
There is a drawback that the so-called latch-up resistance is significantly deteriorated, such as the breakdown voltage between the type wells 2 and between the P-type diffusion layer 10 and the P-type well 3 being reduced.
また同様に、ＮＭＯＳトランジスタとＮＭＯＳトランジ
スタもしくは２ＭＯＳトランジスタと２ＭＯＳトランジ
スタが隣りあった所では、前記Ｌｏｃｏｓ法では、ある
程度の微細化によりＮ型拡散層間隔もしくはＰ型拡赦層
間隔が縮まると耐圧が劣化し、寄生トランジスタ特性を
生じてしまう欠点がある。Similarly, in the case where an NMOS transistor and an NMOS transistor or a 2MOS transistor and a 2MOS transistor are placed next to each other, in the Locos method, as the N-type diffusion layer spacing or the P-type relaxation layer spacing decreases due to a certain degree of miniaturization, the withstand voltage deteriorates. However, it has the disadvantage of causing parasitic transistor characteristics.
本発明の目的は、前記の欠点を除去することにより、ラ
ッチアップを防止でき、かつ高集積度が可能であるＣＭ
ＯＳゲートアレーを提供することにある。An object of the present invention is to provide a CM that can prevent latch-up and enable high integration by eliminating the above-mentioned drawbacks.
The purpose is to provide an OS gate array.
本発明は、ＰチャネルＭＯＳトランジスタとＮチャネル
ＭＯＳトランジスタとを素子とする相補型ゲートアレー
において、前記素子間の分離を行うための溝分離構造を
設けたことを特徴とする。The present invention is characterized in that a complementary gate array including P-channel MOS transistors and N-channel MOS transistors as elements is provided with a groove isolation structure for isolating the elements.
溝分離は、微細な溝を形成し、溝内を例えばシリコン酸
化物で埋めて完全な絶縁分離を達成できる。In trench isolation, complete insulation isolation can be achieved by forming a fine trench and filling the trench with, for example, silicon oxide.
従って、素子分離領域を小さくでき、高集積化が可能に
なるとともに、隣り合う領域は完全に絶縁分離されラッ
チアップの発生を防止することが可能となる。Therefore, the element isolation region can be made smaller, higher integration is possible, and adjacent regions are completely insulated, thereby preventing latch-up.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の第一実施例を示す模式的縦断面図であ
る。FIG. 1 is a schematic vertical sectional view showing a first embodiment of the present invention.
本箱−実施例は、２ＭＯＳトランジスタとＮＭＯＳトラ
ンジスタとを含むＣＭＯＳゲートアレーにおいて、
本発明の特徴とするところの、素子間分離のための、内
部がシリコン酸化膜１５で埋め込まれた素子分離溝１４
が設けられている。This embodiment is a CMOS gate array including 2 MOS transistors and an NMOS transistor, in which an element isolation trench 14 whose inside is filled with a silicon oxide film 15 for isolation between elements, which is a feature of the present invention, is used.
is provided.
次に、本箱−実施例の製造方法について簡単に説明する
。Next, the manufacturing method of the bookcase--Example will be briefly explained.
Ｐ型シリコン基板１内の所定の位置にＮ型ウェル２を形
成する。An N-type well 2 is formed at a predetermined position within a P-type silicon substrate 1.
次に、各々の素子間で分離を要する箇所にエツチングに
より、例えば、輻約１μｍ１深さ約５μｍ程度の素子分
離溝１４を形成する。Next, an element isolation groove 14 having a diameter of about 1 .mu.m and a depth of about 5 .mu.m, for example, is formed by etching at a location where isolation is required between each element.
次に、ゲート絶縁膜６およびゲート電極７を形成し、ゲ
ート電極７をマスクとしてイオン注入により、Ｎ型拡散
層９およびＰ型拡散層１ｏを形成する。Next, a gate insulating film 6 and a gate electrode 7 are formed, and an N-type diffusion layer 9 and a P-type diffusion layer 1o are formed by ion implantation using the gate electrode 7 as a mask.
次に、全面を薄く熱酸化しシリコン酸化膜８を形成した
後、素子分離溝１４を埋めるために、全面に絶縁膜例え
ばＢＰＳＧ等のシリコン酸化膜Ｉ５を成長し、さらに平
坦性をよくするために全体を異方性エツチングし、素子
分離溝１４のみにシリコン酸化膜１５を残す。Next, after thermally oxidizing the entire surface thinly to form a silicon oxide film 8, an insulating film, for example, a silicon oxide film I5 such as BPSG, is grown on the entire surface in order to fill the element isolation trench 14, and to further improve the flatness. Then, the entire structure is anisotropically etched, leaving the silicon oxide film 15 only in the element isolation groove 14.
次に、既存の方法により、層間絶縁膜としてのシリコン
酸化膜１１を形成し、それにコンタクト孔１２をあけ、
アルミニウム配線１３を形成することにより、本箱−実
施例のＣＭＯＳゲートアレーを得る。Next, a silicon oxide film 11 is formed as an interlayer insulating film by an existing method, and a contact hole 12 is formed in it.
By forming the aluminum wiring 13, the CMOS gate array of the bookcase-embodiment is obtained.
第２図は本発明の第二実施例を示す模式的縦断面図で、
素子分離溝内にシリコン酸化膜を埋め込む方法を変えた
場合を示す。FIG. 2 is a schematic vertical sectional view showing a second embodiment of the present invention,
A case is shown in which the method of burying the silicon oxide film in the element isolation trench is changed.
前述した第一実施例では、素子分離溝１４をトランジス
タ形成前に開孔したが、第２図に示すように、素子分離
溝１４をトランジスタ形成後に開孔することも可能であ
る。In the first embodiment described above, the element isolation trench 14 was opened before the transistor was formed, but as shown in FIG. 2, it is also possible to open the element isolation trench 14 after the transistor was formed.
この場合、素子分離溝１４に埋め込むシリコン酸化膜１
５をゲート電極７とアルミニウム配線１３の間のシリコ
ン酸化膜１１と同時に形成できる。In this case, the silicon oxide film 1 buried in the element isolation trench 14 is
5 can be formed simultaneously with the silicon oxide film 11 between the gate electrode 7 and the aluminum wiring 13.
なお、本発明による構造は、実施例に述べた材料および
トランジスタ構造に限られるものではない。Note that the structure according to the present invention is not limited to the materials and transistor structure described in the examples.
以上説明したように、本発明によれば、ラッチアップを
生じることなしに素子分離領域を微細化でき、同時に大
幅な高集積化が可能となり、その効果は大である。また
、本発明による構造では、例えば、Ｐ型シリコン基板を
用いる場合は、ＰＭＯ８形成領域にＮ型ウェルを形成す
るだけでよく、微細化を行ってもダブルウェルとしての
Ｐ型ウェルの形成は不要となる効果も得られる。As described above, according to the present invention, it is possible to miniaturize the element isolation region without causing latch-up, and at the same time, it is possible to significantly increase the degree of integration, which has great effects. Furthermore, in the structure according to the present invention, for example, when using a P-type silicon substrate, it is only necessary to form an N-type well in the PMO8 formation region, and even if miniaturization is performed, there is no need to form a P-type well as a double well. You can also obtain the following effect.
極、８．１１．１５・・・シリコン酸化膜、９・・・Ｎ
型拡散層、１０・・・Ｐ型拡散層、１２・・・コンタク
ト孔、１３・・・アルミニウム配線、１４・・・素子分
離溝。Pole, 8.11.15...Silicon oxide film, 9...N
type diffusion layer, 10...P type diffusion layer, 12...contact hole, 13...aluminum wiring, 14...element isolation groove.
Claims (1)
トランジスタとを素子とする相補型ゲートアレーにおい
て、 前記素子間の分離を行うための溝分離構造を設けた ことを特徴とする相補型ゲートアレー。[Claims] 1. P-channel MOS transistor and N-channel MOS
A complementary gate array having transistors as elements, characterized in that a trench isolation structure is provided for isolating the elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2091620A JPH03290961A (en) | 1990-04-06 | 1990-04-06 | Complementary type gate array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2091620A JPH03290961A (en) | 1990-04-06 | 1990-04-06 | Complementary type gate array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03290961A true JPH03290961A (en) | 1991-12-20 |
Family
ID=14031617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2091620A Pending JPH03290961A (en) | 1990-04-06 | 1990-04-06 | Complementary type gate array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03290961A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08203994A (en) * | 1995-01-24 | 1996-08-09 | Nec Corp | Semiconductor device and its manufacturing method |
| US6087705A (en) * | 1997-12-19 | 2000-07-11 | Advanced Micro Devices, Inc. | Trench isolation structure partially bound between a pair of low K dielectric structures |
| US6140691A (en) * | 1997-12-19 | 2000-10-31 | Advanced Micro Devices, Inc. | Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate |
| US6194772B1 (en) * | 1999-05-12 | 2001-02-27 | United Microelectronics Corp. | High-voltage semiconductor device with trench structure |
-
1990
- 1990-04-06 JP JP2091620A patent/JPH03290961A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08203994A (en) * | 1995-01-24 | 1996-08-09 | Nec Corp | Semiconductor device and its manufacturing method |
| US5966598A (en) * | 1995-01-24 | 1999-10-12 | Nec Corporation | Semiconductor device having an improved trench isolation and method for forming the same |
| US6087705A (en) * | 1997-12-19 | 2000-07-11 | Advanced Micro Devices, Inc. | Trench isolation structure partially bound between a pair of low K dielectric structures |
| US6140691A (en) * | 1997-12-19 | 2000-10-31 | Advanced Micro Devices, Inc. | Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate |
| US6194772B1 (en) * | 1999-05-12 | 2001-02-27 | United Microelectronics Corp. | High-voltage semiconductor device with trench structure |
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