JPH03286333A - Membership function generating circuit - Google Patents

Abstract

PURPOSE:To produce the membership function signals of various U function characteristics in simple constitution by providing a differential amplifier circuit, an output circuit, and a lower limit level clamping circuit. CONSTITUTION:A differential amplifier circuit containing an emitter resistance uses a differential pair of NPN type bipolar transistors TR Q1 and Q2 as an amplifier element. An output circuit contains an emitter follower circuit consisting of the NPN TR Q3 and Q4 connected in parallel with each other and a constant current source IS2. A lower limit level clamping circuit consists of an NPN TR Q5 and a clamping voltage source VCL. In such a constitution, the different characteristics can be obtained by setting optionally a constant current I1, the collector resistances RC1 and RC2, and the emitter resistance RE1 and RE2. Then the membership functions of various U function characteristics can be obtained with the selection of the circuit constants.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fuzzy inference calculation circuit used in various control systems, and more particularly to a membership function generation circuit for U functions and π functions.

[Conventional technology]

Conventionally, computer control, which requires logical rigor, has been the mainstream. Recently, so-called fuzzy control, which uses fuzzy theory that quantifies vague thinking and judgment methods, has become known.

In fuzzy control, optimal control values are determined by fuzzy inference calculations, and membership values are used in this fuzzy inference. This membership value is given in the form of a membership function in response to various input signals. When performing fuzzy control using a computer, membership functions are given by defining specific numerical values as a data table in a memory area.

[Problem to be solved by the invention]

Fuzzy theory is characterized by its flexibility, and can be applied not only to complex and large-scale control systems but also to a wide range of fields. When using fuzzy theory in a relatively small-scale control system, it would be convenient to have a membership function generator that has a simple configuration and can easily change its functional characteristics.

An object of the present invention is to provide a membership function generator that can realize variable characteristics with a relatively simple configuration.

[Means to solve the problem]

According to a first aspect of the present invention, there is provided a member nop function generation circuit that outputs a function signal according to an input signal, which includes: a differential amplifier circuit including a differential transistor pair; and a differential output of the differential amplifier circuit. The device includes an output circuit for outputting each signal from the same output terminal, and a clamp circuit for clamping the lower limit level of the output signal of the output circuit.

A second aspect of the invention is a membership function generation circuit that outputs a function signal according to an input signal, which includes: a differential amplifier circuit including a differential transistor pair; The device includes an output circuit for outputting each of the output signals from the same output terminal, and a clamp circuit for clamping the upper limit level of the output signal of the output circuit.

[Effect]

According to the first aspect of the invention, the differential amplifier circuit generates a pair of differential output signals, and these differential output signals are outputted from the same output terminal by the output circuit. The lower limit level of this output signal is clamped by a clamp circuit.

At this time, by setting the lower limit level to a level higher than the intersection point of the differential output signal, as the potential level of the input signal changes from negative to positive, the output signal temporarily changes from a high potential level to a low potential level. It has the so-called same functional characteristic of dropping to a high potential level and then switching back to a high potential level.

In this way, it is possible to generate membership function signals having arbitrary same function characteristics with a relatively simple configuration and by setting circuit constants.

According to the fourth aspect of the invention, the differential amplifier circuit generates a pair of differential output signals, and these differential output signals are outputted from the same output terminal by the output circuit. The upper limit level of this output signal is clamped by a clamp circuit.

At this time, by setting the upper limit level to a level lower than the intersection point of the differential output signal, the output signal will change from the low potential level to the high potential level once as the potential level of the input signal changes from negative to positive. It has a so-called π-function characteristic in which the potential rises to a low potential level and then returns to a low potential level.

In this way, a membership function signal having an arbitrary π function characteristic can be generated with a relatively simple configuration and by setting circuit constants.

〔Example〕

Next, preferred embodiments of the present invention and the second invention will be described based on the drawings.

First Embodiment FIG. 1 shows an embodiment of the invention according to claim 1. This embodiment discloses an example of a generating circuit for a U function as a membership function. The circuit is roughly divided into a differential amplifier circuit, an output circuit, and a clamp circuit.

The differential amplifier circuit is a so-called differential amplifier circuit with an emitter resistor, and uses NPN bipolar transistors (hereinafter referred to as transistors) Q and Q2 as amplifying elements.
A differential pair is used.

A first input terminal is connected to the base of the transistor Q1, and an input voltage VIN is input thereto. The collector has a power supply voltage V on the high potential side. 0 is applied via the collector resistor Rc1, and a first output terminal is derived from the collector, from which the output voltage V. 1 is output. An emitter resistor RE1 is connected to the emitter, and the emitter resistor RE1 is connected to a constant current source ISt.

A second input terminal is connected to the base of the transistor Q2, and a reference voltage V 1 is applied thereto. The reference EF voltage V is provided by a reference voltage source E. The power supply voltage Vcc is applied to the core EF collector via the collector resistor R61.
is given, and a second output terminal is derived from the collector, from which an output voltage ■. 2 is output. An emitter resistor RE2 is connected to the emitter, and an emitter resistor R
The other end is commonly connected to the other end of the emitter resistor REI2 and connected to a constant current source IS.

The output circuit consists of NPN transistors Q connected in parallel.
and NPN type transistor Q4, and constant current source IS
It is composed of an emitter follower circuit consisting of 2. The collectors and emitters of the transistors Q3 and Q4 are connected to each other, the collector common connection point is connected to the high potential side voltage source voo, and the emitter common connection point is connected to the constant current source IS2. An output terminal is led out from the emitter common connection point, and an output voltage ■ is output from this output terminal. This output voltage■. The base of transistor Q3 is connected to the collector of transistor Q, and the base of transistor Q4 is connected to the collector of transistor Q.
The base of is connected to the collector of transistor Q2. Therefore, the differential output signal, transistor Q1
The output voltage of the transistor Q and the output voltage of the transistor Q. 2 is added by transistor Q3 and transistor Q4, and one output signal output voltage from the common emitter connection point.
is output as

The UT clamp circuit includes an NPN transistor Q5 and a clamp voltage source V. It is composed of L. transistor Q
5 has a collector connected to a high potential side voltage source Vcc, an emitter connected to a common emitter connection point of transistors Q3 and Q4, and a base connected to a clamp voltage source Vcc.
L is connected.

The voltage value of this clamp voltage source VCL determines the operating point of transistor Q5, and therefore transistor Q1
The emitter potential of Q4, ie, the output voltage, is clamped to a certain potential level.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIG. 2. FIG. 2 is an input/output characteristic diagram of the circuit of FIG. 1.

When the input voltage VN is negative, transistor Q1 is OF
F, and transistor Q is turned on. Therefore, the output signal Vo: of the transistor Q becomes the high potential level given by the high potential side voltage source 2, and the output signal Vo2 of the transistor Q becomes the low potential level. Eventually,
As the input voltage ■IN changes from negative to positive, the transistor Q1 turns on and the l-transistor Q turns off, so the output signal V. 1 falls to the low potential level and the output signal V. 2 rises to a high potential level. These differential output voltages change in opposite directions. l and o2 are applied to the bases of transistor Q and transistor Q4, respectively. Output signal ■. When the output signal Vo2 is at a high potential level, the transistor Q3 is turned on, and when the output signal Vo2 is at a high potential level, the transistor Q4 is turned on. therefore,
When the output voltage is at the high voltage UT level, it is given by the emitter potential of the transistors Q and Q, and its value is (Voo-V, el). However, at low potential level, transistor Q
Since the emitter of transistor Q5 is connected and the emitter potential of transistor Q5 is clamped to (2cL-Vbe2), the output voltage (2) does not fall below (vCLUT2). As a result, the output voltage b+2 (2) has a U-shaped UT waveform, as shown by the solid line in FIG. In this way, a U-function signal can be generated.

By the way, in the human output characteristics of a differential amplifier circuit, there exists a range (dyna EF range) A that linearly follows the input voltage (■IN■) in a state of change at the time of zero crossing.

The output 102 amplitude, that is, the potential level of the output voltage v SV of this differential amplifier circuit depends on the constant current I1 collector resistance RSR, as shown in the following equation.

OCI C2 v =V -/R・I 01 CCCI CI V =V -R-1 02CCC2C2 IC1+IC2=11 Therefore, constant current engineer, collector resistance Rc1, Ro2
■ Output voltage of any size by setting. 1, vo2 can be obtained. Furthermore, the slope of the straight line of change in the linear tracking range A depends on the constant current I1 emitter resistances R, R. Therefore, constant current HE2 11, emitter resistance R, EI which sets R arbitrarily
Different properties can be obtained by E2. In this way, membership functions with various U-function characteristics can be generated by selecting circuit constants.

Note that even if the constant current source IJ is replaced with a high resistance one, a differential amplifier circuit having substantially the same function can be obtained. Furthermore, the transistors Q1 and Q may be used as PNP type transistors, in which case the bias voltage of each transistor may be applied with a polarity opposite to that shown in FIG.

Second Embodiment FIG. 3 shows an embodiment of the invention according to claim 4. This embodiment discloses an example of a generating circuit for a π function as a membership function. The circuit configuration is the same as in the first embodiment.
It consists of a differential amplifier circuit, an output circuit, and a clamp circuit. Of these, the configuration and operation of the differential amplifier circuit are the first.
It is the same as the example. The difference is in the configurations of the output circuit and clamp circuit.

The output circuit consists of a PNP type transistor Q, a PNP type transistor Q7, and a constant current source IS connected in parallel.
It is composed of an emitter follower circuit consisting of 2. The collectors and emitters of the transistors Q6 and Q7 are connected to each other, and the common emitter connection point is connected to a high potential side voltage source V via a constant current source S2. 0, and the collector common connection point is grounded. An output terminal is led out from the emitter common connection point, and an output voltage 2 is output from this output terminal. This output voltage V is 0[
:T
It has OUTπ function characteristics. The base of transistor Q6 is connected to the collector of transistor Q, and the bases of transistor Q are connected to the collector of transistor Q. Therefore, the output voltage vo of transistor Q, which is a differential output signal, and transistor Q
, are added together by the transistor Q62 and the transistor Q, and outputted as one output signal output voltage (2) from the common emitter connection point.

The UT clamp circuit includes a PNP type transistor Q8 and a clamp voltage r1. Constructed by VCL. The emitter of transistor Q is connected to the common emitter connection point of transistors Q6 and Q, and the collector is connected to the common connection point of the emitters of transistors Q6 and Q.
, and the base thereof is connected to a clamp voltage source VcL. The operating point of the transistor Q5 is determined by the voltage value of the clamp voltage source vCL, and the emitter potential of the transistor QSQ8, that is, the output voltage V is clamped to a certain potential level.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to FIG. FIG. 4 shows the input/output characteristics of the circuit shown in FIG.

When the input voltage VIN is negative, the transistor Q is O
It is an FF, and the transistor Q2 is turned on. Therefore, the output signal Vo1 of the transistor Q1 is the high potential side voltage source V. 0, and the output signal Vo2 of the transistor Q2 becomes a low potential level. Eventually, as the input voltage VIN changes from negative to positive, transistor Q1 tends to turn on and transistor Q2 turns off, so that the output signal V. 1 falls to a low potential level, and output signal vo2 rises to a high potential level. The differential output voltages v 1 , which change in opposite directions, are applied to the gates of the transistor Q6 and the transistor Q7, respectively. Output signal ■. When 1 is at high potential level, transistor Q6=OFF, I-transistor Q7-○N
1 output signal V. When 2 is at a high potential level, the transistor Q
= ON, h transistor Q7 = OFF. Therefore, when the output voltage VOLτ is at a high potential level, it is given by the emitter potential of the transistors Q and Q7, and its value is (). However, at low potential level, transistor Q
Since the emitter potential of is clamped to (VcL+Vbe2), the output voltage ■ does not rise above (■cL+UT■). As a result, the output voltage e22 has a π-shaped UT waveform, as shown by the solid line in FIG. In this way, a π function signal can be generated.

In addition, in the straight line tracking range A in FIG. ,,
E2 The things that can be changed are the same as in the first embodiment shown in FIGS. 1 and 2.

〔Effect of the invention〕

As described above, according to the invention set forth in claim 1 (by configuring the membership function generation circuit using the z1 differential width circuit, the output circuit, and the lower limit level clamp circuit),
Membership function signals with various U-function characteristics can be generated with a relatively compact configuration.

Further, according to the invention according to claim 4, a differential amplifier circuit,
By configuring the membership function generation circuit using the output circuit and the upper limit level clamp circuit, membership function signals having various π function characteristics can be generated with a relatively scrapped configuration.

■...Output voltage 0jiT ■...Reference voltage source, E.F. ■...High potential side voltage source C VCL...Clamp voltage source R, R...Collector resistance CI　　C2 R, RSR/emitter resistance EI E2 E3 Is IS, ... constant current source II 12 Constant current

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is an input/output characteristic diagram of the circuit in FIG. 1, FIG. 3 is a circuit diagram showing a second embodiment of the present invention, and FIG. is an input/output characteristic diagram of the circuit of FIG. 3; Q 1Q 1Q 1Q4, Q5, Q6, Q7゜123 Q8...Transistor VIN...Input voltage

Claims (1)

[Claims] 1. A membership function generation circuit that outputs a function signal according to an input signal, comprising: a differential amplifier circuit including a differential transistor pair; and a differential output signal of the differential amplifier circuit, respectively. A membership function generation circuit comprising: an output circuit for outputting from the same output terminal; and a clamp circuit for clamping a lower limit level of an output signal of the output circuit. 2. In the membership function generating circuit according to claim 1, the output circuit is an NPN type whose gates are connected to the output terminals of the differential transistor pair, and whose collectors and emitters are commonly connected. A membership function generation circuit characterized by being an emitter follower circuit including a transistor pair. 3. In the membership function generating circuit according to claim 2, the clamp circuit has a collector connected to a high potential side power supply, an emitter connected to a common emitter connection point of the transistor pair of the emitter follower circuit, and a base connected to the clamp circuit. NP connected to a clamping voltage source and operating in the linear region
A membership function generation circuit comprising an N-type transistor. 4. In a membership function generation circuit that outputs a function signal according to an input signal, a differential amplifier circuit including a differential transistor pair and a differential output signal of the differential amplifier circuit are output from the same output terminal. A membership function generation circuit comprising: an output circuit for clamping an upper limit level of an output signal of the output circuit; and a clamp circuit for clamping an upper limit level of an output signal of the output circuit. 5. In the membership function generating circuit according to claim 4, the output circuit is an NPN type whose gates are respectively connected to the output terminals of the differential transistor pair, and whose emitters and collectors are respectively commonly connected. A membership function generation circuit characterized by being an emitter follower circuit including a transistor pair. 6. In the membership function generating circuit according to claim 5, the clamp circuit has an emitter connected to a high potential side power supply, a collector connected to a common connection point of the collectors of the transistor pair of the emitter follower circuit, and a base connected to the clamp circuit. NP connected to a clamping voltage source and operating in the linear region
A membership function generation circuit comprising an N-type transistor.