JPH03285484A - Video signal encoding method - Google Patents

Abstract

PURPOSE:To efficiently transmit pictures with satisfactory picture quality by calculating the sum of the power of a transformation coefficient to a prescribed block form the head to of the block after discrete cosine transformation, comparing it with a threshold value, judging it for the unit of the block whether block data is significant or not, and preventing the non-significant block from being transmitted. CONSTITUTION:A picture data encoder circuit 28 exerts discrete cosine transformation encoding upon a digital video signal S21 for every unit blocks Y00, Y01, Y10, Y11, Cb and Cr. Then, an inter-frame/in-frame encoding control unit 30 calculates the power of the block according to a transformation coefficient Coeff(i) from a head i=1 of the said block, to which discrete cosine transformation encoding is executed, to the prescribed block (i=1). Then, a threshold control unit 35 compares the power with the prescribed threshold value. Afterwards, the unit block Y00, (Y01, Y10, Y11, Cb or Cr) exceeding the threshold value is decided as the significant block and transmitted, and the unit block Y00, (Y01, Y10, Y11Cb or Cr) not exceeding the threshold value is decided as the non-significant block and prevented form being transmitted.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

Industrial field of application B Overview of the invention C Conventional technology (Figs. 7 to 9) D Problems to be solved by the invention l1a E Means for solving the problem (Figs. 1 to 6) F Effects (Figures 4 to 6) Overall configuration of G embodiment (Gl) iI image information transmission system (Figures 1 to 6)
(Fig. 5) (G2) Processing at the transmission block setting port 134 (6th
(G3) Operation of the threshold control unit 35 (FIGS. 1 and 3 to 5) (G4) Other embodiments H Effects of the invention A Industrial field of application The present invention relates to a video signal encoding method. This is suitable for application, for example, when a video signal is highly efficiently encoded and transmitted.

B. Summary of the Invention The present invention provides a video signal encoding method that calculates the power of a block from transform coefficients that are transform encoded for each unit block, and transmits each unit block by comparing the power with a predetermined threshold value. , determine non-transmission.

C. Conventional technology Conventionally, in video telephone systems and conference call systems, relatively severe limitations on transmission capacity have been achieved by highly efficient encoding of video signals consisting of moving images into intra-frame encoded data and inter-frame encoded data. A video signal transmission system has been proposed in which a moving image signal is transmitted through a certain transmission path (Japanese Patent Laid-Open No. 1183/1983).

That is, for example, as shown in FIG. 7(A), time 1=
1. When trying to transmit each image PCI, PO2, PO2, etc. that makes up a moving image in , a, t, ......, the video signal has a large autocorrelation as time passes. It is a process that improves transmission efficiency by compressing image data to be transmitted using certain characteristics, and intra-frame encoding processing involves image PCI, PO2, PO2... For example, the pixel data is compared with a predetermined reference value to find the difference, and thus each image PCI, PO2, PO2
- Old: A compressed amount of image data is transmitted using autocorrelation between pixel data within the same frame.

In addition, the interframe encoding process is performed sequentially on adjacent images PCI and PO2, PO2 and P as shown in FIG. 7(B).
Image data PCI2, PO23, etc. formed by the difference in pixel data between C3-... is obtained, and this is calculated at time 1=1. The initial image Pc1 is transmitted together with the intra-frame encoded image data.

In this way, the images PCI, PO2, PO2, etc. can be encoded with high efficiency into digital data with a much smaller amount of data than in the case of transmitting all the image data, and can be sent to the transmission path. .

Such video signal encoding processing is executed in the image data generation device fi having the configuration shown in FIG.

The image data generation device 1 processes the input video signal VD in the preprocessing circuit 2 to perform processing such as one field drop processing and one field line thinning processing, and then converts the luminance signal and chroma signal into 16 pixels (horizontally). ×16
The input image data S11 is converted into input image data S11 consisting of transmission unit block (referred to as macroblock) data consisting of data for pixels (in the vertical direction), and is supplied to the image data encoding circuit 3.

The image data encoding circuit 3 receives the predicted current frame data S12 formed in the predictive encoding circuit 4, calculates the difference from the input image data Sll, and thereby generates interframe encoded data and performs interframe encoding. mode), or by calculating the difference between the input image data Sll and the reference value data, intra-frame encoded data is formed and this is used as the difference data SI3 by the transform encoding circuit 5.
I will share with you.

The transform code Nr5 is composed of a discrete cosine transform circuit, and transform encoded data S14 obtained by orthogonally transforming the differential data S13 and encoding it with high efficiency is supplied to the quantization circuit 6, thereby converting the quantized image data S15.
send out.

The quantized image data S obtained from the quantization circuit 6 in this way
15 is subjected to high-efficiency encoding processing again in the retransformation encoding circuit 7 including a variable length encoding circuit, and then supplied to the transmission buffer memory 8 as transmission image data 516.

In addition, the quantized image data 515 is subjected to inverse quantization and inverse transform encoding processing in the predictive encoding circuit 4, and is decoded into difference data. After that, the pre-prediction frame data is corrected by the difference data. While saving new pre-prediction frame data, input image data Sl
By motion compensating the pre-prediction frame data stored in the predictive encoding circuit 4 using the motion detection data formed based on the motion detection data l, the predicted current frame data can be formed and supplied to the image data encoding circuit 3. As a result, the difference between the input image data S11 of the frame to be currently transmitted (that is, the current frame) and the predicted current frame data S12 is obtained as difference data S13.

In the configuration shown in FIG. 8, when transmitting the moving image described above with reference to FIG. 7, first, at time 11 in FIG. The encoding circuit 3 enters the intra-frame encoding mode and supplies this to the transform encoding circuit 5 as intra-frame encoded difference data S13.
As a result, the transmission image data S16 is supplied to the transmission buffer memory 8 via the quantum north circuit 16 and the re-conversion encoding circuit 7.

At the same time, the quantized image data S15 obtained at the output end of the quantization circuit 6 is subjected to predictive encoding processing in the predictive encoding circuit 4, so that the input image representing the transmission image data S16 is sent to the transmission buffer memory 8. The data is held in the previous frame memory, and then at time point 11, when macroblock data Sll representing the image PC2 is supplied to the image data encoding circuit 3, the predicted current frame data S12 is motion compensated and the image data encoding circuit 3.

Thus, at time 1=12, the image data encoding circuit 3
supplies the inter-frame encoded difference data S13 to the conversion encoding circuit 5, thereby supplying the difference data representing the change in the image between the frames to the transmission buffer memory 8 as transmission image data 316, By supplying the quantized image data 515 to the predictive encoding circuit 4, pre-prediction frame data is formed and stored in the predictive encoding circuit 4.

The same operation is repeated thereafter, and while the image data encoding circuit 3 executes interframe encoding processing, only the difference data representing the change in the image between the previous frame and the current frame is stored in the transmission buffer memory. 8 will be sent out sequentially.

The transmission buffer memory 8 stores the transmission image data S16 sent out in this way, and sequentially transfers the stored transmission image data S16 to the transmission data D TIIAN$ at a predetermined data transmission rate determined by the transmission capacity of the transmission line 9. The data is extracted as such and transmitted to the transmission line 9.

At the same time, the transmission buffer memory 8 detects the amount of remaining data, feeds back the remaining amount data 317 that changes according to the amount of remaining data to the quantization circuit 6, and performs a quantization step according to the remaining amount data S17. By controlling the size, it is possible to maintain an appropriate remaining amount of data (a data amount that does not cause overflow or underflow) in the transmission buffer memory 8 by adjusting the amount of data generated as the transmission image data S16. It is done like this.

Incidentally, when the remaining amount of data in the transmission buffer memory 8 increases to the allowable upper limit, by increasing the step size of the quantization step 5TPS (FIG. 9) of the quantization circuit 6 using the remaining amount data S17, By performing coarse quantization in the quantization circuit 6, the transmission image data S1
Reduce the amount of data in 6.

On the contrary, when the remaining amount of data in the transmission buffer memory 8 decreases to the allowable lower limit value, the remaining amount data S17 controls the step size of the quantization step 5TPS of the quantization circuit 6 to a small value. As a result, the quantization circuit 6
By performing fine quantization in the transmission image data 316, the amount of data generated for the transmitted image data 316 is increased.

III that the D invention tries to solve! ! ! In this way, in the conventional image data generation device 1, the image data encoding circuit 3 calculates the difference between the macroblock data S11 transmitted from the preprocessing circuit 2 and the predicted current frame data S12 transmitted from the predictive encoding circuit 4. , is sent to the conversion encoding circuit 5 as difference data 313, and is sent to the disc 1. j) Perform cosine transformation processing (Japanese Patent Application Laid-Open No. 62-61159)
By the way, when there is little movement of images between frames, the value of the difference data 513 after predictive coding by interframe coding is almost always zero, but depending on the performance of the analog/digital conversion circuit, it may be necessary to transmit it. In some cases, noise components without noise may be transmitted, making the noise noticeable.

For this reason, blocks with little image movement are less likely to be transmitted, and it is desirable from the standpoint of improving compression efficiency to actively determine such blocks as invalid blocks and not transmit them.

As such a treatment method, for example, Japanese Patent Application Laid-Open No. 62-206981
However, a method for determining an invalid block is not disclosed, and such a method cannot be directly applied when image data is subjected to vibration line processing for each macroblock.

The present invention has been made in consideration of the above points, and when the power of the unit block determined based on the transform coefficient obtained by discrete cosine transform encoding of the unit block does not exceed a predetermined threshold value. This paper attempts to propose a video signal encoding method that can further improve compression efficiency by not transmitting the converted data of the unit block.

8 Means for Solving the Problems In order to solve the problems, the present invention provides a video signal encoding method in which the digital video signal S21 is encoded with high efficiency by interframe encoding and transmitted.
The digital video signal S21 is divided into unit blocks Y0°, Y
e 1, Y,. , Y14, C1, and Cr, and calculate the power of the block from the transform coefficient Comft (i) from the beginning i = 1 to the predetermined number (i = N) of the discrete cosine transform encoded block. , the unit block Y, which compares the power with a predetermined threshold value and exceeds the threshold value. (Yo+, Y, ., YII, C5 or C,) is determined to be a significant block and transmitted, and the unit block Y0° (Yol, Y, ., y, ,, c
, or C,) are determined to be invalid blocks and are not transmitted.

The F-action discrete cosine transform encoded block power is converted from the transform coefficient c,, rt (i) to the unit block Y0゜, Y
, 3, Yl. , Y8, C, ,C, are sequentially obtained, and blocks whose power is larger than a predetermined threshold value are determined to be significant blocks and allowed to be transmitted, whereas blocks whose power is smaller than a predetermined threshold value are insignificant. By determining that it is a block and not allowing transmission, the compression efficiency of the digital video signal S21 can be further improved.

Embodiment G An embodiment in which the present invention is applied to a videophone will be described in detail below with reference to the drawings.

(G1) Overall configuration of image information transmission system In FIGS. 1 and 2, the color image information transmission system 21 is composed of an encoder 21A (FIG. 1) and a decoder 21B (FIG. 2). video signal VD,
, is preprocessed in the input circuit section 22, and then the analog/
In the digital conversion circuit 23, the transmission unit block data consisting of pixel data for 16 x 16 pixels, that is, the input image data S21 consisting of the pixel data of the macro block MB is sent to the pixel data processing system SYMI,
At the timing when pixel data is processed in units of macroblocks MB in each processing stage of the pixel data processing system SYMI, processing information data corresponding to the processed data is sequentially transmitted via the header data processing system SYM2. Thus, pixel data and header data are processed in the pixel data processing system SYMI and header data processing system SYM2, respectively, by the Vibrine method.

In the case of this embodiment, macroblock data sequentially sent out as input image data S21 is extracted from frame image data FRM by a method as shown in FIG.

First, one frame image data FRM is divided into 2 (horizontally) x 6 (vertically) block groups GOB as shown in FIG. 3(A), and each block group GOB is divided into block groups GOB as shown in FIG. As shown in FIG. 3(B), it is configured to include 11 (horizontally) x 3 (vertically) macroblocks MB, and each macroblock MB is 16 x 16 as shown in FIG. 3(C). Luminance signal data for pixels Y0
゜～Y3. (each consisting of luminance signal data for 8×8 pixels) and luminance signal data Y. Color difference signal data Cb consisting of color difference signal data corresponding to all pixel data of ~YI,
and C7.

In this way, the input image data S21 sent for each macroblock MB is given to the motion compensation circuit 25, and the motion compensation circuit 25 receives the motion detection control signal 522 given from the motion compensation control unit 26 provided in the Helada data processing system SYM2. In response to this, the pre-prediction frame data S23 in the pre-prediction frame memory 27 is compared with the input image data S21 to obtain motion vector data MVD (x) and MVD.
(y) is detected and supplied to the motion compensation control unit 26 as data of the first header data HDI (FIG. 4), and the motion compensation circuit body 25A applies motion vector data MVD (
By performing motion compensation for x) and MVD (y), predicted current frame data S24 is formed and is supplied to the image data encoding circuit 28 together with current frame data S25 consisting of input image data S21 that is currently being processed.

Here, the motion compensation control unit 26, as shown in FIG.
Transmission frame number data TRCoun representing the transmission order of
ter and its block group GOB (Figure 3 (A
)) Block group number data representing GOB add
The macroblocks MB that are sequentially transmitted to each processing stage of the pixel data processing system SYMI are displayed by adding macroblock number data MB address representing the macroblocks MB of the macroblocks MB address. Macroblock M to be processed
Flag data FLAGS representing the processing or processing format of B
and motion vector data Hν of the macroblock MB.
D(χ) and -νD (y), and difference data ΣIA-Bi representing their evaluation values are formed.

As shown in FIG. 5, the flag data FLAGS is designed to have a maximum of 1 word (16 bits) worth of flags, and the 0th bit contains the macroblock M to be processed.
A motion compensation control flag MConloff indicating whether or not B should be processed in motion compensation mode is set.

In addition, the first bit of the flag data FLAGS contains interframe/intraframe information indicating whether the macroblock MB to be processed should be processed in interframe coding mode or intraframe coding mode. Flag I
inter/Intra is set.

Further, a filter flag Filter onloff indicating whether or not to use the loop filter 25B of the motion compensation circuit 25 is set in the second bit of the flag data FLAGS.

Furthermore, the third bit of the flag data FLAGS contains a transmission flag Coded/Not- which indicates whether or not the block data Y0° to Cr (FIG. 3(C)) included in the macroblock to be processed is to be transmitted. coded can be set.

Further, the fourth bit of the flag data FLAGS can be set with a drop flawne flag indicating whether or not to drop frames of the macroblock MB to be processed.

Furthermore, the fifth bit of the flag data FLAGS contains a forced refresh flag Refresh on indicating whether or not to forcibly refresh the macroblock MB to be processed.
loff can be set.

Furthermore, the sixth bit of the flag data FLAGS contains a macroblock power evaluation flag MBP appreciat
e can be set.

Further, the difference data ΣIA-Bl is the current frame data 32
5, macroblock data A to be currently processed,
It represents the minimum value of the difference between the pre-prediction frame data S23 and the macroblock data B compensated by the motion vector for detection, so that the detected motion vector can be evaluated.

The image data encoding circuit 28 (FIG. 1) supplies the current frame data S25 given from the motion compensation circuit 25 as it is to the conversion encoding circuit 29 as difference data 326 in the intra-frame encoding mode, and in response to the frame In the inter-encoding mode, difference data S26 consisting of the difference between pixel data of the current frame data S25 and pixel data of the predicted current frame data S24 is supplied to the conversion encoding circuit 29.

The header data processing system SYM2 is provided with an interframe/intraframe encoding control unit 30 corresponding to the image data encoding circuit 28, and a motion compensation control unit 26.
An inter/intraframe flag Inter/In is set for specifying the encoding mode of the image data encoding circuit 28 based on the header data MDI supplied from the header data MDI and the calculation data S31 supplied from the image data encoding circuit 28.
tra (FIG. 5) and a filter flag F for controlling the operation of the loop filter 25B of the motion compensation circuit 25.
The data necessary to obtain the filter onloff (FIG. 5) is calculated and sent to the filter control unit 31 as the second filter data HD2.

As shown in FIG. 4, the second header data HD2 includes transmission frame number data T constituting the header data MDI.
RCounter ~ The power data Σ(A)'' ( L) and Σ(A)” (H
), Σ(A-B)"(L) and Σ(A-B)"(H
), Σ(A-FB)Z(L) and Σ(A-FB)”
(H) and Σ(A) are added in the interframe/intraframe coding control unit) 30.

Here, the power data Σ(A)"(L) and Σ(A)"
(H) represents the lower bit and upper bit of the sum of squares of the macroblock pixel data A of the current frame data S25, and represents the power data Σ(A-B)'' (L) and Σ(A-B
)" (H) is the lower order of the sum of squares of the difference A-B between the macroblock pixel data A of the current frame data S25 and the macroblock pixel data B of the predicted current frame data S24 formed without going through the loop filter 25B. represents the bit and the upper bit, and the power data Σ(A-FB)' (L
) and Σ(A-FB)” (H) is the current frame data S
25 macroblock pixel data A and loop filter 2
The power data Σ
(A) represents the sum of the macroblock pixel data A of the current frame data S25, and the data amount is expressed as a power value in order to evaluate the size of the data to be processed (the sum of squares is a value independent of the sign). ).

The filter control unit 31 performs an image data encoding process based on the second frame data HD2 passed from the interframe/intraframe encoding control unit 30 and the remaining amount data S32 supplied from the transmission buffer memory 32. Nr
It sends out an interframe/intraframe coding mode switching signal S33 to the loop filter 25B, and sends out a filter on/off signal S34 to the loop filter 25B, and together with this, indicates the contents of the filter on/off signal S34. The filter flag Filter onloff is added to the second Hellada data HD2 and the third Hellada data HD3 is added.
It is passed to the threshold control unit 35 as a threshold control unit 35.

Here, the filter control unit 31 first controls the image data encoding circuit 28 when the amount of data to be transmitted when performing interframe encoding processing is larger than the amount of data to be transmitted when performing intraframe encoding processing. Control to intraframe coding mode.

Further, the filter control unit 31 secondly controls the predicted current frame data S that has been processed in the loop filter 25B while processing in the interframe coding mode.
Predicted current frame data S2 that is not subjected to the processing from 24
If the difference value is smaller in 4, the rube filter 25B is controlled by the filter on/off signal S34 so as not to perform the filtering operation.

Thirdly, when the filter control unit 31 enters the forced refresh mode, it switches the image data encoding circuit 28 to the intraframe encoding mode using the interframe/intraframe encoding mode switching signal S33.

Furthermore, the filter control unit 31 fourthly detects when the transmission buffer memory 32 is in a state where there is a risk of overflow based on the remaining amount data 332 supplied from the transmission buffer memory 32 and performs a preventive process. The third radar data HD3 containing flags instructing what to do is sent to the threshold control unit 35.

In this way, the image data encoding circuit 28 encodes the difference data S2 in a mode that minimizes the difference between the current frame data S25 and the predicted current frame data S24.
6 is supplied to the transform encoding circuit 29.

As shown in FIG. 4, the third header data HD3 includes header data (D2 to transmission frame number data TRC).
block data Y in the filter control unit 31 while taking over motion vector data MVD (X) and MVD (y). ~ Filter flag for 6 bits corresponding to C1 Filter onlof
f is added.

The transform encoding circuit 29 is a discrete cosine transform circuit, and converts the coefficient value after the discrete cosine transform into 6
blocks Y0゜, Y01, Y,. ,Yl l,C
, , C, and is sent to the transmission block setting circuit 34 as converted encoded data S35 obtained by zigzag scanning.

The transmission block setting circuit 34 receives six block data Y sent out as converted encoded data S35. , ~C1
(FIG. 3(C)), calculate the sum of squares of up to n pieces from the first coefficient data, and use the calculation result as power detection data S36 to the threshold control unit 35.
give it to

At this time, the threshold control unit 35 compares the power detection data S3C with a predetermined threshold value for each block data Y0° to C1, and compares the power detection data S36 with a predetermined threshold value.
When CBPN is smaller than the threshold value, transmission of the block data is not permitted, and when it is larger, transmission permission data CBPN of 6 bits is generated and passed from the filter control unit 31. Third
The fourth radar data H is added to the radar data HD3.
D4 is passed to the quantization control unit 36, and the corresponding block data Y,
. ~Cr is caused to be sent to the quantization circuit 37 as transmission block patterned data S37.

Here, the fourth header data HD4 is the transmission frame number data τRC of the header data HD3, as shown in FIG.
outer~Filter flag Filter onlo
ff is taken over as is, and a 6-bit transmission permission flag CBPN generated in the threshold control unit 35 corresponding to blocks Y0° to C1 is added.

The quantization control unit 36 is the threshold control unit 3
A quantization step size control signal 538 is given to the quantization circuit 37 based on the fourth hellada data HD4 passed from the transmission buffer memory 32 and the remaining amount data S32 sent from the transmission buffer memory 32. is subjected to quantization processing with a quantization step size adapted to the data included in the macroblock MB, and quantized image data S39 obtained as a result at the output end of the quantization circuit 37 is supplied to the variable length encoding circuit 38.

Along with this, the quantization control unit 36, as shown in FIG. 4, respectively corresponds to the block data Y0° to C7 (FIG. 3 (C)) as the fifth header data 1D5 based on the header data HD4. Flag data FLAG
S and motion vector data MVD (x) and motion vector data MVD
(y) and arranged in series to form data, which is passed to the variable length encoding circuit 38 and the inverse quantization circuit 40.

Here, the header data HD5 is as shown in FIG.
Transmission frame number data TR of header data HD4
Counter ~ Macroblock number data MB ad
At the same time, the quantization control unit 36 inherits the quantization size data T and the flag data FLAGS for the block data Y0° to C7.
, motion vector data MVD (χ) and ■D Cy)
Add.

The variable length encoding circuit 38 performs variable length encoding processing on the Hellada data HD5 and the quantized image data 339 to form transmission image data S40, and supplies this to the transmission buffer memory 32.

The variable-length encoding circuit 38 variable-length encodes the block data Y, .
When "elopement" or "transmission not possible" is specified based on S, the block data is transferred to the transmission image data 54.
Perform processing such as discarding it without sending it as 0.

The transmission buffer memory 32 accumulates the transmission image data S40, reads it out at a predetermined transmission speed, combines it with the transmission audio data 341 sent from the audio data generator 42 in the multiplexer 41, and sends it to the transmission line 4.
Send to 3.

The dequantization circuit 40 dequantizes the quantized image data S39 sent from the quantization circuit 37 based on the header data HD5, and then supplies the dequantized data S42 to the inverse transform encoding circuit 43. Inverse transform encoded data S
43 and then supplied to the decoder circuit 44, and the encoded difference data S44 representing image information sent out as transmission image data 540 is stored in the pre-prediction frame memory 2.
7 to be supplied.

At this time, the pre-prediction frame memory 27 uses the encoded difference data S44 to perform a correction operation on the pre-prediction frame data stored up to that point and stores it as new pre-prediction frame data.

Thus, according to the encoder 21A having the configuration shown in FIG. 1, the pixel data is subjected to vibe line processing in macroblock units in the pixel data processing system SYM1 based on the header information supplied from the header data processing system SYM2. , the header data processing system S is synchronized with this.
By receiving and passing the header data in YM2, pixel data can be adaptively processed as necessary by adding or deleting header data as necessary at each processing stage of the header data processing system SYM2.

As shown in FIG. 2, the decoder 21B transfers the transmission data transmitted from the encoder 2]A via the transmission path 43 to the transmission buffer memory 52 via the demultiplexer 51.
At the same time, the transmitted audio data S51 is received by the audio data receiving device W53.

The image data received in the transmission buffer memory 52 is separated into received image data S52 and header data HDII in a variable length inverse transform circuit 54, and inversely quantized into inverse quantized data S53 in an inverse quantization circuit 55, and then converted into an inverse transform code. The data is subjected to discrete inverse transformation processing in the encoding circuit 56 and is inversely transformed into inversely transformed encoded data S54.

This inversely transformed encoded data S54 is given to the decoder circuit 57 together with the header data HD12 formed in the inverse quantizer 55, and is stored in the frame memory 58 as encoded difference data S55.

The encoded difference data S is stored in the frame memory 58.
The image data transmitted based on 55 is decoded, and the decoded image data 356 is converted into an analog signal in the digital/analog conversion circuit 59 and then sent out as an output video signal VDout via the output circuit section 60. be done.

(G2) Processing in the transmission block setting circuit 34 The transmission block setting circuit 34 processes the discrete cosine transform coefficients C,-=t (i ), the macroblock power MBP is calculated by the following formula, (N=1.3.6.10.15
．． 21.2B, 36.43.49.54.5B, 61.
63, 64) 6 block data Y, respectively, based on (1). ~C,
(Figure 3 (C)).

Incidentally, the discrete cosine transform circuit that constitutes the transform encoding circuit 29 performs the discrete cosine transform using the following formula: F (u, v) b π cos[(2y+1) ・V・ ]6 The discrete inverse transform circuit that executes and forms the inverse transform encoding circuit 56 has the following formula: f (x, y) cos ((2x+1) ・U・ 6 ) π cos ((2y+1) ・V ...(3) Execute discrete cosine inverse transformation by:

Here, x and y represent the coordinates of a hundred elements in the macroblock (the coordinates of the upper left corner are (0, 0)), and U and ■ represent the coordinates of coefficients during discrete cosine transformation.

Also, when U and V=O, in other cases, C(u) C(v) = 1...
It becomes like (5).

In practice, the transformation in equation (2) is performed by horizontally transforming the image data matrix X in the transform encoding circuit 29, where After the converted image data x c-' is obtained by doing this, a converted image data matrix C(X)C-' is obtained by next performing vertical conversion processing.

The thus obtained transformed image data matrix C(X)C-1 has the transformation coefficients C, , (1), C, as shown in FIG.
,,,,(2) ,C,,tf (3”)...C,,
It can be expressed as a transformation coefficient matrix consisting of an 8×8 matrix of The data is read out while scanning in a zigzag pattern in the order of i=1.2.3...64.

In this way, one block of image data is sequentially transformed into transformation coefficients co*frN) (i=1 to 64) constituting a transformation matrix, which are supplied to the quantization circuit 37 as transmission data arranged in time series. It turns out.

By the way, in practice, when a transform coefficient matrix as shown in FIG. 6 is obtained by performing discrete cosine transform on interframe encoded image data, the transform coefficients Co,rt (s) in the upper left corner (i.e., low-order conversion factor)
Since data representing the rough shape of the image is collected in , power is concentrated in
t (i) (that is, high-order transformation coefficients) collects noise components and data representing details of the image, and tends not to produce significant information.

Therefore, the value of N is set to N-1, 3, 6, 1O215,21,28 so that the macroblock power MBP expressed by equation (1) is equal in the horizontal and vertical directions.
, 36, 43, 49, 58, 61, 63, 64 to the cumulative addition X value of each scan column of the conversion coefficient matrix,
Obtained as the sum of squares from the beginning of the block to the Nth coefficient (
This means that the amount of significant information is large in the upper left corner where significant information tends to occur).If this sum of squares is compared with a threshold value Threshold, which is a predetermined value, the image to be transmitted can be determined. It is possible to determine whether the data contains a predetermined amount or more of significant information.

For example, if the value of N is set to N-36, six pieces of block data Y in the macroblock MB are sent out sequentially. , Y, , , Y, , , Y83, C, , the first block data Y, among C,.

The macroblock power MBP of is 8X8'i! Transformation coefficient Ceeffl obtained by discrete cosine transformation of the element
(1) Among (i-1 to 64), the macroblock power MBP is the transformation coefficient Co from the beginning to the 36th
It is obtained as the sum of squares of effl (1), and
Similarly, the second, third, fourth, fifth, and sixth block data Y01, Y, and so on. , Yo, Cb, C- macroblock power MBPt , MBPs , MBP4, M
BPs and MBP are sequentially determined and sent to the threshold control unit 35 as power detection data 536, respectively.

(G3) Operation of threshold control unit 35 The threshold control unit 35 receives the first block Y as the power detection data S36 from the transmission block setting circuit 34. The macroblock power MBP of is compared with a preset threshold value Threshold.

At this time, the threshold control unit 35 sets the macroblock power MBP to a predetermined threshold value Thresh.
If it is determined that the block data is larger than old, the block data Y,. is considered to be a significant block, and the transmission is permitted, and logical "l" data is written in the significant/insignificant flag P1 of the block data Y0°.

On the other hand, block data Y. When it is determined that the macroblock power MBP, of the block Y, is smaller than the threshold value Threshold, the corresponding block Y,. is an invalid block, and does not allow transmission, and writes logical "0" data to the significant/insignificant flag P1.

The threshold control unit 35 controls macroblock powers MBP, .about.
Regarding MBP, the macroblock power MBP is determined in the same manner as in the above case.

~MBP, is larger than the threshold value Threshold, and sets the second to sixth significant/insignificant flags P2 to P6 to logical "1" data (meaning it is a significant block) or logical "0'' data (meaning that it is an invalid block) is written, and a transmission permission flag CBPN is formed based on the following formula (7).

The threshold control unit 35 (FIG. 4) receives the third radar data HD3 passed from the filter control unit 31.
Transmission enable/disable flag cBPN consisting of 1 and 6 bits (e.g. r
llololj) and add the fourth Herada data HD4
It is passed to the quantization control unit 36 as .

The quantization control unit 36 sets the transmission permission flag CBPN to the block data Y, based on the fourth hellada data HD4.
. The transmission flags "1", "1", "0", "1", "0", '
It is written as IJ and sent to the variable length encoding circuit 38 as header data HD5.

The variable length encoding circuit 38 receives input block data Y0.
When performing variable length encoding on ~C7, when the transmission flag is logical rl and data based on the corresponding flag data FLAGS, it is transmitted as transmission image data 340, and logical rQ,
Processes such as discarding data instead of sending it.

For example, block data Y 6 e ,, Y o I
% Y + * s Y + l The transmission flags of %C,,C, are 'lj, 'I', '0', '1', '
0" and "1", the variable length encoding circuit 38 outputs block data Y, respectively. ,Yet sends,Y,. does not transmit, Y++ transmits, Cb does not transmit, and C7 transmits.

According to the above configuration, the sum of squares of the transform coefficients Comtt (i) after discrete cosine transformation is obtained from the first coefficient (i=1) of the block to the Nth coefficient, and this is compared with the threshold value Threshold, which is a predetermined value. By doing so, it is determined whether the block data Y0° to C2 to be transmitted is a significant block or an meaningless block, and based on this, the transmission or non-transmission of the blocks Y0° to C7 is controlled. Image data compression efficiency can be improved.

In this way, blocks with many noise components can be further removed,
Image data with good image quality can be transmitted more efficiently.

(G4) Other embodiments (1) In the above embodiment, the macroblock power MBP is calculated after the transformation coefficient C-tt (i)! From 1f-1 to cumulative addition value i-N (
N-1, 3, 6, 10, 15, 21, 28, 36, 43
, 49, 58, 61, 63, 64), but the present invention is not limited to this.
The macroblock power MBF may be set by the sum of squares of coefficients up to N-th order other than the cumulative addition value of each scan column, such as the sum of squares of -1 to 40th-order coefficients.

(2) In the above embodiment, the macroblock power M
BP is the conversion coefficient Comft (i) starting i = 1 to N
We have described the case where it is set by the sum of squares up to the next coefficient, but
The present invention is not limited to this, but can be applied to the case of equal products set as n-th power sums.

(3) In the above embodiment, the threshold value Thr
Although the case has been described in which esbold is set to a predetermined value in advance, the present invention is not limited to this.
It is also possible to control ld.

(4) In the above embodiment, after the macroblock MB is quantized in the quantization circuit 37, the flag data FLA of the Herada data HD5 is processed in the variable length encoding circuit 38.
Based on GS, block data Y,.

Although the case of controlling the transmission and non-transmission of the block data Y0° to C7 (FIG. 3(C)) has been described, the present invention is not limited to this.
Non-transmission may also be controlled.

(5) In the above embodiment, a case was described in which the header data and image data are processed in the header data processing system and the image data processing system, respectively, but the present invention is not limited to this, and the header data is transmitted together with the image data. You may also do this.

(6) In the above-described embodiments, the case where the present invention is applied to a video telephone is described, but the present invention is not limited to this, and can be widely applied to the case of transmitting image information.

H Effects of the Invention As described above, according to the present invention, the sum of squares of transform coefficients after discrete cosine transformation is obtained from the beginning of the block to a predetermined number, and this is compared with a predetermined threshold value, thereby calculating the sum of squares of the transform coefficients for each block. By determining whether block data is significant or not and actively not transmitting invalid blocks, it is possible to efficiently transmit images with good image quality.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing an encoder and a decoder constituting an image information transmission system to which the video signal encoding method according to the present invention is applied, FIG. 3 is a route map showing the structure of frame image data, and FIG. The figure is a block diagram showing the header processing system of Fig. 1, Fig. 5 is a route map showing the configuration of the flag data of Fig. 4, and Fig. 6 is a diagram showing the conversion coefficient matrix.
FIG. 7 is a route diagram for explaining intra-frame/inter-frame encoding processing, FIG. 8 is a block diagram showing a conventional image data generation device, and FIG. 9 is a chart showing its quantization step. 21... Image information transmission system, 21A...
... Encoder, 21B ... Decoder, 25
... Motion compensation circuit, 27 ... Pre-prediction frame memory, 28 ... Image data encoding circuit, 29 ... Transformation coding circuit, 30 ...・・・・・・
Interframe/intraframe coding control unit, 31...
... Filter control unit, 32 ... Transmission buffer memory, 34 ... Transmission block ffl
Foot circuit, 35...Threshold control unit,
36...Quantization control unit, 37...
- Quantization circuit, 38...Variable length encoding circuit.

Claims (1)

[Claims] A video signal encoding method for highly efficient encoding and transmission of a digital video signal by interframe encoding, comprising discrete cosine transform encoding of the digital video signal for each unit block; Determine the power of the encoded block from the transform coefficients from the beginning to a predetermined number, compare the power with a predetermined threshold value, determine the unit block exceeding the threshold value as a significant block, and transmit it. A video signal encoding method characterized in that a unit block that does not exceed the threshold value is determined to be an invalid block and is not transmitted.