JPH03285429A - Signal transmission system - Google Patents

Abstract

PURPOSE:To reduce a heat generation loss at a current signal return transistor by providing a short circuit detection bit at the head of a synchronizing signal to be sent out during a signal return period and inhibiting a return signal to be sent out to a central processing unit based on the detection output of a short circuit abnormality detecting means provided at a signal repeater. CONSTITUTION:In a slave activation mode, a short circuit detection bit SB is provided on the head side of one block T in a synchronizing signal SYNC to be sent during the return period. In a current signal detection circuit 18, a current mode signal is converted to a voltage and taken out by a resistor 19 connected between the incoming terminal of a two-wire transmission line 3 and a ground. Synchronously with the detection of the current mode signal, a CPU 5 outputs a timing signal for polarity inversion at a high level to a drive circuit 13. In the drive circuit 13, a voltage signal RV inverting the polarity is returned to the two-wire transmission line 3. On the other hand, the CPU 5 decides transmission line short circuit abnormality according to whether the current signal CS is superimposed to the short circuit detection bit SB or not, and when the short circuit is detected, the output is stopped for a fixed period.

Description

Detailed Description of the Invention Purpose of the Invention (Industrial Application Field) The present invention connects a central processing unit, a signal repeater, and a terminal device with a pair of transmission lines, and connects the central processing unit to the terminal device side. The present invention relates to a signal transmission system for transmitting control data to a terminal device and monitoring data from a terminal device side to a central processing unit.

(Prior art) For example, in a signal transmission system that constitutes a remote lighting control system, etc., in order to control the load connected to the terminal, a central processing unit (for example, a main operation panel) sends the terminal device address and control data. Transmission data is sent to a terminal device (for example, a dimming terminal device), and from the terminal device side, monitoring data indicating the status of the load (for example, a lighting load or a dimming level setting device) is sent to the central control device along with its own address. This makes it possible to control and monitor the load.

In such a signal transmission system, data is sent from the central processing unit to the terminal in voltage mode consisting of bipolar pulses of, for example, =24, and data is transferred from the terminal to the central processing unit in current mode. It is carried out in Sending of the current mode signal on the terminal device side is done by shorting the two-wire transmission line with a resistor in synchronization with the voltage mode synchronization signal sent from the central processing unit. is returned to the central processing unit.

Furthermore, when current mode transfer data is sent from the terminal device, the central processing unit returns a voltage signal with inverted polarity to the terminal device in synchronization with the detection of the transfer data.

FIG. 7 is a timing chart showing the transmission and reception of this signal. mode signal C3, (c) is received by the central processing unit after a delay τ due to transmission, t-current signal C8, (d) is a polarity reversal that is sent back from the central processing unit in synchronization with the reception of this current signal C3. voltage signal RV
are shown respectively.

In this way, sending back the polarity-inverted voltage signal RV from the central processing unit to the terminal side in synchronization with the reception of transfer data from the terminal side ensures that the data is sent to the central processing unit without error on the terminal side. This has the advantage of being able to confirm that something has happened.

Examples of signal transmission systems that enable data to be sent and received accurately without errors by returning such polarity-inverted voltage signals RV from the central processing unit are disclosed in, for example, Japanese Patent Application No. 63-218031-3. Some examples include those disclosed in the public relations publication of Japanese Patent Application No. 1-17684.

(Problem to be Solved by the Invention) However, in such a signal transmission system, if the transmission line output transferred from the terminal side is short-circuited for some reason,
Since the current signal C8 is superimposed on all bits of the synchronization signal 5YNC sent from the central processing unit,
It becomes impossible to detect the presence or absence of data transferred from the terminal side.

Therefore, in the past, a part of the transferred data was supplied with a current mote signal C.
A signal bit (short-circuit detection bit SB) which is always 0 without carrying 3 is provided on the terminal side, and by checking this short-circuit detection bit S8, a short-circuit abnormality can be detected in the central processing unit.

If the current mode signal C3 is also detected in the short circuit detection bit 8B, the central processing unit determines that a transmission line short circuit has occurred, and can perform predetermined transmission line short circuit processing.

In the conventional signal transmission system, the short circuit detection and node SB are provided at the tail side of one section T of the transmission data, as shown in the transmission format in FIG. Furthermore, the 8th
In the figure (a> is the synchronization signal 5YNC1 sent from the central processing unit when the central processing unit is waiting for the slave activation to wait for the spontaneous transmission of monitoring data from the terminal. (b) is the synchronization signal 5YNC1 that is monitored by the terminal by the slave activation Return data sent back from the central processing unit when data is transferred; (c) is transmission data sent from the central processing unit when the parent starts to control the terminal; (d) shows the terminal when the parent starts. Each of the figures shows return data sent back from the central processing unit when ACK data is returned from the device side.

By the way, in this way, short circuit detection bit S8 is set to transmission data 1.
If it is provided at the tail end of section T, the current signal C3 will be superimposed on all of the bits until the short circuit detection bit S8 is detected, and the signal repeater that relays the data transferred from the terminal will be A current signal return transistor 54 provided
The heat loss of the return transistor increases as it is repeatedly turned on intermittently. Particularly in the child activation mode, since the number of bits on which the current signal C3 is superimposed is large, the heat loss in the return transistor becomes large.

Conventionally, therefore, the second heat loss was dealt with by using a current return transistor with a large collector loss.

The present invention was proposed to solve these problems, and an object of the present invention is to provide a highly reliable signal transmission system that does not cause heat loss in the current signal return transistor when the transmission line is short-circuited. .

[Structure of the invention]

(Means for Solving the Problem) In order to achieve the above object, a signal transmission system according to the present invention connects a central processing unit, a signal repeater, and a terminal device by a pair of transmission lines, and the central processing unit connects the terminal device to a central processing unit. During the signal return period from the terminal side, a synchronization signal corresponding to the return timing signal is sent in voltage mode, and from the terminal side, the return signal in current mode is centrally processed via a signal repeater in synchronization with this synchronization signal. In what is sent to the device, a short circuit detection bit that prohibits the sending of the return signal in the current mode is provided at the beginning of the synchronization signal sent during the signal return period in order to detect transmission line short-circuit abnormalities, and the above-mentioned The signal repeater includes short-circuit abnormality detection means for detecting short-circuit abnormalities in the transmission line, and, based on the detection output of the short-circuit abnormality detection means, sends the return signal after the short-circuit detection bit except for the short-circuit detection bit to the central processing unit. The present invention is characterized by providing a means for prohibiting return shipment.

(Function) According to the above-described configuration, since a short circuit detection bit is provided at the beginning of the synchronization signal during the return period, if the short circuit abnormality in the transmission line can be detected by the short circuit abnormality detection means using this detection bit, the short circuit abnormality is detected by the return prohibition means. It is possible to prohibit the sending of return signals after the short circuit detection bit except for the short circuit detection bit.

(Example) Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

The block diagram in FIG. 1 is an overall configuration diagram showing one embodiment of a signal transmission system according to the present invention.

In this figure, a central processing unit 1, which is a sharp device, and a plurality of terminal devices 2, which are child devices, are connected by a two-wire transmission line 3, and the two-wire transmission line 3, which sandwiches the terminal device 2, is used for signal amplification, A signal repeater 4 is provided for correcting waveform distortion and the like. If this signal transmission system is a remote lighting control system, the central control device 1 corresponds to a main operation panel, and the terminal device 2 corresponds to a dimming level setting device or a dimming terminal device connected to a lighting load.

This signal transmission system has a short circuit detection bit SB at the beginning of one section T of the synchronization signal 5YNC sent during the return period in the child activation mode, as shown in the signal transmission former node in Fig. 2. A short-circuit abnormality in the transmission line output is detected at the beginning of one section Tcr of the synchronizing signal 5YNC. ) can be prevented from generating unnecessary heat. In the parent activation mode, a short circuit detection bit SB is provided at the beginning of one section T- of the synchronization signal 5YNC corresponding to the ACK return period.

Note that FIG. 2 corresponds to the above-mentioned FIG. 8, and in (a) and (b) in the child startup mode, area 01 is a data area where the self address of the terminal device 2 is written, and area D2 is the data area where the self address of the terminal device 2 is written. Area D in (c) and (d) in parent startup mode corresponds to the data area where the monitoring data sent from is written.
3 corresponds to a data area in which the destination terminal address is written, area D4 corresponds to a data area in which control data is written, and area D5 corresponds to an ACK data area for requesting an ACK (acknowledgment) from terminal 2.

Note that a short pulse corresponds to data 0゛, and a long pulse corresponds to “1”.
Corresponds to ゛.

Next, transmission data including address data and control data is sent using the bipolar pulse voltage mode, and the synchronization signal 5Y
The specific configuration of the central control unit 1, which sends out the NC and returns the voltage signal RV whose polarity is inverted when the current mode signal is transferred from the terminal device 3 side, will be described with reference to FIG.

A clock circuit 6 that generates an operating clock signal of a predetermined frequency and a reset circuit #r7 that outputs a reset signal for initial state setting are connected to the CPU (central processing unit) that functions as a signal processing unit. has been done. In the power supply circuit 8 to which commercial alternating current power (AC power) is supplied, a DC power supply=VS for bipolar pulse generation and a DC power supply VC for intra-circuit power supply are produced. A zero-crossing detection circuit 12 comprising a transformer 9, a diode bridge 10, an amplifying transistor 11, etc. detects a zero-crossing of the AC power supply, and this zero-crossing detection signal is supplied to the CPU 5.

Transmission data outputted from the data output terminal of the CPU 5 in a predetermined format is converted by the drive circuit 13 into bipolar pulses of, for example, ±24V and outputted to the two-wire transmission line 3.

In the zero-crossing signal sending circuit 17, which consists of an analog switch 14, a photocoupler 15, and a diode bridge 16, the transmission line 3 is temporarily short-circuited at the beginning of one data section T in synchronization with the zero-crossing detection signal. A necessary zero-crossing signal 23 is created, and this zero-crossing signal IS is sent to the transmission line 3.

In the current signal detection circuit 18, the current mode signal transferred from the terminal device 2 side is converted into a voltage by a resistor 19 connected between the end of the return path of the two-wire transmission line 3 and ground, and is taken out. This detection signal is converted into digital data by the A/D converter 20 and supplied to the CPU 5. The CPU 5 outputs a high-level ("°H" level) polarity inversion timing signal to the drive circuit 13 in synchronization with the detection of the current mode signal. The drive circuit 13 receives this timing signal, inverts the polarity of the bipolar pulse, and returns the polarity-inverted voltage signal RV to the two-wire transmission line 3. Further, in the CPU 5, the current signal C is set to the short circuit detection bit SB.
A transmission line short circuit abnormality is determined based on whether or not 8 is superimposed, and if a short circuit is confirmed, a protective measure is taken to stop output for a certain period of time.

Next, the specific configuration of the terminal device 2 shown in FIG. 4 will be explained.

A clock circuit 21a that generates an operating clock signal and an address setting circuit 22 that sets a self address are connected to the CPU 21, which functions as a signal processing section.

In the receiving circuit 23 connected to the two-wire signal line 3, "0" and "1" in the voltage mode consisting of bipolar pulses are low (° "L") and high ("H") with reference to 0. ) T
It is converted into a TL level voltage signal and supplied to CPtJ21. The CPU 21 analyzes the input data from the receiving circuit 23, determines the address and decodes the control data, and returns a current mode return signal C3 to the central processing unit 1 as necessary. In the case of the child activation mode, an internal process is performed to generate a short circuit detection bit S8 that prohibits the return of the current mode signal after a certain start signal SS at the beginning of one section of the transmission data. In the parent activation mode T', processing is performed to create this short circuit detection bit 3B at the beginning of the ACK area.

In the diode bridge 24 to which the two-wire transmission line 3 is connected, full-wave rectification of the bipolar pulse is performed, and in the power supply circuit 25 to which this rectified output is supplied, a DC power supply Vc to be supplied to the circuit is created.

The zero cross signal 2S is received by a receiving circuit 26 connected to the diode bridge 24 and supplied to the CPU 21.

The switch transistor 28 configuring the transmitting circuit 27 is
It is electrically connected by the H" level signal (corresponding to +1111) of CPt, :21 outputted during data transfer from the terminal device 2 to the central processing unit 1, and at this time, the resistor 29 is shorted between the lines of the two-wire transmission line 3. A current mode return signal C3 is then returned to the two-wire transmission line 3.

At the switch i30 connected to the CPU 21, the load 3
Various settings such as on/off and control level of the CPU 1 are performed, and the setting data is transferred as monitoring data to the central processing unit 1 in the current mode.

In the dimming circuit illustrated as the load-side circuit 32, the lighting load 31 is dimmed based on the zero-cross signal ZS and control data sent from the central processing unit 1.

Next, a specific configuration of the signal repeater 4 shown in FIG. 5 will be explained.

In the power supply circuit 33 to which AC power is supplied, a DC power supply -1-Vs for supplying power to the output transistor unit 34 that generates bipolar pulses and a DC power supply ■p for supplying power to the transmitting and receiving circuit units are created. .

In the diode bridge 35 to which the two-wire transmission line 3a on the central processing unit 1 side is connected, the bipolar pulse is full-wave rectified, and the rectified output is supplied to the power supply port F#136 for supplying power to the control circuit section. A DC power supply VC is created.

The bipolar pulse voltage mode signal transmitted through the transmission line 3a is
The LED 37 is transmitted by a photocoupler 38 connected between one side of the transmission [3a and ground], and this coupler output from a phototransistor 39 is converted into a bipolar pulse by a drive circuit 40 and an output transistor section 34 and sent to a terminal device. The signal is sent out to the two-wire transmission line 3b on the second side.

Moreover, the voltage mode transmission signal of the bipolar pulse is transmitted through the transmission line 3a.
is received by a receiving circuit 41 connected to this receiving circuit 4.
1, the voltage mode signals "0" and "1" are converted into a voltage signal of "L11.1"H" with reference to 0, and the voltage signal is supplied to the received signal input terminal of the control section 42. Figure 6 (a)
indicates a received signal (synchronous signal 5YNC) input to this input terminal in the child activation mode. When this received signal is in the child start mode, the first bit following the start signal SS is the short circuit detection bit S as shown in Fig. 2 (a>, (b)).
B, and the second and subsequent bits form the address data area D1 following the mode signal. In synchronization with this received signal, the control unit 42 outputs a timing signal RP (see FIG. 6(b)) indicating a return possible period to an AND gate 43, which will be described later.

The zero-crossing signal ZS is detected by a zero-crossing detection circuit 44 connected to the DC output of the diode bridge 35, and the detection signal is supplied to the drive circuit 40 via a photocoupler 45. The drive circuit 40 performs processing to temporarily interrupt the supply of output to the output transistor section 34 in synchronization with this detection signal, and reproduces the zero cross signal ZS.
It is sent to the two-wire transmission line 3b.

The return signal in current mode from the terminal device 2 side is converted into a voltage signal by a resistor 46 connected between the return end of the two-wire transmission line 3b and ground, and shaped by a receiving circuit 47 to which this voltage signal is supplied. It is converted into the voltage signal of IILIllH11. The reception output of the reception circuit 47 is supplied to one input terminal of AND gates 43 and 49 via a photocoupler 48, respectively. Here, if the two-wire transmission line 3b on the terminal device 2 side is short-circuited, the short-circuit detection voltage taken out from the photocoupler 48 will always be at the ``+Hi'' level as shown in FIG. 6(e). Therefore, the output of the AND gate 43 to which the returnable section timing signal RP is supplied is always "°H" when the timing signal RP is "°H".
becomes H, and this gate output is supplied to one input terminal of the AND gate 50.

In addition, the control unit 42 outputs a first bit timing signal TSI (
6(c)) is supplied to the other input terminal of the AND gate 49, and the second bit timing signal D, which is at "H'° in the interval from the rising edge of the first bit to the rising edge of the second bit, is supplied to the other input terminal of the AND gate 49. S2 (see Figure 6(d)) is
It is supplied to the clock terminal of flip-flop 51. As a result, when the transmission line is short-circuited, the first bit timing signal TS1 passes through the AND gate 49 and is supplied to the clock terminal of the flip-flop 52. Here, the AND gate 49 constitutes short circuit abnormality detection means. Also, the control section 4
2, a negative logic clear signal CP synchronized with the falling timing of the start signal SS is supplied to the clear terminal of each flip-flop 51 and 52.

The data input terminal of the flip-flop 52 is always “H”.
The Q output of this flip-flop 52 is supplied to the data input terminal of the flip-flop 51. Also, the Q of flip-flop 51
The output is supplied to the input terminal of AND gate 50.

Here, the circuit section 56 constitutes a return prohibition circuit.

Therefore, the Q output of the flip-flop 51 is as shown in FIG.
As shown in f), the second and subsequent bits become the °''L level return prohibition signal IP, and this prohibition signal IP is supplied to the other input terminal of the AND gate 50.As a result, when the transmission line is short-circuited, the The pulse output of the AND gate 43 at “H”° passes through the AND gate 50 only when the return timing signal RP is “H”, and the voltage signal R3 corresponding to the return signal is shown in FIG. As shown, return is prohibited for the second and subsequent bits, and only the return signal of the short circuit detection bit is returned to the two-wire transmission line 3a via the return circuit 53.

Here, this return diagram #I53 is the diode bridge 35
A current signal return transistor 5 connected between the DC terminals of
When the signal is returned, this transistor 54 is turned on and the DC terminals are short-circuited by the resistor 55, and the return signal C5 in the 1E flow mode is transmitted to the 2-wire transmission line 3.
returned to a.

Furthermore, transmission, IJ! 3b is not short-circuited, the output of the AND gate 49 is always kept at the L level, so the Q output of the flip-flop 51 is always kept at the H level, and the current mode signal C5 is normally sent to the central processing unit. It is sent back to the first side.

In the parent activation mode, the above-mentioned operation is performed from the beginning of one section of the synchronization signal 5YNC corresponding to the ACK area, and when the transmission line is short-circuited, the current of the short circuit detection bit SB provided at the beginning of one section is Only the mode signal C3 is now returned to the central processing unit 1.

In this way, in the above signal transmission system, by providing the short-circuit detection bit SB at the beginning of the synchronization signal 5YNC, it is possible to send back only the current signal riding on the short-circuit detection bit S8 from the signal repeater 4 when the transmission line is short-circuited. , heat loss in the current signal return transistor 54 can be almost eliminated.

〔Effect of the invention〕

As explained above, according to the present invention, since the short circuit detection bit is provided at the beginning of the synchronization signal during the return period, when a transmission line short circuit abnormality is detected by the short circuit abnormality detection means of the signal repeater using this detection bit, , transmission of subsequent return signals except for the short circuit detection bit is prohibited by the return prohibition means.

Therefore, when the transmission line is short-circuited, the return signals other than the short-circuit detection bit do not pass through the current signal return transistor of the signal repeater, and the current signal return transistor does not generate heat unnecessarily.

This makes it possible to use a return transistor with a small capacity, and also improves the reliability of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the signal transmission system according to the present invention, FIG. 2 is a diagram showing the signal transmission format in this signal transmission system, and FIG. 3 is a diagram showing the configuration of the central processing unit of the signal transmission system. 4 is a circuit diagram showing the configuration of a terminal device that makes up the above signal transmission system, FIG. 5 is a circuit diagram showing the structure of a signal repeater that makes up the above signal transmission system, and FIG. An operational waveform diagram for explaining the operation of a signal repeater, Figure 7 is a waveform diagram for explaining a current mode signal and a voltage signal with reversed polarity, and Figure 8 is a signal transmission format in a conventional signal transmission system. It is a diagram. 1...Central processing unit 2...Terminal device 3...2-wire transmission line 4...Signal repeater 5.21...CPU
13,40...Drive circuit 18...Current detection circuit 19.46...Resistor 20 for current detection
...A, /D converter 22...Address setting switch 24.35...Diode bridge 27...Sending port 71 2B...Switch transistor 29, 55...Resistance 30 for shorting between lines ...Switch circuit 31 for various settings...Lighting load 32...Load side circuit 34
... Output transistor section 36 ... Power supply circuit 37 ... LEDs 38, 4
5.48... Photocoupler 39... Phototransistor 41... Receiving circuit 42... Control section 43, 4
9.50...And Gate 471. =Receiving circuit 51.52 Mountain flip-flop 53...Return circuit 54...Current signal return transistor

Claims (1)

[Claims] A central processing unit, a signal repeater, and a terminal device are connected by a pair of transmission lines, and the central processing unit generates a synchronization signal corresponding to a return timing signal during a signal return period from the terminal device side. Transmission line short-circuit abnormalities can be detected in a signal transmission system in which the signal is sent in voltage mode, and the terminal side sends a return signal in current mode to the central processing unit via a signal repeater in synchronization with this synchronization signal. In order to do this, a short-circuit detection bit that prohibits the transmission of the return signal in the current mode is provided at the beginning of the synchronization signal sent during the signal return period, and the signal repeater has a short-circuit detection bit that prohibits the transmission of the return signal in the current mode. The present invention is characterized in that it is provided with a detection means and a return prohibition means for prohibiting the sending of the return signal after the bit excluding the short circuit detection bit to the central processing unit based on the detection output of the short circuit abnormality detection means. Signal transmission system.