JPH03285409A - Amplifier - Google Patents

Abstract

PURPOSE:To maintain the linearity of an output voltage over a wide range to an input voltage of a wide range by obtaining the output voltage by switching plural amplifier circuits by a switch means in a state the input voltage range is made common for the plural amplifier circuits. CONSTITUTION:In this amplifier, when the input voltage is weak, a switch means 4 connects a differential step B to an output step 5 and applies the output to the output step 5 and a differential step A, however, is not operated yet. When the input voltage is gradually increased, the differential steps A and B are operated together and turned to the state of maintaining the linearity of the output voltage. When the switching point set in advance of the switch means 4 comes over in the state of operating the differential steps A and B together, the switch means 4 switches the connection on the differential step A side from the differential step B to the output step 5. At such a time, since one input terminal of the differential steps A and B is connected through a feedback line to the output terminal of the output step, the deviation of the output voltage at the time of switching can be suppressed at a minimum.

Description

[Detailed Description of the Invention] [Summary] Regarding an amplifier, particularly an amplifier that can maintain output voltage linearity over a wide range of input voltages, the present invention relates to an amplifier that can maintain output voltage linearity over a wide range of input voltages. A plurality of amplifier circuits each having a different input voltage range that can provide a stable output with respect to the input voltage,
switch means for selecting one of the output terminals of the plurality of amplifier circuits according to a selection signal, and in a state where the input voltage range of the amplifier circuits is common, the switch means switches the plurality of amplifier circuits. and get the output voltage.

[Industrial application field]

The present invention relates to an amplifier, and particularly to an amplifier that can maintain output voltage linearity over a wide range of input voltages.

[Prior Art] As a conventional amplifier, there is an amplifier as shown in FIG. 5(a). This amplifier consists of a differential stage, an output stage, and a feedback line that feeds back the output voltage of the output stage to one input of the differential stage.
It constitutes a voltage follower circuit.

Specifically, the differential stage includes a current mirror circuit consisting of an enhancement type P-channel MOS transistor P9゜PIO, and an enhancement type current mirror circuit that controls the current from the current mirror circuit in response to the input voltage input to the gate. n-channel MOS) transistor N9. N
IO and an enhancement type n-channel MO3I- whose gate receives a constant voltage from a bias circuit (not shown).
The constant current source is composed of a transistor Nll.

The output stage consists of an enhancement-type p-channel MOS transistor pH connected in series between the high-potential power line CC and the low-voltage power line SS, whose gate receives the output of the differential stage, and a bias circuit (Fig. It consists of an enhancement type n-channel MOS (not shown) which receives constant voltage from a constant current source section consisting of a transistor N12,
OS) An output terminal 15 is provided at the drain of the transistor pH. Then, the output terminal 15 and the n-channel MOS
The gate of transistor N9 is connected, for example, via a feedback line.

The operation of such an amplifier is as follows for two input voltages:
Only one of the input voltages changes, and an output voltage corresponding to the amount of change in the voltage difference between them is output.

[Problem to be solved by the invention]

However, when conventional amplifiers are used with weak or very high input voltages, the following problems occur. Fifth
As shown in Figure (b), there is a problem that the device does not operate in a region where the input voltage is small. This is the potential of the constant potential power supply line (O
n-channel MO due to the voltage drop of the constant current source with respect to V)
3I - transistor N9. The voltage of the source of NIO and the n-channel MOS transistor N9. Unless a voltage higher than the sum of the threshold voltage of NIO is applied to the input terminal, the n-channel MOS) transistor N9. This is because N10 cannot operate.

On the other hand, if the input voltage is too high, the linearity of the output voltage with respect to the input voltage cannot be maintained, resulting in a problem that stable amplification cannot be achieved. This is because if the input voltage is too high, the n-channel MO5I-transistor N9. The potential of the source of NIO and the potential of the drain of P-channel MOS transistor PIO (pH) of the current mirror circuit are almost equal, and even if a higher voltage is applied to the input voltage, the voltage at the output terminal does not increase and reaches a plateau. Become. This is because the output terminal of the output stage receiving the voltage at the output terminal similarly rises and fixes the n-channel MOS transistor N9 at a high voltage.

For this reason, conventional amplifiers are unable to perform amplification when the input voltage is near the low potential power supply voltage, and there is a limit to the lower limit of the input voltage, or when the input voltage is too high, linearity cannot be maintained. The range of input voltage that can provide stable amplification is limited.

Therefore, an object of the present invention is to provide an amplifier that can maintain output voltage linearity over a wide range of input voltages.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic configuration of an amplifier according to the present invention.

In the figure, 1 is an amplifier, 2 and 3 are differential stages, 4 is a switch means, 5 is an output stage, 6 is a bias voltage line, 7 is a selection signal line, 8 is a feedback line, and 9 is the output of differential stage 2 10 is the output end of the differential stage 3, and 15 is the output terminal.

The amplifier of the present invention includes a plurality of amplifying circuits each having a different input voltage range from which a stable output can be obtained with respect to an input voltage, and a switch means for selecting one of the output terminals of the plurality of amplifying circuits by a selection signal. In a state where the input voltage range of the amplifier circuits is common, the plurality of amplifier circuits are switched by the switch means to obtain the output voltage.

In addition, there are multiple differential stages where the input voltage is input to one input terminal of each, an output stage where the output voltages of the multiple differential stages are input, and a voltage corresponding to the output voltage is output to the output terminal. switch means for connecting one of the plurality of output terminals of the plurality of differential stages to the output stage by inputting a signal; and feedback for applying the output voltage of the output terminal to each of the other input terminals of the plurality of differential stages. and the plurality of differential stages are configured such that the input voltage range in which each differential stage operates stably with respect to the input voltage is partially different, and the switch means is configured to When the input voltage range is common, the selection signal is used to switch the connection to the output stage.

Furthermore, there is a differential stage in which an input voltage is input to one input terminal, and an output stage connected to the output terminal of the differential stage and outputting a voltage corresponding to the output voltage of the differential stage to the output terminal of the output stage. , a feedback line that supplies the output voltage of the output terminal of the output stage to the other input terminal of the differential stage, and one of the plurality of output terminals of the plurality of amplifier circuits according to the input of the selection signal. Each of the plurality of amplifier circuits is configured to have a different input voltage range in which it operates stably with respect to the input voltage, and the switch means is configured such that the input voltage range of the plurality of amplifier circuits is common to the input voltage range. I am trying to switch it when it is.

[Effect]

In the amplifier of the present invention, each differential stage operates stably with respect to the input voltage (the linearity of the output voltage with respect to the input voltage can be maintained). Since the input voltage range is expanded by sequentially switching the stages, the linearity of the output voltage can be maintained even over a wide range of input voltages.

Also, since multiple differential stages each have different characteristics,
When switching by a switch means, there is a risk that voltage deviation may occur in the output voltage, but in the present invention, the output voltage of the output stage is commonly fed back to each differential stage via a feedback line, so that the voltage is The deviation can be minimized.

〔Example〕

The first embodiment will be described using FIG. 1, FIGS. 2(a) and (b), and FIGS. 3(a) and (b).

In the figure, A and B are differential stages, P1 to P5 are enhancement type P-channel MO5) run disks, N1 to N4
is an enhancement type n-channel MOS transistor, Ql and Q2 are depletion type n-channel MOS transistors, and 11 is a switching point of the switch means 4 when a predetermined input chamber is reached. Components that are the same as those in FIG. 1 are given the same reference numerals.

The amplifier of the first embodiment will be explained.

In the amplifier of the first embodiment, in the configuration of the amplifier 1 shown in FIG. 1, the differential stage 2 is the differential stage A shown in FIG. 2(a).
(same configuration as the amplifier shown in FIG. 5 shown in the conventional example), and the differential stage 3 is the amplifier shown in FIG. 2(b).
The output stage 5 is composed of the conventional output stage shown in FIG. The gates of the n-channel MOS transistors Nl and Ql of the differential stages A and B are commonly connected to an input terminal to which an input voltage is applied, and the gates of the n-channel MOS transistors N2 . The gates of Q2 are commonly connected to the output terminal via a feedback line 8, and the gates of the n-channel MOS transistors N
3. N4 is a bias voltage 49 applied to a bias circuit (not shown).
They are commonly connected via 16.

Further, as shown in FIG. 3(a), the differential stage A has an input voltage connected to an n-channel MOS transistor Nl.

N2 threshold (for example, about 1■) and n-channel MOS
It has a characteristic that it cannot operate at a voltage lower than the sum of the drain voltage of transistor N3.

The differential stage B is constructed as shown in FIG. 2(b), and the differential stage A
In n-channel MO3) transistors Nl and N2 are connected to n-channel MO3! - the thresholds of transistors Q1, Q2 (e.g. MOS) are n-channel MO3
(lower voltage than the drain voltage during operation of transistor N4). This results in n
Since the channel MOS transistors Ql and Q2 are conductive even when no input terminal is applied, an output voltage appears at the output terminal even if the input voltage is weak. However, the third
As shown in Figure (b), when the input voltage is lower than that of the differential stage A, the linearity of the output voltage cannot be maintained.

The operation of the amplifier of the first embodiment using the differential stages A and B and the switch means 4 as described above will be explained.

In this amplifier, when the input voltage is weak, the switching means 4 connects the differential stage B to the output stage 5 and gives its output to the output stage 5, but the differential stage A is not yet in operation.

Therefore, the output voltage appears at the output terminal from the differential stage B while maintaining linearity.

differential stage A as the input voltage gradually increases.

B operate together, and the linearity of the output voltage is maintained in both cases. At this time, since the switch means 4 has not yet been switched to the differential stage B side, the output voltage is the output voltage of the differential stage B. When a preset switching point of the switch means 4 comes with both differential stages A and B operating, the switch means 4 switches the side of the differential stage A from the differential stage B to the output stage 5. Switch connections. At this time, since one of the input terminals of the differential stages A and B is connected to the output terminal of the output stage via a feedback line, the deviation in the output voltage at the time of switching can be minimized. If the input voltage further increases, differential stage B will no longer be able to maintain the linearity of the output voltage, but since the switch means has already been switched to the differential stage A side, differential stage A will be able to maintain linearity. The output voltage appears at the output terminal.

As mentioned above, in the first embodiment, the differential stage A.

Differential stages A and B are switched while B is operating stably (the linearity of the output voltage with respect to the input voltage can be maintained), so even if the input voltage is weak, the linearity of the output voltage of the amplifier is maintained. can be maintained, and output voltage linearity can be maintained even over a wide range of input voltages.

Next, as a second embodiment, FIG. 6 shows another amplifier having the same effect as that in FIG. 1, and FIGS. 7(a), (b)
) shows the specific configuration of differential stages 2 and 3. In the figure, P20~
P27 is an enhancement type p-channel MOS transistor, and N20 to N27 are enhancement type n-channel MO34 transistors. Components similar to those in FIG. 1 are designated by the same reference numerals.

The amplifier in FIG. 6 includes a bias circuit 131 that applies a bias voltage to the differential stage 2, and an output stage 5 that receives the output of the differential stage C.
1, and a bias circuit 1 that provides a bias voltage to the differential stage 3.
32, an output stage 52 receiving the output of the differential stage, and said 2
It has switch means 41 for switching the outputs of the two output stages 51 and 51.

Regarding the differential stages 2 and 3, for example, the differential stage 2 is configured as shown in FIG. 7(a), and includes a differential stage C, a resistor R, and
A bias circuit 131 consisting of a channel MOS transistor N22, an n-channel MO3 transistor N24 and a p
Output stage 51 consisting of channel MOS transistor P22
and has. The differential stage 3 is constructed as shown in FIG. 7(b), and includes a bias circuit 132 consisting of a resistor R, a P-channel MO5) transistor P23, an n-channel MO3) transistor N27, and a p-channel MO3. ) and an output stage 52 consisting of a transistor P25.

Differential stage C has the same configuration as differential stage A in FIG. 2(a),
As mentioned above, the input voltage is applied to the n-channel MOS transistor N20. There is a characteristic that control by the input voltage cannot be performed when the voltage is lower than the sum of the threshold voltage of N21 (for example, about IV) and the drain voltage of the n-channel MO3 transistor N23.

In the differential stage, due to the n-channel MOS transistor N25 configured as a current mirror circuit, the open degree of the n-channel MOS transistor N26 is large and the voltage drop is minimal, so the input voltage to the gate of the P-channel MOS transistor P27 is n-channel MO3) transistor N2
Even for a weak input voltage that is less than the voltage drop caused by 6, it is possible to control the input voltage. On the other hand, when the input voltage is high, the linearity of the output voltage cannot be maintained.

The operation of this amplifier is such that when the input voltage is weak, the switch means 41 is switched to output the output voltage on the differential stage side, and when the input voltage reaches the switching point, the switch means 41 is switched to the differential stage side. The output voltage from the differential stage C is output by switching to the C side.

As mentioned above, in the third embodiment, FIG. 7(a),
Since the amplifier in (b) is used, the differential stage A in Fig. 2 is used.
, B, there is no need to use a depletion type MOS transistor, so the manufacturing process can be simplified.

Next, a third embodiment will be explained using FIG. 4.

FIG. 4 shows the above-described first embodiment applied to a part of a digital-to-analog converter. In the figure, P6 to P8
is an enhancement type P-channel MOS transistor,
N5 to N8 are enhancement type n-channel MOS transistors, D1 to D4 are digital terminals into which digital signals are input, 12 is an R-2R ladder resistor, and 13 is a resistor and an enhancement type n-channel MOS transistor N5 connected in series. Bias circuits 14a and 14b that generate a constant voltage are switches consisting of transfer gates. Differential stages A and B are shown in FIG.
) and (b). In addition, this digital
The analog converter switches the differential stage AB to the top pin 1.
-04 (at this time, differential stages A and B are both in operation and both output voltages with linearity), eliminating the need for a circuit to generate a selection signal. ing.

This digital-to-analog converter operates as follows. “0000J~ro” on digital terminal D4~DI
111J is input, the voltage divided by the R-2R ladder resistor is commonly input to one input terminal of differential stages A and B, and in this state, the digital terminal D4 is "
0'', the transfer gate 14a of the switch
opens and provides the output voltage of differential stage B to the output stage. The differential stage B operates stably even if the input voltage of the digital terminals D4 to D1 is rooooj and the input voltage is weak.

On the other hand, since the transverse gate ) 14b is closed, the output voltage of the differential stage A is not transmitted to the output stage. The input to the digital terminals D4 to D1 changes, and the input to the digital terminals D4 to D1 changes from "1000" to rl
When 111J is input, digital terminal D4 becomes “1”.
'', the switch transfer gate H4b opens and applies the output voltage of the differential stage A to the output stage. The differential stage A operates stably even if the input voltage of the digital terminals D4 to DI is rllllJ and the input voltage thereof is high. On the other hand, differential stage B
is already unable to maintain the linearity of the output voltage,
Since the transfer gate 14a is closed, the output voltage of the differential stage B is not transmitted to the output stage.

In this way, when the present invention is applied to a digital-to-analog converter, the linearity of the output voltage of the amplifier can be maintained over a wide range from a weak input voltage state to a power supply voltage. Also, the switching of differential stages A and B can be done using the topmost via.
) D4 or differential stages A and B both output voltages with linearity to generate the selection signal, thereby eliminating the need for a circuit for generating the selection signal.

FIG. 8 shows a fourth embodiment.

In this fourth embodiment, the amplifier of the second embodiment is applied to a part of a digital-to-analog converter. The switch means 41 is composed of transfer gates 14a and 14b as in the third embodiment, and is controlled by an input signal input to D4, and the switching thereof is also the same. Note that the operation of the digital-to-analog converter in the fourth embodiment is substantially the same as that in the third embodiment, so a description thereof will be omitted.

As mentioned above, in this embodiment, multiple differential stages are used in which the input voltage range in which the linearity of the output voltage can be maintained with respect to the input voltage is different, while being switched. Linearity can be maintained.

Note that, in the present invention, the number of differential stages configured such that the input voltage range in which the linearity of the output voltage can be maintained is different in some parts is not limited to two, and there may be a plurality of differential stages.

[Effects of the Invention] As explained above, the amplifier of the present invention can maintain the linearity of the output voltage even over a wide range of input voltages, thereby expanding the guaranteed range of the output voltage and contributing to voltage control of semiconductor devices, etc. .

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle configuration of the amplifier of the present invention, Fig. 2(a),
(b) is a block diagram of differential stages 2 and 3, and Fig. 3 (a) and (b)
is a characteristic diagram of the differential stage 2.3, FIG. 4 is a block diagram of an embodiment in which the present invention is applied to a digital-to-analog converter, FIG. 5 is a diagram showing a conventional amplifier, and FIG. 6 is a diagram of another embodiment of the present invention. Configuration diagram of amplifier, Fig. 7(a),
(b) is a block diagram of other differential stages 2 and 3, and FIG. 8 is a block diagram of an embodiment in which another amplifier of the present invention is adopted as a digital-to-analog converter. In the figure, 1 is an amplifier, 2 and 3 are differential stages, 4.41 is a switch means, 5.51.52 is an output stage, and 6.61.6
2 is a bias voltage line, 7 is a selection signal line, 8 is a feedback line, 9
10 is the output end of the differential stage 2, 11 is the switching point of the switch means 4, 12 is a ladder resistor, 13.
131, 132 are bias circuits, 14 a, 14
b is a transfer gate, 15 is an output terminal, P1 to P1
1. P20 to P27 are enhancement type p-channel to 10S transistors, Nl-N12. N2
0-N27 is an enhancement type n-channel MO3)
The transistors Ql and Q2 are depletion type n-channel MOS transistors, and D1 to D4 are digital terminals. Law (α) (11) Miaki 1! hA, BQ circulation plan 2 '42 days 0 long Kanjo Aδ layer H 蛎 ink 3 昂ス ま n platform width! L-1st name, 5′″y 謬ii

Claims (3)

[Claims] (1) It includes a plurality of amplifier circuits each having a different input voltage range that provides a stable output with respect to the input voltage, and a switch means that selects one of the output terminals of the plurality of amplifier circuits by a selection signal. . An amplifier characterized in that, in a state where the input voltage range of the amplifier circuits is common, the plurality of amplifier circuits are switched by a switch means to obtain an output voltage. (2) A plurality of differential stages (2, 3) into which the input voltage is input to one input terminal, and an output terminal into which the output voltages of the plurality of differential stages are input and a voltage corresponding to the output voltage is output. (15); and switch means (4) for connecting one of the plurality of output terminals of the plurality of differential stages to the output stage upon input of a selection signal.
and a feedback line (8) for supplying the output voltage of the output terminal to each of the other input terminals of the plurality of differential stages, the plurality of differential stages each having a difference with respect to the input voltage. The input voltage range in which the differential stages operate stably is different in some parts, and the switch means connects the output stage to the output stage using the selection signal when the input voltage range of the plurality of differential stages is common. An amplifier characterized by switching. (3) Differential stage (2
), and an output stage (
5), and a feedback line (8) for supplying the output voltage of the output stage output terminal to the other input terminal of the differential stage; switch means (4) for selecting one of the plurality of output terminals, each of the plurality of amplifier circuits being configured to have a different input voltage range in which it stably operates with respect to the input voltage; An amplifier characterized in that the switch means performs switching when the input voltage ranges of the plurality of amplifier circuits are common.