JPH0993052A - Multi-input differential amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-input differential amplifier circuit by which a dynamic range can be expanded, circuit scale can be reduced and power consumption can be saved. SOLUTION: Currents are respectively separately supplied to pMOS transistors PT10 and PT11 constituting a differential pair and pMOS transistors PT20 and PT21 constituting a differential pair for each differential pair by pMOS transistors PT01 and PT02 constituting a current mirror circuit together with a pMOS transistor PT1 of a bias part 11. The output signal of a differential amplifier part 12a is inputted through a source follower part 13 constituted of pMOS transistors PT2 and PT3 to a push-pull output part 14 constituted of a pMOS transistor PT4 , nMOS transistor NT3 , resistor R10 and capacitor C10 , inverted and outputted to an output terminal TOUT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-input differential amplifier circuit having two or more pairs of positive and negative input terminals.

[0002]

2. Description of the Related Art A conventional multi-input differential amplifier circuit, for example,
A conventional technique using a MOS 4-terminal input differential amplifier circuit as an example.
The technique will be described. Figure 10 is a MOS type 4-terminal input differential
3 is a circuit diagram of the amplifier circuit 10. FIG. As shown in FIG.
The differential amplifier circuit of the bias section 11, the differential amplifier section 12,
From the follower section 13 and push-pull output section 14
It is configured. In FIG. 10, PT₀, PT₁, P
T₂, PT_Three, PT_Four, PT_Ten, PT₁₁, PT₂₀, PT
_{twenty one}Is a p-channel MOS (hereinafter referred to as pMOS) transition
Star, NT₁, NT₂, NT_ThreeIs an n-channel MOS (below
Lower nMOS) transistor, CUR₁Is the current source,
R_TenIs a resistance element, C_TenIs a capacitive element, T_Ten, T₁₁, T₂₀,
T _{twenty one}Is the input terminal, T_OUTShows the output terminals respectively
You. Further, 15 and 16 are power supply voltage V, respectively._DDAnd electricity
Source voltage V_SSShows the supply line of.

A 4-terminal input differential amplifier circuit 10 shown in FIG.
, PMOS transistors PT ₀ , PT ₁ , P
T ₂ constitutes a current mirror circuit, and the nMOS transistors NT ₁ and NT ₂ also constitute a current mirror circuit.

The source of the pMOS transistor PT ₁ is connected to the supply line 15 for the power supply voltage V _DD , the gate and drain of the pMOS transistor PT ₁ are connected, and the node ND ₁ is constituted by these connection points. Node ND
₁ and the supply line 16 of the power supply voltage V _SS , a current source CUR
₁ is connected. The pMOS transistor PT ₁ and the current source CUR _{1 form} a bias unit 11.

The source of the pMOS transistor PT ₀ is connected to the supply line 15 for the power supply voltage V _DD . And p
The gate of the MOS transistor PT ₀ is connected to the node ND _1, and the pMOS transistor PT _{1 of the} bias section 11 is connected.
Together with this, a current mirror circuit is formed, and a current corresponding to the current I ₁ of the current source CUR ₁ is supplied to the drain of the pMOS transistor PT ₀ .

PMOS transistors PT ₁₀ , PT ₁₁ , P
The sources of T ₂₀ and PT ₂₁ are connected to each other, and the node ND ₂ is constituted by these connection points. The node ND ₂ is connected to the drain of the pMOS transistor PT ₀ . The drains of the pMOS transistors PT ₁₁ and PT ₂₁ are connected to each other, and a node ND ₃ is constituted by the connection point of these. The nMOS transistor N is connected to the node ND _3.
The drain of T ₁ is connected. Further, the drains of the pMOS transistors PT ₁₀ and PT ₂₀ are connected to each other, and a node ND ₄ is formed by the connection point thereof. The drain of the nMOS transistor NT ₂ is connected to the node ND ₄ . In addition, the nMOS transistor N
The gates of T ₁ and NT ₂ are connected to the node ND ₃ , and the sources are connected to the supply line 16 of the power supply voltage V _SS . pM
The gate of the OS transistor _{PT 10, PT 20, PT 11} , PT 21 is connected to the input terminal _{T 10, T 20, T 11} , T 21 , respectively. Due to the above-mentioned elements and their connection,
A differential amplifier section 12 of the circuit is configured. Note that pMO
The substrate nodes of the S transistors PT ₁₀ , PT ₂₀ , PT ₁₁ and PT ₂₁ are connected to the source node ND ₂ , but they may be connected to the supply line 16 of the power supply voltage V _DD .

The source of the pMOS transistor PT ₂ is connected to the supply line 15 for the power supply voltage V _DD . And p
The gate of the MOS transistor PT ₂ is connected to the node ND _1, and the pMOS transistor PT _{1 of the} bias unit 11 is connected.
Together with this, a current mirror circuit is formed, and a current corresponding to the current I ₁ of the current source CUR ₁ is supplied to the drain of the pMOS transistor PT ₂ . pMOS transistor PT ₂
Is connected to the source of the pMOS transistor PT ₃ , and a node ND ₅ is constituted by these connection points. The gate of the pMOS transistor PT ₃ is connected to the node ND _4, and the drain of the pMOS transistor PT ₃ is connected to the supply line 16 of the power supply voltage V _SS . p
The source follower unit 13 is composed of the MOS transistor PT ₂ and the pMOS transistor PT ₃ .

The source of the pMOS transistor PT ₄ is connected to the supply line 15 of the power supply voltage V _DD , while the source of the nMOS transistor NT ₃ is supplied to the supply line 16 of the power supply voltage V _SS.
It is connected to the. In addition, pMOS transistor PT ₄
Is connected to the drain of the nMOS transistor NT ₃ , and a node ND ₆ is constituted by these connection points. The gate of the pMOS transistor PT ₄ is connected to the node ND _5, and the gate of the nMOS transistor NT ₃ is connected to the node ND ₄ . A resistor element R ₁₀ and a capacitor element C ₁₀ for phase compensation are connected in series between the node ND ₆ and the node ND _4, and further, the node ND
_The output terminal T _OUT is connected to ₆ . A push-pull output unit 14 is configured by the above elements and their connections.

The operation of the 4-terminal input differential amplifier circuit 10 will be described below with reference to FIG. Up to four signals can be simultaneously input to the four-terminal input differential amplifier circuit 10. Of the four input terminals, T ₁₀ and T ₁₁ , T ₂₀ and T
₂₁ are differential input terminals. Then, in the differential amplifier section 12, the difference between the signals input to the differential input terminals T ₁₀ and T ₁₁ is extracted and output to the node ND ₄ .
Similarly, the difference between the signals input to the differential input terminals T ₂₀ and T ₂₁ is extracted and output to the node ND ₄ .

In the source follower unit 13, the node N
The signal appearing at D ₄ is output to the node ND ₅ , that is, the source of the pMOS transistor PT ₃ . As a result, in-phase signals appear at the nodes ND ₅ and ND ₄ .

Further, the signal appearing at the node ND ₄ constitutes an nMOS transistor N constituting the push-pull output section 14.
The signals input to the gate of T ₃ and appearing at the node ND ₅ are input to the gates of the pMOS transistors PT ₄ forming the push-pull output section 14. As a result, in the push-pull output unit 14, an inverted signal of the signals of the node ND ₄ and the node ND ₅ input to the node ND ₆ appears and is output to the output terminal T _OUT . In the push-pull output unit 14, the resistance element R ₁₀ and the capacitance element C ₁₀ connected in series between the node ND ₄ and the node ND ₆ allow the source follower unit 13 in the preceding stage to operate.
And the phase distortion of the signal generated in the differential amplifier section 12 at the previous stage is compensated.

The operation principle of the 4-terminal input differential amplifier circuit 10 shown in FIG. 10 has been described above. This differential amplifier circuit 10 takes out the difference between the signals input to the input terminals T ₁₀ , T ₁₁ and T ₂₀ , T ₂₁ , which form the differential input terminals, respectively, and outputs the inverted output of the differential amplifier circuit. Further, the inverted signal is output to the output terminal T _OUT . With respect to the output terminal T _OUT , T ₁₀ and T ₂₀ are common mode input terminals, and T ₁₁ and T _20
21 is an inverting input terminal. The output voltage V _OUT of the output terminal T _OUT in such a configuration is given by the following equation.

## EQU1 ## V _OUT = g (V ₁₀ −V ₁₁ + V ₂₀ −V ₂₁ ) ... (1) Here, V ₁₀ , V ₁₁ , V ₂₀ , and V ₂₁ are input terminals T, respectively.
Input voltage of minute amplitude to ₁₀ , T ₁₁ , T ₂₀ , and T ₂₁ , and g indicates the gain of the entire operational amplifier circuit.

FIG. 11 shows two transconductances
FIG. 6 is a circuit diagram of a bipolar 4-terminal input operational amplifier circuit including an amplifier and other elements. FIG.
Although different from the 4-terminal input differential amplifier circuit 10 shown in FIG. 3, this bipolar 4-terminal input operational amplifier circuit is also an example of a conventional multi-input differential amplifier circuit.

In FIG. 11, 1 and 2 are transconductance amplifiers having a gain g _m , 3 is an output buffer,
R _C and C _C are resistance elements and capacitance elements, T _X1 and T _X2 are differential input terminals of the transconductance amplifier 1, T _Y1 and T _Y
Y2 indicates a differential input terminal of the transconductance amplifier 2, and T _OUT indicates an output terminal. As shown in FIG. 11, a transconductance amplifier 1 and a transconductance amplifier 2 connected in parallel Voltage - constitute a current converter, the connected resistor element R _C and the capacitive element C _C in parallel A current-voltage converter having a high impedance Z is configured.

Here, the voltages input to the differential input terminals T _X1 and T _X2 of the transconductance amplifier 1 are V _X1 and V _X2 , respectively, and the transconductance amplifier 2
If the voltages input to the differential input terminals T _Y1 and T _Y2 are V _Y1 and V _Y2 , respectively, the currents I _X and I _Y shown in the following equations are output to the output terminals of the transconductance amplifier 1 and the transconductance amplifier 2. Is obtained.

[Number 2] _{I X = g m (V X1} -V X2) I Y = g m (V Y1 -V Y2) ... (2)

The impedance Z of the current-voltage converter formed by the resistance element R _C and the capacitance element C _C connected in parallel is given by the following equation.

[Equation 3] _{Z = R C / (1 +} j2πfR C · C C) ... (3)

[0017] Voltage - the current converter, a transconductance amplifier 1 and the current I _X output by 2, the sum current of _{I Y (I X + I Y} ) current - is converted into a voltage by the voltage conversion unit, the next stage Input to the output buffer 3. If the gain of the output buffer is +1 for example, the output voltage V _OUT appearing at the output terminal T _OUT is given by the following equation.

(4) V _OUT = Z (I _X + I _Y ) = g _m · Z (V _X1 −V _X2 + V _Y1 −V _Y2 ) (4)

That is, g _m · Z in the equation (4) is an open loop gain of the bipolar type four-terminal input operational amplifier circuit, and this open loop gain is an extremely large value.

[0019]

By the way, the above-mentioned conventional multi-input differential amplifier circuit has problems such as a narrow dynamic range and difficulty in obtaining high accuracy.

FIG. 12 shows the 4-terminal input differential amplifier shown in FIG.
Non-inversion increase of 1/2 gain constituted by the width circuit 10.
The circuit diagram of the width device and its input / output characteristics are shown. FIG.
As shown in 2, the four input terminals of the operational amplifier 10
T_Ten, T₁₁, T₂₀, T _{twenty one}Of T₁₁And T_{twenty one}Is the output terminal T
_OUTConnected to the input terminal T₂₀Analog ground power
Grounded to the input terminal T_TenVoltage V_INIs applied
Is done.

FIG. 12 (b) shows the input / output characteristics of the 4-terminal input operational amplifier in the above connection. As can be seen from this figure, in the 1/2 gain non-inverting amplifier constituted by the 4-terminal input differential amplifier circuit 10, the dynamic range in which the gain satisfies 1/2 is very narrow.

Next, the cause of the narrow dynamic range of the conventional multi-input differential amplifier circuit such as the 4-terminal input differential amplifier circuit shown in FIG. 10 will be considered. To facilitate understanding of the reason why the dynamic range of the multi-input differential amplifier circuit is narrow, the dynamic range of a normal two-terminal input differential amplifier circuit will be described first.

FIG. 13 shows an ordinary 2-terminal input differential amplifier circuit 1.
It is a circuit diagram of 0d. As shown, the two-terminal input differential amplifier circuit 10d includes a bias unit 11, a differential amplifier unit 12d, a source follower unit 13, and a push-pull output unit 14. In the 2-terminal input differential amplifier circuit 10d, the bias unit 11, the source follower unit 13 and the push-pull output unit 14 are the same as those of the 4-terminal input differential amplifier circuit shown in FIG. Since it is similar to the embodiment, the detailed description thereof will be omitted here. Further, the same components of the circuit will be denoted by the same reference numerals as those in FIG.

As shown in FIG. 13, two-terminal input differential amplification
The differential amplifier 12d of the circuit 10d is a current mirror circuit.
Comprising pMOS transistor PT₀, Differential input element
Comprising pMOS transistor PT_Ten, PT₁₁,Also,
NMOS transistor N forming a current mirror circuit
T₁, NT₂It is composed by. pMOS transformer
Dista PT_Ten, PT₁₁Of the input terminals T
_Ten, T ₁₁It is connected to the.

FIG. 14A shows the 2-terminal input difference shown in FIG.
Voltage follower configured using a dynamic amplifier circuit 10d
It is a circuit. 2 terminal input difference
Two input terminals T of the dynamic amplifier circuit 10d _Ten, T₁₁Of T
₁₁Is the output terminal T_OUTConnected to the input terminal T_TenVoltage V
_INIs applied. Input voltage V in the above connection_INAnd output
Terminal T_OUTVoltage V_OUTInput voltage range where
Enclose the dynamic range of the 2-terminal input differential amplifier circuit 10d.
It's called nge. Fig. 14 (b) shows the two terminals in the above connection.
An example of the input / output characteristics of the force differential amplifier circuit 10d is shown.
The dynamic range of this example is about 0.3V to 4.5V.
Voltage range.

FIG. 15A shows the internal voltage in the differential amplifier circuit 12d of the two-terminal input differential amplifier circuit in the connection of FIG. 14A in detail with the input voltage V _IN as the horizontal axis. . In a two-terminal input differential amplifier circuit, it is almost always used by applying negative feedback from the output terminal T _OUT to the inverting input terminal T ₁₁ , and in that case, the in-phase input terminal T ₁₀ and the inverting input terminal T ₁₁ are used. Virtual ground is established between them, and the voltage at the inverting input terminal T ₁₁ becomes equal to the voltage at the in-phase input terminal T ₁₀ ,

(5) V _T10 ≈ V _T11 (5) That is,

## EQU6 ## V _OUT ≈V _IN (6)

As shown in FIG. 15A, when the input voltage V _IN becomes close to V _SS or V _DD in the range of V _th ,
There is a transistor in the circuit that cannot operate normally because it cannot pass current, that is, V _OUT
≠ V _IN . As described above, the range in which V _OUT ≈V _IN holds, that is, the dynamic range is an important characteristic indicating the input voltage range in which the two-terminal input differential amplifier circuit operates normally, and it holds in the widest input voltage range. Is desirable.

As shown in FIG. 15A, the differential amplifier 12
The voltage of the output node ND ₃ of d hardly changes even if the input voltage V _IN changes. This is the source follower section 1
Assuming that the combined amplification factor of 3 and the push-pull output unit 14 is g _sp , the voltage change of the output node ND ₃ of the differential amplifier unit 12d becomes 1 / g _sp of the voltage change of V _OUT (≈V _IN ). This is because. The combined amplification factor g _sp of the source follower unit 13 and the push-pull output unit 14 is usually 20 dB to 40 d,
That is, a value of several ten times to several hundred times is used.

As shown in FIG. 15A, the differential amplifier 12
The voltage of the source node ND ₂ of the differential input transistors PT ₁₀ and PT ₁₁ of d changes with the level being shifted with respect to the change of the input voltage V _IN . This is when considering an OR-type source follower circuit in which the gates T ₁₀ and T ₁₁ of the pMOS transistors PT ₁₀ and PT ₁₁ are input terminals, the pMOS transistor PT ₀ is a constant current source, and the node ND ₂ is an output terminal. It can be explained as the characteristic of the output voltage.

FIG. 15B shows a voltage follower connection.
Of the differential amplifier circuit 12d of the two-terminal input differential amplifier circuit in
The current flowing in each transistor in the part is the input voltage
V_INIs shown as the horizontal axis. pMOS transistor PT₀To
The flowing current is the pMOS transistor PT of the bias section.
₁Drain current, ie current source CUR₁Current I₁
Current I according to ₀It is. However, input voltage V_IN(≒ V
_OUT) Is the power supply voltage V_DDThe current I₀Ie the difference
The current flowing through the dynamic amplification circuit is the pMOS transistor P.
T_Ten, PT₁₁Limited by the gate voltage of
You. nMOS transistor NT₁, NT₂Current flowing through
These two transistors form a current mirror circuit.
Therefore, the current value is almost the same.

[Equation 7] _{I NT1 ≒ I NT2 ≒ I 0} /2 ... is (7). In addition, the currents flowing through the pMOS transistors PT ₁₀ and PT ₁₁ are nMOS transistors NT ₂ and NT ₂ , respectively.
Equal to the current flowing through NT ₁ ,

[Equation 8] _{I PT10 ≒ I PT11 ≒ I 0} /2 ... is (8).

The level shift amount from the input voltage V _IN shown in FIG. 15A to the source node ND ₂ of the differential input transistor, that is, the gate-source potential V _GSPT10 (≈ of the pMOS transistor PT ₁₀ or PT ₁₁ ).
V _GSPT11 ) is obtained from the current formula in the saturation region of the pMOS transistor.

I _PT10 = (1/2) × β × (V _GSPT10 −V _th ) ² (9) where β = (μ / C _OX ) × (W _eff / L _eff ). Here, μ is the carrier mobility and C _ox is the capacitance of the gate oxide film per unit area. Furthermore, V _th , W
_eff and L _eff are the threshold voltages of the pMOS transistors PT ₁₀ and PT ₁₁ , respectively, W _eff is the execution channel width,
L _eff indicates the execution channel length, respectively. The following equation is obtained from the equations (8) and (9).

V _GSPT10 = V _th − (I ₀ / β) ^1/2 (10) Here, V _GSPT10 and V _th are negative values.

Now, comparing with the description of the dynamic range of the above-mentioned two-terminal input differential amplifier circuit, the conventional FIG.
Consider the cause of the narrow dynamic range of a multi-input differential amplifier circuit such as the 4-terminal input differential amplifier circuit shown in FIG. Although the virtual ground (V _T10 ≈V _T11 ) and the dynamic range in the two-terminal input differential amplifier circuit have been described in order above, the relationship and the dynamic range correspond to the virtual ground in the multi-input differential amplifier circuit. The input / output characteristics will be described.

In the multi-input differential amplifier circuit as shown in FIG. 10, since there are a plurality of in-phase input terminals and a plurality of inverting input terminals, respectively, unlike the case of the two-terminal input differential amplifier circuit, the integrated input on the in-phase side is obtained. And the total input balance on the inverting side.

Here, the 4-terminal input differential amplification shown in FIG.
In the differential amplifier 12 of the circuit 10, the pMOS transistor
Star PT_Ten, PT₁₁, PT₂₀, PT_{twenty one}Have similar characteristics
Let's do it. In addition, these pMOS transistors
W is the effective channel width and effective channel length_eff
And L_effIn addition, these pMOS transistors
The threshold voltage of the_thAnd the source voltage is V_SToss
You. Also, the input terminal T _Ten, T₁₁, T₂₀, T_{twenty one}In it
Each V_T10, V_T11, V_T20, V_T21Voltage is applied
Shall be.

When the 4-terminal input differential amplifier circuit 10 of FIG. 10 is used with negative feedback, the virtual ground (V _T10 ≈V _T11 ) in the 2-terminal input differential amplifier circuit is used.
As a relationship corresponding to, it is necessary as a characteristic of the multi-input differential amplifier circuit that the sum of input voltages applied to the in-phase input terminal side becomes equal to the sum of input voltages applied to the inverting input terminal side. That is, it is desired that the following relationship holds for a wide input voltage range.

[ _Equation 11] V _T10 + V _T20 ≈V _T11 + V _T21 (11) Also, this means that the two-terminal input differential amplifier circuit has V _T10 ≈
The multi-input differential amplifier circuit has to operate under the condition that each input voltage is different, such as V _T10 ≠ V _T11 ≠ V _T20 ≠ V _{T2 1} , whereas the multi-input differential amplifier circuit has to operate under the V _T11 input condition. Is required.

In the connection of FIG. 12A, V _T10 = V _IN , V _T20 = V _AGND , V _T11 = V _T21 = V _{OUT, and} therefore, according to equation (11).

## EQU12 ## V _OUT ≈ (1/2) × (V _IN + V _AGND ) ... (12) here,

[Equation 13] v _in = V _IN −V _AGND v _out = V _OUT −V _AGND (13) is replaced, and the equation (12) is converted to the analog ground AGN.
When the voltage equation with D as a reference is rewritten, the following equation is obtained.

V _out = v _in / 2 (14)

However, the conventional multi-input differential amplifier circuit could not satisfy the relationship of the expression (12) in a sufficiently practical range.

FIG. 16A shows in detail the internal voltage in the differential amplifier section 12 of the conventional 4-terminal input differential amplifier circuit in the connection of FIG. 12A with the input voltage V _IN as the horizontal axis.
The current flowing through each transistor at that time is shown in FIG.
(B). The characteristic of equation (12) is obtained when V _IN
It is an extremely narrow input voltage range near ≈V _AGND (= 2.5V).

This can also be derived from the relationship between the gate-source voltage of each input transistor and the current. pM
If the current flowing through the OS transistor PT ₁₀ is I ₀ ,
NMOS transistor N forming a current mirror circuit
The current flowing through T ₁ and NT ₂ is I _0/2 . Therefore, the pMOS transistors PT ₁₀ , PT ₂₀ , PT ₁₁ , P
The currents flowing through T ₂₁ are I _PT10 , I _PT20 , I _PT11 ,
I _PT21

[Number 15] the _{I PT10 + I PT20 = I 0} /2 I PT11 + I PT21 = I 0/2 ... (15).

Here, in the range where each transistor operates in the saturation region, a current equation similar to the equation (9) holds for each transistor, and therefore, according to the equation (15),

Equation 16] (β / 2) × (V IN -V S -V th) 2 + (β / 2) × (V AGND -V S -V th) 2 = I 0/2 (β / 2) × to become _{(V OUT -V S -V th)} 2 × 2 = I 0/2 ... (16). Here, by replacing v _in = V _IN −V _AGND v _out = V _OUT −V _AGND v _S = V _S + V _th −V _AGND k = I ₀ / 2β, the equation (16) is replaced with the analog ground AGN.
Solving for a voltage referenced to D gives:

[0041]

V _out = (v _in / 2) -k ^1/2 + {k- (v _in / 2) ² } ^1/2 v _S = (v _in / 2) + {k- (v _in / 2) ² } ^1/2 (17)

The current flowing through the pMOS transistor PT ₁₀ is given by the following equation.

I _PT10 = (β / 2) × (V _IN −V _S −V _th ) ² = (β / 2) × (v _in −v _S ) ² = (β / 2) × [(v _in / 2)-{k- (v _in / 2) ² } ^1/2 ] ² ... (18) When the equation (18) is differentiated with respect to v _in , the following equation is obtained.

[0043]

Equation 19] _{dI PT10 / dv in = (β} / 2) × _{[v in / 2- {k- (v} in / 2) 2} 1/2 ] × _{[1+ (v in / 2) /} {k- when (v _in / 2) ^{2} 1/2]} ... (19) v _in = 0 the gradient for v _in the current I _PT10 when the (V _iN = V _AGND) and m, by the equation (19), the following The formula is obtained.

[Number 20] _{m = dI PT10 / dv in =} - (1/2) (I 0 · β / 2) 1/2 ... (20) current I _PT10 flowing to the pMOS transistor PT ₁₀ is, v
± I _0/4 varies around the value I _0/4 in the case of _in = 0. Thus, [Delta] V = - When _{(I 0/4) / m} , expressed as follows.

[Expression 21] ΔV = (I ₀ / 2β) ^1/2 (21) Equation (17) holds in the input voltage range of approximately V _AGND −ΔV <V _IN <V _AGND + ΔV, but even within this range, Only a part of the range satisfies the relationship of Expression (14).

In the input voltage range of V _IN <V _AGND -ΔV,
Node N that is a common source of input transistors
The voltage V _{S of} D ₂ is almost determined as the output voltage of the source follower circuit with V _IN as the input, and V ₂ is applied to the gate.
_No current flows in the pMOS transistor PT ₂₀ to which _AGND is input. In equation (15), I _PT20 =
When set to 0, the following equation is obtained.

(22) v _out = v _in + (2 ^1/2 -1) k ^1/2 v _S = v _in + (2k) ^1/2 (22)

In the input voltage range of V _IN > V _AGND + ΔV,
Node N that is a common source of input transistors
The voltage V _{S of} D ₂ is almost determined as the output voltage of the source follower circuit with V _AGND as input, and no current flows through the pMOS transistor PT ₁₀ having V _IN input to its gate. In the formula (15), I _PT10
When = 0, the following equation is obtained.

(23) v _out = (2 ^1/2 -1) k ^1/2 v _S = (2k) ^1/2 (23)

Further, in the bipolar type four-terminal input operational amplifier circuit shown in FIG. 11, since a current is converted into a voltage by using a high resistance element, a highly accurate resistance element is required, or a circuit for correction or Other correction means are needed.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a multi-input differential amplifier circuit capable of widening the dynamic range, reducing the circuit scale, and reducing the power consumption. Especially.

[0048]

To achieve the above object, the present invention provides a multi-input differential amplifier circuit including a differential amplifier section having at least two pairs of positive and negative input terminals.
Each differential pair of the differential amplifier section is connected to a different current source, and a current is individually supplied to each differential pair.

Further, in the present invention, the differential amplifier section is composed of at least two pairs of metal insulating film semiconductor transistors whose gates form differential input terminals, and the connection point between the sources of each transistor pair is the above-mentioned current. The drains of the transistors forming the positive side input element are connected to a common node, and the drains of the transistors forming the negative side input element are connected to another common node.

Further, in the present invention, each of the current sources is constituted by a metal insulating film semiconductor transistor connected between the power source and the connection point between the sources of the differential pairs, and the differential input element and the current source are connected. The conductance of the constituent metal insulating film semiconductor transistors is set to be different for each differential pair.

According to the present invention, a current is supplied to each differential input pair in the differential amplifier. This widens the dynamic range of the differential amplifier circuit.

In the differential amplifier section, the conductance of the metal insulating film semiconductor transistor as a differential input element and the metal insulating film semiconductor transistor for supplying a constant current are set to be different for each differential input pair. The signals input to the input terminals are weighted. As a result, it is possible to configure a non-inverting amplifier having an arbitrary gain value smaller than 1.

Further, the present invention has a switch circuit for switching the input to each of the input terminals.

Further, by switching the input signal or the level thereof to each differential input pair by the analog switch, for example, the gain can be variably set such as 1/2, 1 and 2, and the inversion and non-inversion can be switched. Can be configured.

[0055]

BEST MODE FOR CARRYING OUT THE INVENTIONFirst embodiment FIG. 1 shows a first embodiment of a multi-input differential amplifier circuit according to the present invention.
It is a circuit diagram which shows a form. Figure 1 shows a MOS type 4-terminal input difference
It is a circuit diagram of a dynamic amplifier circuit 10a. In FIG. 1, PT
₀₁, PT₀₂, PT₁, PT₂, PT_Three, PT_Four, P
T_Ten, PT₁₁, PT₂₀, PT_{twenty one}Is pMOS transistor
Ta, NT₁, NT₂, NT_ThreeIs an nMOS transistor,
CUR₁Is the current source, R_TenIs a resistance element, C_TenIs a capacitive element,
T _Ten, T₁₁, T₂₀, T_{twenty one}Is the input terminal, T_OUTIs the output terminal
Are shown respectively. Also, 15 and 16 are electric
Source voltage V_DDAnd power supply voltage V_SSShows the supply line of.

As shown in FIG. 1, this differential amplifier circuit includes a bias section 11, a differential amplifier section 12a, and a source follower section 1.
3 and push-pull output unit 14.
pMOS transistors PT ₀₁ , PT ₀₂ , PT ₁ , PT ₂
Constitutes a current mirror circuit, and the nMOS transistors NT ₁ and NT ₂ also constitute a current mirror circuit.

The source of the pMOS transistor PT ₁ is connected to the supply line 15 for the power supply voltage V _DD , the gate and drain of the pMOS transistor PT ₁ are connected, and the node ND ₁ is constituted by these connection points. Node ND
₁ and the supply line 16 of the power supply voltage V _SS , a current source CUR
₁ is connected. The pMOS transistor PT ₁ and the current source CUR _{1 form} a bias unit 11.

The sources of the pMOS transistors PT ₀₁ and PT ₀₂ are connected to the supply line 15 for the power supply voltage V _DD . Then, the gates of the pMOS transistors PT ₀₁ and PT ₀₂ are connected to the node ND ₁ to form current mirror circuits respectively, and a current corresponding to the current I ₁ of the current source CUR ₁ is supplied to the drains of the pMOS transistors PT ₀₁ and PT _02. Supplied.

The sources of the pMOS transistors PT ₁₀ and PT ₁₁ are connected to each other, and the node ND is connected by these connection points.
₂₁ is configured, and the drain of the pMOS transistor PT ₀₁ as the first constant current source is connected to the node ND ₂₁ . The sources of the pMOS transistors PT ₂₀ and PT ₂₁ are connected to each other, and a node ND ₂₂ is formed by the connection point of these, and the pMOS transistor P as a second constant current source.
The drain of T ₀₂ is connected to the node ND ₂₂ . Further, the drains of the pMOS transistors PT ₁₁ and PT ₂₁ are connected to each other, and a node ND ₃ is constituted by these connection points. The nMOS transistor N is connected to the node ND _3.
The drain of T ₁ is connected. Further, the drains of the pMOS transistors PT ₁₀ and PT ₂₀ are connected to each other, and a node ND ₄ is formed by the connection point thereof. The drain of the nMOS transistor NT ₂ is connected to the node ND ₄ . In addition, the nMOS transistor N
The gates of T ₁ and NT ₂ are connected to the node ND ₃ , and the sources are connected to the supply line 16 of the power supply voltage V _SS .

PMOS transistors PT ₁₀ , PT ₂₀ , P
The gates of T ₁₁ and PT ₂₁ are input terminals T ₁₀ , T ₂₀ , and
It is connected to T ₁₁ and T ₂₁ . A differential amplifier section 12a of the circuit is configured by the above-mentioned elements and their connection. In the differential amplifier 12a, the pMOS transistor PT ₁₀ and the pMOS transistor PT _{11 form} one differential pair, and the pMOS transistor PT ₀₁ supplies a current corresponding to the current I ₁ of the current source CUR ₁ to this differential pair. To do. In addition, pMOS transistor PT ₂₀ and pMOS
Transistor PT ₂₁ constitutes another differential pair, pM
The OS transistor PT ₀₂ has a current source CUR _{1 for} this differential pair.
A current corresponding to the current I ₁ of is supplied. The nMOS transistor NT ₂ and the nMOS transistor NT _{2 form a} current mirror circuit, and form an output load of the differential amplifier 12a.

The source of the pMOS transistor PT ₂ is connected to the supply line 15 for the power supply voltage V _DD . And p
The gate of the MOS transistor PT ₂ is connected to the node ND _1, and the pMOS transistor PT _{1 of the} bias unit 11 is connected.
Together with this, a current mirror circuit is formed, and a current corresponding to the current I ₁ of the current source CUR ₁ is supplied to the drain of the pMOS transistor PT ₂ . pMOS transistor PT ₂
Is connected to the source of the pMOS transistor PT ₃ , and a node ND ₅ is constituted by these connection points. The gate of the pMOS transistor PT ₃ is connected to the node ND _4, and the drain of the pMOS transistor PT ₃ is connected to the supply line 16 of the power supply voltage V _SS . p
The source follower unit 13 is composed of the MOS transistor PT ₂ and the pMOS transistor PT ₃ .

The source of the pMOS transistor PT ₄ is connected to the supply line 15 of the power supply voltage V _DD , while the source of the nMOS transistor NT ₃ is supplied to the supply line 16 of the power supply voltage V _SS.
It is connected to the. In addition, pMOS transistor PT ₄
Is connected to the drain of the nMOS transistor NT ₃ , and a node ND ₆ is constituted by these connection points. The gate of the pMOS transistor PT ₄ is connected to the node ND _5, and the gate of the nMOS transistor NT ₃ is connected to the node ND ₄ . A resistance element R ₁₀ and a capacitance element C ₁₀ are connected in series between the node ND ₆ and the node ND _4, and the output terminal T is connected to the node ND _6.
OUT is connected. A push-pull output unit 14 of the differential amplifier circuit is configured by the above elements and their connections.

Hereinafter, in the above-mentioned configuration, 4 shown in FIG.
The operation of the terminal input differential amplifier circuit will be described. This 4
Up to four signals can be simultaneously input to the terminal input differential amplifier circuit.
I can do it. T out of 4 input terminals_TenAnd T₁₁, T₂₀And T
_{twenty one}Are differential input terminals. And the circuit
Of the differential input terminal T_TenAnd T₁₁
The difference between the signals input to_FourOut
Similarly, the differential input terminal T ₂₀And T_{twenty one}Entered in
The signal difference is taken out and the node ND_FourIs output to

In the source follower unit 13, the node N
The signal appearing at D ₄ is output to the node ND ₅ , that is, the source of the pMOS transistor PT ₃ . As a result, in-phase signals appear at the nodes ND ₅ and ND ₄ .

Further, the signal appearing at the node ND ₄ constitutes the nMOS transistor N constituting the push-pull output section 14.
The signals input to the gate of T ₃ and appearing at the node ND ₅ are input to the gates of the pMOS transistors PT ₄ forming the push-pull output section 14. As a result, in the push-pull output unit 14, an inverted signal of the signals of the node ND ₄ and the node ND ₅ input to the node ND ₆ appears and is output to the output terminal T _OUT . Further, in the push-pull output section 14, the resistance element R ₁₀ for phase compensation and the capacitance element C ₁₀ are connected in series between the node ND ₄ and the node ND _6, and the source follower section 1 of the previous stage is connected.
3 and the phase distortion of the signal generated in the differential amplifying section 12a in the second previous stage is compensated.

As described above, the 4-terminal input differential amplifier circuit shown in FIG.
The operating principle of was explained. This 4-terminal input differential
Inputs that make up the differential input terminals by the amplifier circuit
Terminal T_Ten, T₁₁, Again T₂₀, T_{twenty one}Difference between signals input to
Is taken out, and is further placed in the push-pull output section 14.
Output terminal T after being inverted_OUTIs output to output
Terminal T_OUTInput terminal T for the output of_Ten, T₂₀Entry into
Force becomes in-phase input and input terminal T₁₁, T_{twenty one}Input to
It becomes a transfer input. Set the gain of the entire operational amplifier circuit to g and enter
Force terminal T_Ten, T₁₁, T₂₀, T_{twenty one}Small amplitude input to
V_Ten, V₁₁, V ₂₀, V_{twenty one}Then output V_OUTIs
Like

V _OUT = g (V ₁₀ −V ₁₁ + V ₂₀ −V ₂₁ ) ... (24)

Next, the dynamic range of the 4-terminal input differential amplifier circuit will be considered. Here, in the differential amplifier 12a, pMOS transistors PT ₁₀ and P
T ₁₁ , PT ₂₀ , and PT ₂₁ have similar characteristics.
The effective channel width and effective channel length of these pMOS transistors are W _eff and L _eff , respectively, and the threshold voltage of these pMOS transistors is V _th . Also, the pMOS transistor PT ₁₀
And the source voltage of the differential pair formed by the pMOS transistor PT ₁₁ is V _S1 , and the pMOS transistor P
The source voltage of the differential pair formed by T ₂₀ and the pMOS transistor PT ₂₁ is V _S2 .

FIG. 2A is a circuit diagram showing an example of a 1/2 gain non-inverting operational amplifier circuit configured by using the 4-terminal input differential amplifier circuit shown in FIG. 2 (b) is this one
It is a graph which shows the input / output characteristic of the non-inverting operational amplifier circuit of / 2 gain.

As shown in FIG. 2A, 4-terminal input operation
The four input terminals T of the amplifier 10a_Ten, T₁₁, T₂₀, T_{twenty one}
Of T₁₁And T_{twenty one}Is the output terminal T_OUTConnected to the input end
Child T ₂₀Is grounded to the analog ground potential AGND
You. Input terminal T_TenVoltage V_INIs applied.

FIG. 2B shows the input / output characteristics of the 4-terminal input operational amplifier in the above connection. 12 (b) showing the input / output characteristics of the 1/2 gain non-inverting amplifier formed by the conventional 4-terminal input operational amplifier 10, it is formed by the 4-terminal input operational amplifier 10a of the present invention. It can be seen that in the 1/2 gain non-inverting amplifier, the dynamic range in which the gain satisfies 1/2 is significantly improved.

This can also be derived from the relationship between the gate-source voltage of each input transistor and the current. PMOS transistor P serving as a constant current source of the differential amplifier 12a
The current flowing through T ₀₁ and the pMOS transistor PT ₀₂ is I _0/2 . NMO forming a current mirror circuit
The current flowing through the S transistors NT ₁ and NT ₂ is also I _0/2
Becomes Therefore, the pMOS transistors PT ₁₀ and P
The currents flowing through T ₂₀ , PT ₁₁ and PT ₂₁ are respectively I _PT10 ,
If I _PT20 , I _PT11 , I _PT21

[Number 25] the _{I PT10 + I PT11 = I 0} /2 I PT20 + I PT21 = I 0/2 I PT10 + I PT20 = I 0/2 I PT11 + I PT21 = I 0/2 ... (25). From the equation (25), the following equation is obtained.

[ _Expression 26] I _PT10 = I _PT21 I _PT11 = I _PT20 (26)

Here, in the range in which each transistor operates in the saturation region, a current equation similar to the equation (9) holds for each transistor, and therefore the following equation is obtained from the equation (25). I want it.

[Number 27] (β / 2) × (V IN -V S1 -V th) 2 + (β / 2) × (V OUT -V S1 -V th) 2 = I 0/2 ... (27)

[Number 28] (β / 2) × (V AGND -V S2 -V th) 2 + (β / 2) × (V OUT -V S2 -V th) 2 = I 0/2 ... (28) the formula ( The following equation is obtained from 26).

(Β / 2) × (V _IN −V _S1 −V _th ) ² = (β / 2) × (V _OUT −V _S2 −V _th ) ² (29)

(30) (β / 2) × (V _OUT −V _S1 −V _th ) ² = (β / 2) × (V _AGND −V _S2 −V _th ) ² (30)

Here, v _in = V _IN -V _AGND v _out = V _OUT -V _AGND v _S1 = V _S1 + V _th -V _AGND v _S2 = V _S2 + V _th -V _AGND k = I ₀ / 2β Solving the equations (27) and (30) for the voltage with the analog ground AGND as a reference,

V _out = v _in / 2 (31)

(32) v _S1 = (3/4) × v _in + {(k / 2) − (v _in / 4) ² } ^1/2 (32)

(33) v _S2 = (1/4) × v _in + {(k / 2) − (v _in / 4) ² } ^1/2 (33) The following equation is obtained from the equations (32) and (33).

(34) v _S1 −v _S2 = v _in / 2 (34)

The equation (31) is the same as the equation (14) which is the characteristic required for the 4-terminal input differential amplifier circuit, and the input / output characteristic which cannot be realized by the conventional 4-terminal differential amplifier circuit 10 is provided by the present invention. It is clear that

4 in the connection of FIG. 2A is shown in FIG.
The internal voltage in the differential amplifier section 12 of the terminal input differential amplifier circuit 10a is shown in detail with the input voltage V _IN as the horizontal axis. The current flowing through each transistor at that time is shown in FIG.
(B).

Now, the current flowing through the pMOS transistor PT ₁₀ is

(35) I _PT10 = (β / 2) × (V _IN −V _S1 −V _th ) ² = (β / 2) × (v _in −v _S1 ) ² = (β / 2) × [(v _in / 4) - a - {(k / 2) ( v in / 4) 2} 1/2 ] ² (35). Differentiating the expression (35) with respect to v _in , the following expression is obtained.

Equation 36] _{dI PT10 / dv in = (β} / 4) × _{[(v in / 4) - {} (k / 2) - (v in / 4) 2} 1/2 ] × [1+ (v _in / 4) / {(k / 2)-(v _in / 4) ² } ^1/2 ] ... (36) When v _in = 0 (V _IN = V _AGND ), the slope of current I _PT10 with respect to v _in is m. Then, the following equation is obtained from the equation (36).

_M = dI _PT10 / dv _in = − (1/8) (I ₀ · β) ^1/2 (37)

[0077] current I _PT10 flowing to the pMOS transistor PT ₁₀ is, ± about the value I _0/4 in the case of v _in = 0
I _0/4 changes. _{Therefore, ΔV = (- I 0/} 4)
/ M, the following equation is obtained.

(38) ΔV = 2 (I ₀ / β) ^1/2 (38) Equation (31) holds in the input voltage range of approximately V _AGND −ΔV <V _IN <V _AGND + ΔV, and within this range. Satisfies the relationship of equation (14) for almost all regions.
Comparing equation (21) and equation (38), the value of ΔV is 2
・ It can be seen that it is 2 ^1/2 times larger.

In the present example shown in FIG. 3A, V
The input voltage range is _AGND −1.2V <V _IN <V _AGND + 1.2V, which is sufficiently practical. It will also be apparent that the above description of the 4-terminal input differential amplifier circuit 10a is sufficiently satisfactory.

As described above, in the first embodiment,
According to this, the pMOS transistor P forming the differential pair
T_Ten, PT₁₁And pMOS transistors forming a differential pair
Star PT ₂₀, PT_{twenty one}Is connected to the pMOS transistor of the bias unit 11.
Dista PT₁PM that composes a current mirror circuit with
OS transistor PT₀₁, PT₀₂According to each
Since the electric current is supplied to each
Realized MOS type 4-terminal input differential amplifier circuit
It is possible to reduce the circuit scale and power consumption.
There are advantages that can be achieved.

Second Embodiment FIG. 4 is a circuit diagram showing a second embodiment of the multi-terminal input differential amplifier circuit according to the present invention. FIG. 4 is a circuit diagram of the MOS type 6-terminal input differential amplifier circuit 10b. 6 as shown
The terminal input differential amplifier circuit 10b includes a bias unit 11, a differential amplifier unit 12b, a source follower unit 13, and a push-pull output unit 14. In the 6-terminal input differential amplifier circuit 10b, the differential amplifier section 12b
Except for the above, the bias unit 11, the source follower unit 13, and the push-pull output unit 14 are the same as those of the first embodiment of the present invention shown in FIG. 1, and therefore the detailed description thereof will be omitted here. Moreover, the same components of the circuit are denoted by the same reference numerals as those in FIG.

As shown in FIG. 4, a 6-terminal input differential amplification circuit is used.
The differential amplifier 12b of the path 10b constitutes a current mirror circuit.
PMOS transistor PT₀₁, PT₀₂, PT₀₃,
PMOS transistor PT forming a differential input element_Ten,
PT₂₀, PT₃₀, PT₁₁, PT_{twenty one}, PT₃₁, Again
NMOS transistor N forming a mirror circuit
T ₁, NT₂It is composed by.

PMOS transistors PT ₀₁ , PT ₀₂ , P
The source of T ₀₃ is connected to the supply line 15 of the power supply voltage V _DD ,
The gate is connected to the node ND ₁ of the bias unit 11. The sources of the pMOS transistor PT ₁₀ and the pMOS transistor PT ₁₁ are connected to each other and to the drain of the pMOS transistor PT ₀₁ to form a node ND ₂₁ . The sources of the pMOS transistor PT ₂₀ and pMOS transistor PT ₂₁ are connected to each other and to the drain of the pMOS transistor PT ₀₂ to form a node ND ₂₂ . The sources of the pMOS transistor PT ₃₀ and the pMOS transistor PT ₃₁ are connected to each other and to the drain of the pMOS transistor PT ₀₃ to form a node ND ₂₃ .

PMOS transistors PT ₁₀ , PT ₂₀ , P
The drain of T ₃₀ is connected to form a node ND ₄ ,
The drains of the pMOS transistors PT ₁₁ , PT ₂₁ , and PT ₃₁ are connected to form a node ND ₃ . nMO
The gates of the S transistor NT ₁ and the nMOS transistor NT ₂ are connected to each other and to the node ND ₃ ,
The drains of the transistor NT ₁ and the nMOS transistor NT ₂ are connected to the nodes ND ₃ and ND ₄ , respectively. In addition, nMOS transistors NT ₁ and NT
The source of ₂ is connected to the supply line 16 of the power supply voltage V _SS . A current mirror circuit is configured by the nMOS transistors NT ₁ and NT ₂ and constitutes an output load of the differential amplifier 12b.

The gates of the pMOS transistors PT ₁₀ and PT ₁₁ are connected to the input terminals T ₁₀ and T ₁₁ to form a first differential input terminal, and the gates of the pMOS transistors PT ₂₀ and PT ₂₁ are input terminals T ₂₀ and It is connected to the T _21, to constitute a second differential input pair, the gate of the pMOS transistor PT _30, PT ₃₁ is connected to the input terminal T _30, T _31, constituting a third differential input pair.

The difference between the signals input to the respective input terminals is taken out by the differential amplifier 12b, and the differential amplifier 1
It is output to the node ND ₄ of 2b. And the node ND
The output signal of the differential amplification unit 12b output to ₄ is inverted via the source follower unit 13 and the push-pull output unit 14 in the subsequent stage and output to the output terminal T _OUT .

FIG. 5 shows the 6-terminal input differential amplifier circuit 10 described above.
The circuit diagram of the non-inverting amplifier of 1/3 gain comprised by b, and its input-output characteristic are shown. FIG. 5A is a circuit diagram of a 1/3 gain non-inverting amplifier using the 6-terminal input differential amplifier circuit 10b. As shown in the figure, the voltage V _IN is input to the input terminal T ₁₀ , the input terminals T ₂₀ and T ₃₀ are grounded to the analog ground potential AGND, and the input terminals T ₁₁ , T ₂₁ and T ₃₁ are output terminals T _OUT. It is connected to the. FIG. 5B shows the input / output characteristics of the 1/3 gain non-inverting amplifier.

According to this embodiment, in the MOS type multi-input differential amplifier circuit, the number of input terminals is not limited to four, and it is possible to increase the number. Thereby, for example, a non-inverting amplifier with a gain of 1/3 can be constructed. Further, as in the first embodiment, the second embodiment can realize a MOS multi-input differential amplifier circuit having an improved dynamic range.

Third Embodiment FIG. 6 is a circuit diagram showing a third embodiment of the multi-terminal input differential amplifier circuit according to the present invention. FIG. 6 is a circuit diagram of the MOS type four-terminal input differential amplifier circuit 10c. This circuit diagram is shown in Figure 1.
Is a circuit diagram and Hobodo of 4-terminal input differential amplifier circuit 10a shown in supplies pMOS transistor PT _20a, the PT _21a and therewith to the constant current of the differential input element pM
The size of the OS transistor PT _02a is the differential amplifier circuit 10.
It is set to be different from a.

Here, the parameter β _i representing the characteristics of the MOS transistor is defined as (β _i = W _eff / L _eff ). As already described, W _eff and L _eff are the effective channel width and effective channel length of the MOS transistor, respectively.

In the third embodiment, the pMOS transistors PT ₁₀ , P constituting the differential amplifier section 12c are formed.
T ₁₁ , PT _20a , PT _21a and pM supplying constant current
The parameters β _i of the OS transistors PT ₀₁ and PT _02a are set so as to satisfy the following conditions.

[Number 39] _{β PT10: β PT11: β PT20a} : β PT21a = 1: 1: 2: 2 β PT01: β PT02a = 1: 2 ... (39)

That is, a MOS that constitutes a differential input element
It is possible to weight each input signal by setting the size of the transistor and the size of the MOS transistor that supplies the constant current to be different for each differential pair.

FIG. 7 shows a circuit diagram of a 1/3 gain non-inverting amplifier constructed using the 1: 2 weighted 4-terminal input differential amplifier circuit 10c and its input / output characteristics. As shown in FIG. 7 (a), 4 of the four input terminals of the terminal input differential amplifier circuit 10c, T ₂₀ is grounded to the analog ground potential AGND, the T _11, T ₂₁ is the output terminal over T _OUT It is connected and the voltage V _IN is applied to the input terminal T ₁₀ . FIG. 7B shows the input / output characteristics of the 1/3 gain non-inverting amplifier.

As described above, according to the third embodiment, in the differential amplifier section 12c, the MO is provided for each differential pair.
By setting the sizes of the S transistors differently, it is possible to configure a non-inverting amplifier whose gain can be set to an arbitrary value smaller than 1. Further, similar to the second embodiment, the third embodiment can realize a MOS multi-input differential amplifier circuit having an improved dynamic range.

In each of the embodiments described above, each differential input element is composed of a pMOS transistor, but it goes without saying that it can be composed of an nMOS transistor. Further, although the output load is configured by the current mirror circuit using the nMOS transistor, it may be configured by a circuit other than the current mirror circuit. It is also possible that the constant current source is composed of a bipolar type circuit.

Further, in each of the above-described embodiments, the differential amplifier circuit is composed of the bias section, the differential amplifier section, the source follower section and the push-pull output section, but the push-pull output section is omitted and the source is omitted. It may be a type that outputs by the follower unit.

Two application examples using the four-terminal input differential amplifier circuits 10a and 10c of the above-described first and third embodiments will be described below with reference to FIGS. 8 and 9. 8 is 4
Terminal input differential amplifier circuit 10a and analog switch A
The circuit diagram of the gain 1 / 2,1,2 variable non-inverting amplifier comprised using SW1, ASW2, ASW3, ASW4, and the ON / OFF state of the analog switch are shown. FIG. 8A shows a circuit diagram of a variable gain type non-inverting amplifier, and FIG. 8B shows analog switches ASW1 and ASW.
It is a figure which shows the relationship between the on / off state of 2, ASW3, ASW4, and a gain.

As shown in FIG. 8A, the voltage V _IN is applied to the input terminal T ₁₀ , and the input terminal T ₂₀ is grounded to the analog ground potential AGND via the analog switch ASW1. An analog switch ASW2 is connected between the input terminal T _{10 and the} input terminal T ₂₀ . The input terminal T ₁₁ is grounded to the analog ground potential AGND via the analog switch ASW3, and the input terminal T ₂₁ is connected to the output terminal T _OUT . Further, the analog switch ASW4 is connected between the input terminal T ₁₁ and the input terminal T ₂₁ .

FIG. 8B shows the relationship between the on / off state of each analog switch and the gain of the amplifier in the above connection.
Is shown in As shown, the gain of the amplifier can be set to ½, 1 and 2 by changing the on / off state of each analog switch.

FIG. 9 shows a 4-terminal input differential amplifier circuit 10c weighted to 1: 2 and analog switches ASW1 ,.
It shows a non-inverting / inverting switching amplifier having a gain of 1/2, which is configured by using ASW2, ASW3, and ASW4. FIG. 9A shows a circuit diagram of an amplifier capable of non-inverting / inverting switching, and FIG. 9B shows an analog switch AS.
It is a figure which shows the ON / OFF state of W1, ASW2, ASW3, and ASW4, and the relationship of a gain.

As shown in FIG. 9A, the input terminals T ₁₀ and T ₁₁ are respectively analog switches ASW.
2, connected to the input signal V _IN via ASW4. On the other hand, the input terminal T ₁₀ and the input terminal T ₁₁ are grounded to the analog ground potential AGND via the analog switches ASW1 and ASW3, respectively. Further, the input terminal T ₂₀ is grounded to the analog ground potential AGND, and the input terminal T ₂₁ is connected to the output terminal T _OUT .

FIG. 9B shows the relationship between the on / off state of each analog switch and the gain of the amplifier in the above connection.
Is shown in As shown, by changing the on / off state of each analog switch, the amplifier gain 1
It can be arbitrarily set to the non-inversion state and the inversion state of / 2.

[0102]

As described above, according to the multi-input differential amplifier circuit of the present invention, the dynamic range of the differential amplifier circuit can be greatly improved and a high input impedance circuit can be realized. This has the advantage that the circuit scale of the differential amplifier circuit can be reduced and power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a 4-terminal input differential amplifier circuit according to the present invention.

2A and 2B are a circuit diagram and an input / output characteristic of a 1/2 gain non-inverting amplifier using a 4-terminal input differential amplifier circuit.

FIG. 3 is a diagram showing a voltage of each part and a current of a differential amplifier transistor with respect to an input voltage in a ½ gain non-inverting amplifier circuit using a 4-terminal input differential amplifier circuit according to the present invention.

FIG. 4 is a circuit diagram of a 6-terminal input differential amplifier circuit according to the present invention.

5A and 5B are a circuit diagram and an input / output characteristic of a 1/3 gain non-inverting amplifier using a 6-terminal input differential amplifier circuit.

FIG. 6 is a circuit diagram of a 4-terminal input differential amplifier circuit in which an input signal is 1: 2 weighted.

7A and 7B are a circuit diagram and an input / output characteristic of a 1/3 gain non-inverting amplifier using a 4-terminal input differential amplifier circuit in which an input signal 1: 2 is weighted.

FIG. 8 is a circuit diagram of a variable gain type non-inverting amplifier using a 4-terminal input differential amplifier circuit and a relationship diagram of a switch state and a gain.

FIG. 9 is a circuit diagram of a non-inverting / inverting switching amplifier using a 4-terminal input differential amplifier circuit in which an input signal 1: 2 is weighted and a relationship diagram between a switch state and a gain.

FIG. 10 is a circuit diagram of a conventional MOS 4-terminal input differential amplifier circuit.

FIG. 11 is a circuit diagram of a conventional bipolar 4-terminal input operational amplifier circuit.

FIG. 12 is a circuit diagram of a 1/2 gain non-inverting amplifier using a conventional MOS 4-terminal input differential amplifier circuit and a diagram showing input / output characteristics.

FIG. 13 is a circuit diagram of a two-terminal input differential amplifier circuit.

14A and 14B are a circuit diagram and an input / output characteristic of a voltage follower circuit using a two-terminal input differential amplifier circuit.

FIG. 15 is a diagram showing a voltage of each unit and a current of a differential amplifier unit transistor with respect to an input voltage in a voltage follower circuit using a two-terminal input differential amplifier circuit.

FIG. 16 is a diagram showing a voltage of each unit and a current of a differential amplifier unit transistor with respect to an input voltage in a ½ gain non-inverting amplifier circuit using a conventional MOS 4-terminal input differential amplifier circuit.

[Explanation of symbols]

 1, 2 ... Transconductance amplifier 3 ... Output buffer 10 ... Conventional 4-terminal input differential amplifier circuit 10a, 10b ... 4-terminal input differential amplifier circuit 10c ... 6-terminal input differential amplifier circuit 11 of the present invention ... Bias section 12, 12a, 12b, 12c, 12d ... Differential amplification section 13 ... Source follower section 14 ... Push-pull output section 15 ... Power supply voltage V_DDSupply line 16 ... Power supply voltage V_SSSupply line PT₀, PT₁, PT₂, PT_Three, PT_Four, PT₀₁, P
T₀₂, PT_02a, PT ₀₃... pMOS transistor PT_Ten, PT₁₁, PT₂₀, PT_{twenty one}, PT_20a, P
T_21a, PT₃₀, PT₃₁... by pMOS transistor
Configured differential input element NT₁, NT₂, NT_Three... nMOS transistor CUR₁… Current source I₁… Current source CUR₁Current value R_Ten, R_C... Resistance element C_Ten, C_C… Capacitance element T_Ten, T₁₁, T₂₀, T_{twenty one}, T₃₀, T₃₁, T_X1, T_X2, T
_Y1, T_Y2… Input terminal T_OUT… Output terminal ND₁, ND₂, ND_{twenty one}, ND_{twenty two}, ND_{twenty three}, ND_Three, N
D_Four, ND_Five, ND₆… Nodes ASW1, ASW2, ASW3, ASW4… Analogs
Itch AGND ... Analog ground potential g_sp… Amplification factor μ… Carrier mobility C_OX... Capacity of gate oxide film per unit area V_DD, V_SS…Power-supply voltage

Claims (4)

[Claims] 1. A multi-input differential amplifier circuit comprising a differential amplifier section having at least two pairs of positive and negative input terminals, wherein each differential pair of the differential amplifier section is connected to a different current source. , A multi-input differential amplifier circuit in which current is individually supplied to each differential pair. 2. The differential amplifier section is composed of at least two pairs of metal insulating film semiconductor transistors whose gates form input terminals, and the connection point between the sources of each transistor pair is connected to the current source. 2. The multi-input difference according to claim 1, wherein the drains of the transistors forming the side input element are connected to a common node, and the drains of the transistors forming the negative side input element are connected to another common node. Dynamic amplification circuit. 3. A metal insulating film which comprises a metal film insulating semiconductor transistor connected between a power source and a connection point between sources of each differential pair, and which constitutes a differential input element and a current source. 3. The multi-input differential amplifier circuit according to claim 2, wherein the conductance of the film semiconductor transistor is set to be different for each differential pair. 4. The multi-input differential amplifier circuit according to claim 1, further comprising a switch circuit for switching an input to each of the input terminals.