JPH03284894A - Thick film circuit substrate and manufacture thereof - Google Patents
Thick film circuit substrate and manufacture thereofInfo
- Publication number
- JPH03284894A JPH03284894A JP8598990A JP8598990A JPH03284894A JP H03284894 A JPH03284894 A JP H03284894A JP 8598990 A JP8598990 A JP 8598990A JP 8598990 A JP8598990 A JP 8598990A JP H03284894 A JPH03284894 A JP H03284894A
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- wiring
- paste
- circuit
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000004020 conductor Substances 0.000 claims abstract description 34
- 239000000919 ceramic Substances 0.000 claims abstract description 24
- 239000012212 insulator Substances 0.000 claims abstract description 14
- 238000005498 polishing Methods 0.000 claims description 9
- 238000007639 printing Methods 0.000 abstract description 14
- 239000000463 material Substances 0.000 abstract description 7
- 239000010408 film Substances 0.000 abstract 7
- 239000010409 thin film Substances 0.000 abstract 2
- 238000007650 screen-printing Methods 0.000 abstract 1
- 238000010304 firing Methods 0.000 description 14
- 239000010410 layer Substances 0.000 description 13
- 238000000034 method Methods 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 239000000428 dust Substances 0.000 description 7
- 238000004806 packaging method and process Methods 0.000 description 4
- 239000011230 binding agent Substances 0.000 description 3
- 230000000740 bleeding effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 239000006061 abrasive grain Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000009760 electrical discharge machining Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高密度配線の厚膜回路基板に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thick film circuit board with high density wiring.
一般に、厚膜回路基板は、セラミック基板上に導体ペー
ストを印刷、乾燥、焼成して導体パターンを形成してい
た。さらに、導体パターン上に、絶縁体ペーストや抵抗
ペーストを印刷、乾燥、焼成して、所望回路を形成する
ための絶縁層や所望回路を構成する抵抗体が形成されて
いた。このような厚膜回路基板は、電子機器などの特に
信頼性が要求される部分に搭載されて使用されてきた。Generally, thick film circuit boards are produced by printing, drying, and firing a conductor paste on a ceramic substrate to form a conductor pattern. Further, an insulating paste or a resistive paste is printed, dried, and fired on the conductor pattern to form an insulating layer for forming a desired circuit and a resistor for forming the desired circuit. Such thick film circuit boards have been used in parts where reliability is particularly required, such as in electronic devices.
近時、厚膜回路基板は、電子機器の小型、軽量化のため
、−層の高密度の配線パターンが必要とされてきた。現
在の技術では、厚膜印刷手法によれば、線幅、線間とも
に１００μｍ前後であり、はぼ限界に近い頌域にまで到
達している。In recent years, thick film circuit boards have been required to have high-density wiring patterns in the negative layer in order to make electronic devices smaller and lighter. With current technology, both line width and line spacing are around 100 μm using thick film printing techniques, which has reached a near-limit range.
しかも、上述の厚膜回路基板は、基板上に一層の回路パ
ターンを形成するのではなく、より実装密度を向上させ
るために、厚膜配線パターン上の一部に絶縁体ペースト
を塗布し、該絶縁体層上にさらに第２層目の回路パター
ンを形成する。また導電性ペーストで形成した厚膜配線
パターン上の一部に抵抗ペーストの塗布により形成した
抵抗体を配置したりする。Furthermore, the above-mentioned thick film circuit board does not involve forming a single layer of circuit patterns on the board, but instead coats an insulating paste on a portion of the thick film wiring pattern to further improve the packaging density. A second layer circuit pattern is further formed on the insulator layer. Further, a resistor formed by applying a resistive paste may be placed on a part of a thick film wiring pattern formed using a conductive paste.
上述の厚膜手法によって配線パターンを形成すると、厚
膜導体ペーストの粘性流動により、繊細なパターンを形
成したとしても、印刷後のペーストの流動、印刷時のカ
スレなどが発生してしまい、これ以上繊細なパターンの
厚膜配線基板を形成する・ことが困難であった。また、
印刷後の焼成時において、搬送・焼成する焼成炉内での
ゴミの付着により、パターン間の短絡や断線なとを惹起
してしまうこともある。When wiring patterns are formed using the above-mentioned thick film method, even if a delicate pattern is formed due to the viscous flow of the thick film conductor paste, the paste will flow after printing and scratches during printing will occur. It has been difficult to form thick film wiring boards with delicate patterns. Also,
At the time of firing after printing, dust adhesion in the firing furnace where the printing is carried out and fired may cause short circuits or disconnections between patterns.
さらには、−層の厚膜配線だけでなく、その配線パター
ン上に絶縁体層、抵抗体膜を厚膜手法により形成するが
、例えば、抵抗体膜を配線パターン上に形成することに
より、配線パターンのエッチ部分で抵抗体膜の断線が生
じることもあり、−定形状の抵抗体膜を印刷することが
困難であった。Furthermore, in addition to the - layer thick film wiring, an insulator layer and a resistor film are formed on the wiring pattern using a thick film method. For example, by forming a resistor film on the wiring pattern, the wiring Disconnection of the resistor film may occur at the etched portion of the pattern, making it difficult to print a resistor film with a regular shape.
本発明は、上述の問題点に鑑みて案出したものであり、
その目的は高実装密度の配線パターンが可能な厚膜回路
基板及びその製造方法を提供することにある。The present invention has been devised in view of the above-mentioned problems,
The purpose is to provide a thick film circuit board that allows wiring patterns with high packaging density and a method for manufacturing the same.
上述の問題点を解決するために行った本発明の具体的な
手段は、条溝に導電材料を充填した厚膜配線を有するセ
ラミック基板上に、絶縁体又は抵抗ペーストから成る厚
膜印刷パターンを形成したことを特徴とする厚膜回路基
板である。The specific means of the present invention taken to solve the above-mentioned problems is to print a thick film printed pattern made of an insulator or a resistive paste on a ceramic substrate having a thick film wiring whose grooves are filled with a conductive material. This is a thick film circuit board characterized by the following:
また、セラミック基板に条溝を形成する工程と、前記条
溝に導電材料を充填する工程と、前記条溝以外の導電材
料を研磨除去する工程と、条溝の厚膜配線上に、絶縁体
又は抵抗ペーストから成る厚膜印刷パターンを形成する
工程とを備えたことを特徴とする厚膜回路基板の製造方
法である。Further, the process includes a step of forming grooves on the ceramic substrate, a step of filling the grooves with a conductive material, a step of polishing and removing the conductive material other than the grooves, and a step of forming an insulator on the thick film wiring in the grooves. or a step of forming a thick film printed pattern made of resistive paste.
上述の手段により、セラミック基板内に所望配線パター
ンと同一の溝を形成し、この溝に導電性ペーストを充填
することにより所望回路配線を形成している。即ち、回
路配線は基板に形成する溝の幅に規定され、従来の厚膜
導体ペーストを印刷するよりも、高密度な配線が可能と
なる。By the above-described means, a groove identical to the desired wiring pattern is formed in the ceramic substrate, and the groove is filled with conductive paste to form the desired circuit wiring. That is, the circuit wiring is defined by the width of the groove formed in the substrate, and higher density wiring is possible than by printing conventional thick film conductor paste.
また、基本的には、上述の回路配線が基板と同一平面と
なるため、この回路配線上に絶縁体層や抵抗体膜の形成
にあたり、導体膜厚段差に起因する段切れなどの印刷形
状の不安定さがなく、確実な被着・接合及び抵抗体膜等
の印刷形状の安定化が可能となる。In addition, since the above-mentioned circuit wiring is basically on the same plane as the substrate, when forming an insulator layer or a resistor film on this circuit wiring, it is necessary to avoid printing shapes such as breaks due to differences in conductor film thickness. There is no instability, and reliable adhesion/bonding and stabilization of printed shapes of resistor films, etc. are possible.
以下、本発明の厚膜回路基板を図面に基づいて詳説する
。Hereinafter, the thick film circuit board of the present invention will be explained in detail based on the drawings.
第１図は、本発明の厚膜回路基板の平面図である。FIG. 1 is a plan view of the thick film circuit board of the present invention.
、本発明の厚膜回路基板１０は、セラミック基板ｌと厚
膜配線２とで構成されている。The thick film circuit board 10 of the present invention is composed of a ceramic substrate 1 and a thick film wiring 2.
セラミック基板ｌの表面には、所望回路パターンと対応
する条溝３が形成されている。そして該条溝３の凹部に
は、銅などの導体材料４が充填されており、所望回路の
厚膜配線２が形成されている。A groove 3 corresponding to a desired circuit pattern is formed on the surface of the ceramic substrate l. The concave portion of the groove 3 is filled with a conductive material 4 such as copper, and a thick film wiring 2 of a desired circuit is formed.
さらこの条溝３の導体材料４上に絶縁体層５や、抵抗体
膜６が形成されている。尚、絶縁体層５上には、上述の
厚膜配線２や抵抗体膜６、その他の電子部品７などと接
続する第２の厚膜配線８か形成されている。Furthermore, an insulator layer 5 and a resistor film 6 are formed on the conductor material 4 of this groove 3. Incidentally, on the insulator layer 5, a second thick film wiring 8 is formed to connect with the above-described thick film wiring 2, the resistor film 6, other electronic components 7, and the like.
上述の構成において、所望厚膜配線２か条溝３に規制さ
れて形成されるため、ペーストが条溝３に流れ込む状態
となり、ペーストだれによる隣接パターンとの短絡は一
切なく、またペーストにじみが皆無となる。In the above structure, the desired thick film wiring 2 is formed in a manner restricted by the grooves 3, so that the paste flows into the grooves 3, and there is no short circuit with adjacent patterns due to paste dripping, and there is no paste bleeding. becomes.
また、上述の条溝３は、線幅を３０〜７０μｍ、線間も
３０〜７０μｍ程度にまで設定できるため、厚膜配線２
のパターンを実質的に線幅・線間３０〜７０μｍに設定
できることになる。In addition, since the above-mentioned grooves 3 can have a line width of 30 to 70 μm and a line spacing of about 30 to 70 μm, the thick film wiring 2
This means that the pattern can be substantially set to a line width and line spacing of 30 to 70 μm.
従来のように、セラミック基板１上に単にスクリーン印
刷していた厚膜配線に比べ、回路の実装配線密度を２倍
以上に大幅に向上させることができる。Compared to the conventional thick film wiring that is simply screen printed on the ceramic substrate 1, the wiring density of the circuit can be significantly increased by more than double.
また、厚膜配線２０表面が、実質的にセラミック基板の
表面と同一高さとなるため、この厚膜配線２上に所定ペ
ーストによる厚膜印刷が容易・確実となる。例えば、厚
膜配線２の一部をパッドとして、その間に抵抗ペースト
による抵抗体膜６を形成する場合、厚膜配線２の一部の
パッドが基板ｌと同一の平面上に位置するため、パッド
と抵抗体膜６との交差部分で発生する段切れが一切なく
、確実に接続が達成される。Further, since the surface of the thick film wiring 20 is substantially at the same height as the surface of the ceramic substrate, thick film printing using a predetermined paste on the thick film wiring 2 becomes easy and reliable. For example, when a part of the thick film wiring 2 is used as a pad and a resistor film 6 is formed using a resistor paste between them, the part of the pad of the thick film wiring 2 is located on the same plane as the substrate l, so the pad There is no disconnection that occurs at the intersection between the resistor film 6 and the resistor film 6, and a reliable connection is achieved.
次に、本発明の厚膜回路基板の製造方法を第２図（ａ）
〜（ｅ）を用いて説明する。尚、各断面図は第１図のＡ
−Ａ線断面に相当する。Next, the method for manufacturing a thick film circuit board of the present invention is shown in FIG. 2(a).
This will be explained using (e). In addition, each cross-sectional view is A in Figure 1.
- Corresponds to the A-line cross section.
第２図（ａ）はセラミック基板ｌに条溝３を形成する工
程である。FIG. 2(a) shows a step of forming grooves 3 on a ceramic substrate l.
セラミック基板１は、９１０℃前後で焼成可能な低温焼
成用の基板であり、例えば、ＣａＯ（２５モル％）、Ｂ
２０．（８モル％）、５ｉ０２（５６モル％）から成る
ガラス質成分（４５重量％）とアルミナ（５５重量％）
と有機バインダーから成る材料であり、ドクターブレー
ド法によりセラミックグリーンシートに形成する。The ceramic substrate 1 is a substrate for low-temperature firing that can be fired at around 910°C, and includes, for example, CaO (25 mol%), B
20. (8 mol%), vitreous component (45% by weight) consisting of 5i02 (56 mol%) and alumina (55% by weight)
It is a material consisting of an organic binder and an organic binder, and is formed into a ceramic green sheet using the doctor blade method.
その後、所望回路パターンに対応するＳＵＳの基板（図
示せず）上に放電加工などで凹凸を施した金型２０など
を使用して、セラミックグリーンシート上の表面に回路
パターンに対応し、線幅３０〜７５μｍ１線間３０〜７
０μｍの条溝３を形成する。Thereafter, using a mold 20 or the like, which has been roughened by electrical discharge machining or the like on a SUS substrate (not shown) corresponding to the desired circuit pattern, the surface of the ceramic green sheet is shaped to correspond to the circuit pattern, and the line width is 30-75μm between 1 line 30-7
A groove 3 of 0 μm is formed.
第２図（ｂ）は、前記条溝２に導電材料４を充填する工
程である。FIG. 2(b) shows a step of filling the grooves 2 with a conductive material 4.
このようなセラミックグリーンシートは、脱バインダー
後、所定温度、例えば９１０°Ｃで焼成され、セラミッ
ク基板１が作製される。After removing the binder, such a ceramic green sheet is fired at a predetermined temperature, for example, 910° C., and the ceramic substrate 1 is produced.
厚膜配線２は、例えば銅ペースト（デュポン社＃９１５
３）が使用され、基板１の条溝３を含む基板ｌの全面又
は一部を塗布又はスクリーン印刷する。これにより、銅
ペーストが条溝３に充填される。尚、条溝３以外部分に
も銅ペーストが被着される。The thick film wiring 2 is made of, for example, copper paste (DuPont #915
3) is used to coat or screen print the entire surface or part of the substrate 1 including the grooves 3 of the substrate 1. As a result, the grooves 3 are filled with copper paste. Incidentally, the copper paste is also applied to the parts other than the grooves 3.
次に、銅ペーストを約９００℃で焼成することにより、
銅の厚膜導体を形成する。この状態では、条溝３および
基板ｌ上の回路配線とは不要な部分にも厚膜導体が被着
されていることになる。Next, by firing the copper paste at about 900°C,
Forming a copper thick film conductor. In this state, the thick film conductor is also adhered to portions unnecessary for the grooves 3 and the circuit wiring on the substrate l.
第２図（Ｃ）は、前記条溝３以外の導電材料４を研磨す
る工程である。FIG. 2(C) shows a step of polishing the conductive material 4 other than the grooves 3.
基板１の表面を研磨加工することにより、条溝３以外の
不要な導体膜を除去して所定の厚膜配線２を完成する。By polishing the surface of the substrate 1, unnecessary conductor films other than the grooves 3 are removed to complete a predetermined thick film wiring 2.
研磨方法としては、例えば、砥粒が分散された研磨基板
２１を用意し、この研磨基板２１で、セラミック基板ｌ
の回路形成面を接触させ、所定応力を印加して、所定時
間だけ、平面的に研磨加工し、不要な導体膜を除去する
。As a polishing method, for example, a polishing substrate 21 in which abrasive grains are dispersed is prepared, and this polishing substrate 21 is used to polish a ceramic substrate l.
The circuit forming surfaces of the two are brought into contact with each other, a predetermined stress is applied, and the unnecessary conductor film is removed by polishing the two surfaces for a predetermined period of time.
尚、不要な導体膜はせいぜい数百μｍ程度であるから、
若干な応力で、約ｌθ秒程度の研磨加工で不要な導体膜
を除去できる。そして、セラミック基板１をフレオンや
水で洗浄し、不要な導体膜の剥離物を完全に処理する。In addition, since the unnecessary conductor film is about several hundred μm at most,
With a slight stress, the unnecessary conductor film can be removed by polishing for about lθ seconds. Then, the ceramic substrate 1 is washed with Freon or water to completely remove unnecessary peeled conductor films.
この状態が第２図（ｄ）に示す。This state is shown in FIG. 2(d).
第２図（ｅ）は条溝３に形成された厚膜配線２上に、絶
縁体又は抵抗ペーストから成る厚膜印刷パターンを形成
する工程である。FIG. 2(e) shows a step of forming a thick film printed pattern made of an insulator or resistance paste on the thick film wiring 2 formed in the groove 3.
最後に、必要に応じて、２層目の回路パターンを形成す
るために、絶縁体層５を形成したり、また抵抗体膜６を
形成し、更に他の電子部品７を搭載する。Finally, in order to form a second-layer circuit pattern, an insulator layer 5 and a resistor film 6 are formed as necessary, and other electronic components 7 are mounted.
上述の工程において、焼成工程は量産性の向上のため、
焼成炉を使用してインライン処理される。In the above process, the firing process is performed to improve mass productivity.
Processed in-line using a firing furnace.
この焼成炉を通過する時に、セラミック基板ｌ上にゴミ
などが付着することがあるが、焼成工程後に、不要な導
体膜の除去工程があるため、不要な導体膜とともに、基
板上に付着したゴミが研磨される。このため、従来のよ
うにこのゴミが配線パターンに存在し、導体配線間のシ
ョートの原因を排除して、安定した回路が達成できるこ
とになる。When passing through this firing furnace, dust and the like may adhere to the ceramic substrate l. However, since there is a process to remove unnecessary conductor films after the firing process, dust and dirt adhered to the substrate together with the unnecessary conductor film are removed. is polished. For this reason, it is possible to achieve a stable circuit by eliminating the cause of short-circuits between conductor wirings due to the existence of this dust in the wiring pattern as in the past.
本発明者らが、線幅、線間ともに５０μｍ、導電材料と
して銅（デュポン社＃９１５３）の導体ペーストを使用
して、厚膜回路基板１０を形成し、この厚膜回路基板Ｉ
Ｏを一５５〜１２５６Ｃまでの熱サイクル試験が、厚膜
配線２のオープン−ショートの試験を行ったが、全く支
障はなかったことを確認した。The present inventors formed a thick film circuit board 10 using a conductive paste of 50 μm in line width and line spacing and copper (DuPont #9153) as a conductive material, and this thick film circuit board I
A thermal cycle test was carried out at -55 to 1256C, and an open-short test was conducted on the thick film wiring 2, but it was confirmed that there were no problems at all.
このような厚膜回路基板１０に形成された厚膜配線２は
基板表面に対して一次的な回路である。The thick film wiring 2 formed on such a thick film circuit board 10 is a primary circuit with respect to the surface of the board.
そこで、さらに回路の高実装をおこなうために、デュポ
ン社＃４４７５や旭硝子社＃５８１５などのクロスガラ
スの絶縁性ペーストを塗布又は印刷し、焼成して、厚膜
回路基板１０の所定箇所番こ絶縁体層５を形成する。尚
、絶縁性ペーストの焼成温度は９００℃未満である。Therefore, in order to achieve higher circuit mounting, an insulating paste of cross glass such as DuPont #4475 or Asahi Glass #5815 is coated or printed and baked to insulate the thick film circuit board 10 at predetermined locations. A body layer 5 is formed. Note that the firing temperature of the insulating paste is less than 900°C.
また、上述の厚膜回路基板１０の所望厚膜配線２に抵抗
体膜６として、酸化ルテニウム、珪化物系などからなる
抵抗体ペーストを塗布又は印刷し焼成する。Further, a resistor paste made of ruthenium oxide, silicide, or the like is coated or printed as the resistor film 6 on the desired thick film wiring 2 of the above-mentioned thick film circuit board 10, and then baked.
以上のように、本発明よれば、厚膜配線２を基板１の凹
部の条溝３に形成し、その表面高さを基板１と実質的に
同一に構成したため、隣接する配線とのマイグレーショ
ンやパターンだれ、にじみによる短絡が完全になく、ま
た、厚膜配線上に形成する絶縁体又は抵抗体膜の表面も
段差のない面となるため、さらに絶縁体又は抵抗体膜上
に形成する別の導体の印刷が容易に達成でき、信頼性の
高い多層厚膜配線が可能となる。As described above, according to the present invention, the thick film wiring 2 is formed in the groove 3 of the concave portion of the substrate 1, and its surface height is configured to be substantially the same as that of the substrate 1, so that migration with adjacent wiring and There are no short circuits due to pattern sag or bleeding, and the surface of the insulator or resistor film formed on the thick film wiring is also a flat surface. Printing of conductors can be easily achieved, and highly reliable multilayer thick film wiring becomes possible.
さらに、厚膜配線の線幅、線間が、条溝の溝幅、溝間に
よって決定され、従来の厚膜印刷配線に比較して、高密
度に設定することができる。Furthermore, the line width and line spacing of the thick film wiring are determined by the groove width and groove spacing of the grooves, and can be set at a higher density than conventional thick film printed wiring.
また、線幅が大変に狭くとも、条溝の溝深さを所定以上
に設定すれば、厚膜配線の断面積が従来よりも大きくな
り、電気伝導率を向上させることができ、隣接する条溝
どうしを極限的に近接化し、より高実装の厚膜配線を可
能にする。In addition, even if the line width is very narrow, if the groove depth of the groove is set to a predetermined value or more, the cross-sectional area of the thick film wiring becomes larger than before, which improves electrical conductivity. By bringing the grooves as close as possible to each other, it enables thick-film wiring with higher packaging density.
たとえば、従来の厚膜配線では、線幅、線間が１００〜
２００μｍである場合、焼成時などの製造過程で発生す
る異物（ゴミなど）の基板付着による歩留低下は５〜１
０％であったのに対して、本発明品では、線幅、線間が
３０〜７０μｍに設定しても、異物（ゴミなど）の基板
付着による歩留低下は０〜１％であった。また、本発明
品では同一回路を基板に形成しても、従来の基板面積の
１／９以下で形成できる。For example, in conventional thick film wiring, the line width and line spacing are 100~
When the thickness is 200 μm, the yield decrease due to adhesion of foreign matter (dust, etc.) generated during manufacturing processes such as firing is 5 to 1.
In contrast, in the product of the present invention, even when the line width and line spacing were set to 30 to 70 μm, the yield reduction due to adhesion of foreign matter (dust, etc.) to the substrate was 0 to 1%. . Furthermore, even if the same circuit is formed on a substrate in the product of the present invention, it can be formed in less than 1/9 of the area of a conventional substrate.
上述に示した条溝の製造方法では、溝深さを５０〜２０
０μｍ程度にすることができる。また、従来のの通常の
厚膜印刷方法では、膜厚は５〜２０μｍである。即ち、
線幅を１００μｍに設定したとには、導体の断面積を本
発明品では５０００〜２００００μｍ２であり、従来品
では５０〜２０００μｍ２であり、本発明品の断面積を
一桁も太きくすることができる。In the groove manufacturing method described above, the groove depth is set to 50 to 20 mm.
The thickness can be set to about 0 μm. Further, in the conventional conventional thick film printing method, the film thickness is 5 to 20 μm. That is,
Setting the line width to 100 μm means that the cross-sectional area of the conductor is 5000 to 20000 μm2 for the product of the present invention, and 50 to 2000 μm2 for the conventional product, and it is possible to increase the cross-sectional area of the product of the present invention by an order of magnitude. can.
尚、上述の実施例によれば、条溝に充填する導体材料を
銅として説明した。これは、電気伝導率が高く、マイグ
レーションを起こしにくいからであり、焼成温度や焼成
雰囲気、その他の材料、例えば抵抗体材料との組合せか
ら、銀や銀−パラジウムを用いても構わない。In addition, according to the above-mentioned Example, the conductor material filled in the groove was explained as copper. This is because it has high electrical conductivity and is difficult to cause migration, and silver or silver-palladium may be used depending on the firing temperature, firing atmosphere, and combination with other materials such as resistor material.
以上のように、本発明によれば、セラミック基板に形成
した条溝に導電性ペーストを充填し、基板と路間−面に
加工した厚膜配線上に、絶縁又は抵抗ペーストから成る
配線パターンを形成した厚膜回路基板であるため、高実
装密度の配線パターンの厚膜配線が可能であり、さらに
他の厚膜印刷膜体との接続を安定・確実にすることがで
きる。As described above, according to the present invention, conductive paste is filled in the grooves formed on a ceramic substrate, and a wiring pattern made of insulating or resistive paste is formed on the thick film wiring processed between the substrate and the track. Since the thick film circuit board is formed, thick film wiring with a wiring pattern of high packaging density is possible, and furthermore, the connection with other thick film printed film bodies can be made stable and reliable.
また、条溝に導電性ペーストを充填し、焼成後に不要な
導体膜の除去工程があるため、不要な導体膜とともに、
基板上に付着したゴミが研磨されるため、配線パターン
間のショートの原因を排除して、安定した回路が製造で
きる。In addition, since there is a process of filling conductive paste into the grooves and removing unnecessary conductive film after firing, along with the unnecessary conductive film,
Since dust adhering to the substrate is polished away, the cause of short circuits between wiring patterns can be eliminated and stable circuits can be manufactured.
第１図は本発明の厚膜回路基板の平面図であり、第２図
（ａ）〜（ｅ）は、本発明の厚膜回路基板の製造方法で
主要工程における断面図である。
厚膜回路基板
セラミック基板
厚膜配線
条溝
導体材料
絶縁体層
抵抗体膜
１０ ・ ・
ｌ ・ ・ ・
２ ・ ・ ・
３ ・ ・ ・
４ ・ ・ ・
５ ・ ・ ・
６ ・ ・ ・FIG. 1 is a plan view of the thick film circuit board of the present invention, and FIGS. 2(a) to 2(e) are sectional views of main steps in the method of manufacturing the thick film circuit board of the present invention. Thick film circuit board Ceramic board Thick film wiring groove Conductor material Insulator layer Resistor film 10 ・ ・ l ・ ・ 2 ・ ・ 3 ・ ・ 4 ・ ・ ・ 5 ・ ・ 6 ・ ・ ・
Claims (2)
ミック基板上に、絶縁体又は抵抗ペーストから成る厚膜
印刷パターンを形成したことを特徴とする厚膜回路基板
。(1) A thick film circuit board characterized in that a thick film printed pattern made of an insulator or a resistive paste is formed on a ceramic substrate having thick film wiring whose grooves are filled with a conductive material.
溝に導電材料を充填する工程と、 前記条溝以外の導電材料を研磨する工程と、条溝の厚膜
配線上に、絶縁体又は抵抗ペーストから成る厚膜印刷パ
ターンを形成する工程とを備えたことを特徴とする厚膜
回路基板の製造方法。(2) forming grooves on the ceramic substrate; filling the grooves with a conductive material; polishing the conductive material other than the grooves; or a step of forming a thick film printed pattern made of resistive paste.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8598990A JPH03284894A (en) | 1990-03-30 | 1990-03-30 | Thick film circuit substrate and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8598990A JPH03284894A (en) | 1990-03-30 | 1990-03-30 | Thick film circuit substrate and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03284894A true JPH03284894A (en) | 1991-12-16 |
Family
ID=13874088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8598990A Pending JPH03284894A (en) | 1990-03-30 | 1990-03-30 | Thick film circuit substrate and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03284894A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05226812A (en) * | 1992-02-18 | 1993-09-03 | Nec Corp | Printed wiring board and its manufacture |
| JP2008047613A (en) * | 2006-08-11 | 2008-02-28 | Jatco Ltd | Method for forming fixing part of surface mounting component to laminated ceramic substrate, method for fixing surface mounting component to fixing part, and laminated ceramic substrate used for these |
| JP2013038415A (en) * | 2011-08-05 | 2013-02-21 | Samsung Electro-Mechanics Co Ltd | Thin film electrode ceramic substrate and method for producing the same |
-
1990
- 1990-03-30 JP JP8598990A patent/JPH03284894A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05226812A (en) * | 1992-02-18 | 1993-09-03 | Nec Corp | Printed wiring board and its manufacture |
| JP2008047613A (en) * | 2006-08-11 | 2008-02-28 | Jatco Ltd | Method for forming fixing part of surface mounting component to laminated ceramic substrate, method for fixing surface mounting component to fixing part, and laminated ceramic substrate used for these |
| JP2013038415A (en) * | 2011-08-05 | 2013-02-21 | Samsung Electro-Mechanics Co Ltd | Thin film electrode ceramic substrate and method for producing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3958532B2 (en) | Manufacturing method of chip resistor | |
| JPS5846079B2 (en) | Multilayer wiring board manufacturing method | |
| JPH03284894A (en) | Thick film circuit substrate and manufacture thereof | |
| JP2000306711A (en) | Multiple chip resistor and production thereof | |
| JP3111823B2 (en) | Square chip resistor with circuit inspection terminal | |
| JP2806802B2 (en) | Chip resistor | |
| JPH05135902A (en) | Rectangular type chip resistor and manufacture thereof | |
| US5691690A (en) | Chip type jumper | |
| JP3121325B2 (en) | Structure of chip type resistor | |
| JPH03212901A (en) | Square board type chip resistor | |
| JPH0567882A (en) | Multilayer circuit board | |
| JPH07273447A (en) | Ceramic circuit board and its manufacture | |
| JP2002246206A (en) | Chip resistor and its manufacturing method | |
| JPH09246006A (en) | Rectangular chip resistor and its manufacture | |
| JPH0427180Y2 (en) | ||
| JPH11307899A (en) | Thick film circuit board and manufacture thereof | |
| JPS63296293A (en) | Formation of thick film circuit | |
| JPH05234702A (en) | Rectangular chip resistor, manufacture thereof, and string of taping parts therefor | |
| JPH09330802A (en) | Resistor and its manufacture | |
| JPH0758456A (en) | Manufacture of ceramic circuit board | |
| JPH08124701A (en) | Chip type resistor and manufacture thereof | |
| JPH03263301A (en) | Rectangular type chip resistor and manufacture thereof | |
| JP2003209001A (en) | Chip resistor | |
| JPH06152113A (en) | Mounting method for electronic component and conductive adhesive used therefor | |
| JPH10303001A (en) | Method for manufacturing square chip resistor |