JPH03284016A - Afc circuit for satellite broadcast receiver - Google Patents

Abstract

PURPOSE:To perform an AFC operation with high accuracy with simple configuration by correcting the output of a reference frequency oscillator which belongs to a PLL circuit, and suppressing the frequency drift of an intermediate frequency signal. CONSTITUTION:A reference oscillator(VCXO) 12a is comprised of an oscillator with comparatively high frequency stability though with narrow variable range, and a control voltage in proportion to the drift of a second intermediate frequency signal IF2 is supplied from the frequency discrimination part (f-V) 3a of a frequency demodulator (FM DEMOD) 3 to the control input of the oscillator. The control voltage generates the change of fr+ f(or fr- f) in the output of the oscillator 12a. The PLL circuit consisting of a local oscillator(VCO) 10, a fixed frequency divider 11, and a PLL synthesizer 12 follows the change f of reference oscillator output, and the output of the oscillator output L0 is changed so as to cancel the drift in the signal IF2 of the output of a mixer 2. In other words, a loop consisting of the PLL circuit comprises an AFC circuit, and loop control is performed so as to eliminate the drift of the signal IF2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an AFC circuit for a satellite broadcast receiver consisting of an outdoor unit and an indoor unit.

[Prior Art] In a satellite broadcasting receiving system, a frequency converter called a BS converter or LNC is attached to an outdoor parabolic antenna, etc., and a received signal converted to a first intermediate frequency by this converter is transmitted to a receiving unit, which is an indoor unit. is supplied to the machine. Frequency converters for outdoor units tend to drift in the output conversion frequency due to the influence of the environment such as temperature. For this reason, the satellite broadcasting receiver, which is an indoor unit, has an A that absorbs the frequency fluctuation of the first intermediate frequency signal.
An FC circuit is provided.

FIG. 2 shows a block diagram of the main parts of a tuner section of a conventional satellite broadcasting receiver. In this example, a general PLL synthesizer method is adopted. A first intermediate frequency signal IFI from an outdoor frequency converter is supplied from an amplifier 1 (AMP> to a mixer 2 (MIX>), which generates a second intermediate frequency signal IFI.
It is converted to F2 and taken out. Second intermediate frequency signal IF
is supplied to an FM demodulator 3 (FMDEMOD), and a demodulated signal containing video and audio is derived to a subsequent video and audio circuit. The local oscillation signal LO given to the mixer 2 is PL
It is formed in an L synthesizer type variable oscillator 4.

The variable oscillator 4 has a local oscillator 10 composed of a voltage controlled oscillator circuit (VCO), and its output is connected to a fixed frequency divider 11.
The PLL synthesizer 12 includes a variable frequency divider that further divides the fixed frequency divided output by a variable frequency division ratio, and a crystal oscillator 1.
3, and a phase comparator that compares the phases of these variable frequency-divided outputs and the reference oscillation output. The frequency division ratio of the variable frequency divider is determined according to tuning information (frequency setting data) from the control microcomputer 14. If there is a frequency difference between this variable frequency division output and the reference oscillation output, an error voltage is sent from the phase comparator of the synthesizer 12 to the local oscillator 10, so that its oscillation frequency changes. As a result, a loop consisting of the local oscillator 10, fixed frequency divider 11, and PLL synthesizer 12 is operated, and a local oscillation output of the frequency corresponding to the selected broadcast channel is obtained.

The control microcomputer 14 receives voltage data proportional to the drift of the second intermediate frequency signal IF2 from the frequency discriminator 3a (f-V) of the FM demodulator 3 via the A/D converter 15, and receives voltage data proportional to the drift of the second intermediate frequency signal IF2. Frequency correction data for canceling the difference is added to the frequency setting data of the channel selection information and is supplied to the variable frequency divider of the PLL synthesizer 12.

As a result, the second intermediate frequency signal IF2 of the output of the mixer 2
The drift component is removed from , and a stable frequency output is obtained. The above-mentioned mixer 2, FM demodulator 3 <frequency discriminator 3a
), A/D converter 15, microcomputer 14
, PLL synthesizer 12, and local oscillator 10 constitute an AFC circuit.

[Problems to be Solved by the Invention] Since the above-mentioned AFC circuit includes a PLL synthesizer type variable oscillator, there is a disadvantage that the frequency can only be controlled to be changed at frequency intervals.

The minimum frequency interval that can be controlled by AFC is [Reference frequency]
Xc fixed frequency division ratio]. This means that the local oscillation output LO is approximately 100kHz for a change in the LSB (one bit) of the frequency correction data given from the control microcomputer 14 to the variable frequency divider of the PLL synthesizer 12.
This corresponds to the AFC circuit having a loop gain that causes a change in z.

With this level of AFC accuracy, there is a concern that the pit error rate will increase in high-definition broadcasting, PCM audio broadcasting, data broadcasting, etc. that handle digital signals.

It is possible to increase the AFC accuracy to about 10 kHz/1 bit, but if the frequency division ratio of the PLL synthesizer is changed for this purpose, problems such as unstable operation of the PLL will occur.

It is an object of the present invention to solve the above-mentioned problems and to obtain a relatively simple and highly accurate AFC operation.

[Means for Solving the Problems] The AFC circuit of the satellite broadcast receiver according to the present invention detects the frequency fluctuation of an intermediate frequency signal obtained by mixing a local oscillation output and a satellite broadcast reception signal, and Equipped with A and FC loops that correct the output frequency of the oscillator.

The AFC loop is a PLL configured to compare the phases of the output of the reference frequency oscillator and a signal obtained by frequency-dividing the output of the local oscillator based on channel selection information, and control the output frequency of the local oscillator based on the comparison output. Equipped with a circuit.

The reference frequency oscillator is composed of a variable frequency oscillator, and the frequency fluctuation detection signal of the intermediate frequency signal is output from the reference oscillator and the output from the local oscillator is frequency-divided based on the channel selection information. In comparison, a PLL circuit configured to control the output and internal frequencies of the local oscillator using a comparison output is provided.

The reference frequency oscillator is comprised of a variable frequency oscillator, and is characterized in that it supplies a detection signal of frequency fluctuation of the intermediate frequency signal to a control input for the output frequency of the reference frequency oscillator.

[Operation] The output frequency of the reference frequency oscillator is modulated (FM) by the frequency fluctuation of the intermediate frequency signal, and the modulation is P
This appears as a change in the output frequency of the local oscillator through the LL circuit. Therefore, the AFC loop operates so that the drift of the undesirable intermediate frequency signal by mixing the local oscillation output and the input received signal is canceled.

The PLL circuit changes the frequency of the local oscillation output in accordance with the channel selection information, and operates to follow the frequency change of the reference frequency oscillator in a linear relationship.

[Embodiment] FIG. 1 shows a block diagram of essential parts of a satellite broadcasting receiver according to an embodiment of the present invention. Note that the same parts as in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 1, broadcast radio waves from a broadcasting satellite 20 are received by a parabolic antenna 21, converted to a first intermediate frequency signal IFI by an outdoor unit 22 (frequency converter), and then transmitted through a cable 23 to an indoor unit 24 (satellite broadcast receiver). machine).

The first intermediate frequency signal IFI input to the input terminal T1 of the indoor unit 24 is given to the mixer 2 via the filter 1 as in FIG. 2, where it is converted to the second intermediate frequency signal IF2 and then , are derived to the FM demodulator 3. The demodulated signal output from the FM demodulator 3 is separated into a video signal and an audio signal in a video circuit 5 and an audio circuit 6, and introduced into output terminals T2 and T3, respectively. Further, the demodulated output of the FM demodulator 3 is led out to the output terminal T4 as a detection output signal.

A variable oscillator 4 that provides a local oscillation output to the mixer 2 is a second
Similar to the figure, the PLL synthesizer system is adopted, and a variable PLL circuit consisting of a local oscillator 10, a fixed frequency divider 11, and a PLL synthesizer 12 is provided. The PLL synthesizer 12 includes a variable frequency divider that divides the frequency division output of the fixed frequency divider 11 by a variable frequency division ratio, and a phase difference that compares the phase of the variable frequency division output with the reference frequency output fr from the reference oscillator 12a. It is equipped with a comparator. The frequency division ratio of the variable frequency divider of the PLL synthesizer 12 is based on the tuning information (frequency setting data) given from the control microcomputer 14.
determined according to When the frequency division ratio is set, the local oscillation output LO corresponding to the selected broadcast channel is
is obtained by the loop operation of

The reference oscillator 12a is a voltage controlled crystal oscillator (■CX0)
The control input is a second intermediate frequency signal IF from the frequency discriminator 3a (f-V) of the FM demodulator 3.
A control voltage proportional to the drift of 5 is applied. This control voltage causes a change of fr+Δf (or fr−Δf) in the output of the reference oscillator 12a. A PLL circuit consisting of a local oscillator 10, a fixed frequency divider 11, and a PLL synthesizer 12 follows this change Δf in the reference oscillation output,
The frequency of the local oscillation output (○) changes so as to cancel the drift in the second intermediate frequency signal output from the mixer 2.

That is, the mixer 2, the frequency discriminator 3a of the FM modulator 3,
A loop consisting of the reference oscillator 12a, PLL synthesizer 12, and local oscillator 10 constitutes an AFC circuit, and loop control is performed so that the drift of the second intermediate frequency signal IF2 is eliminated.

Since the drift of the second intermediate frequency signal IF2 is about several hundred Hz, the frequency variable range of the reference oscillator 12a may be narrow, and can be realized by a relatively simple circuit in which a variable capacitance diode is incorporated into a crystal oscillator.

In addition, since the above-mentioned AFC circuit operates in the analog domain regardless of the digital control part (variable frequency divider) of the PLL synthesizer 12, linear drift canceling performance without steps can be obtained, and highly accurate AFC operation can be achieved. It becomes possible.

Note that the A/D required in the conventional AFC circuit shown in Figure 2
Since the converter 15 is not required in the AFC circuit of the embodiment shown in FIG. 1, there is an advantage that the circuit configuration is simplified.

[Effects of the Invention] As described above, the present invention suppresses the frequency drift of the intermediate frequency signal by correcting the output frequency of the reference frequency oscillator attached to the PLL circuit.
Highly accurate AFC operation can be obtained with a relatively simple configuration. In particular, in a tuner with a PLL synthesizer configuration, such as a conventional AFC circuit, there are problems caused by adding or subtracting data for drift correction to local oscillation frequency control data according to tuning information. Since the output frequency of the oscillator is changed stepwise, the drawback that fine correction within one step width was not possible is corrected, and almost complete drift correction becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a satellite broadcasting receiver showing an embodiment of the present invention, and FIG. 2 is a block diagram of the main parts of a conventional AFC circuit. DESCRIPTION OF SYMBOLS 1... Amplifier, 2... Mixer, 3... FM demodulator, 3a... Frequency discrimination part, 4... Variable oscillator, 10
... Local oscillator, 1], ... Fixed frequency divider, 12...
- PLL synthesizer, 12a... Reference frequency oscillator, 14... Microcomputer, 20... Broadcasting satellite, 21... Parabolic antenna, 22... Outdoor unit.

Claims (1)

[Claims] The above-mentioned system comprises an AFC loop configured to detect frequency fluctuations in an intermediate frequency signal obtained by mixing a local oscillation output and a satellite broadcast reception signal, and correct the output frequency of the local oscillator. The AFC loop is a PLL configured to compare the phases of the output of the reference frequency oscillator and a signal obtained by frequency-dividing the output of the local oscillator based on channel selection information, and control the output frequency of the local oscillator based on the comparison output. A satellite broadcasting receiver comprising a circuit, wherein the reference frequency oscillator is configured with a variable frequency oscillator, and supplies a detection signal of frequency fluctuation of the intermediate frequency signal to an output frequency control input of the reference frequency oscillator. AFC circuit.