JPH03283980A - Picture recording and reproducing device - Google Patents

Abstract

PURPOSE:To improve the quick-review speed and to relieve a load exerted onto a mechanism part and a tape by dividing a still picture into plural picture element groups each comprising same number of picture elements as a split still picture and observing one split still picture while feeding the tape in the high speed reproduction state. CONSTITUTION:When a quick-review switch is operated, a high speed drive signal F/R is outputted and a tape 26 is driven at a fast speed while being in contact onto a circumferential face of a rotary cylinder 23. While keeping the rotary speed of the rotary cylinder 23 as the speed of the normal reproduction, when the drive speed of the tape 26 is increased, the locii of recording and reproducing heads i4, 25 tracing the tape 26 intersect a helical track. Then picture element data of each part of plural split still pictures are collected and recorded in a quick-review memory 43 to form one picture. On the other hand, the written picture element data in the quick-review memory 43 is sequentially read in a prescribed timing and extracted from an output terminal 39 and used for picture display.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is directed to recording and reproducing digitized still images in a helical scan type tape recording and reproducing device, such as a rotary head type digital audio tape recorder. The present invention relates to an image recording and reproducing apparatus for recording and reproducing signals, and particularly to one for reproducing still image signals recorded on a tape at high speed.

(Prior Art) As is well known, rotary head type digital audio recorders have been developed and are widely used in the market for the purpose of recording and reproducing digitized audio signals on magnetic tape. Since this digital audio tape recorder basically records and plays back digitized signals, it is also possible to digitize and record and play back still image signals in addition to audio signals. Development in this direction is actively underway. By the way, while digital audio recorders have a very large storage capacity and can record a large amount of data, they can be difficult to use if they lack the search ability to quickly retrieve the desired data. This causes the inconvenience of being lost.

Therefore, in order to improve the search ability, search means have been devised that play back tapes at high speed to quickly view still images. That is, to record a still image signal in a digital audio tape recorder, first, the still image signal for one screen is converted into digital data, and once each pixel is written into a memory M such as a RAM, as shown in FIG. let In this case, each pixel data of the still image signal is sequentially written in one-to-one correspondence to each memory element in the memory M, as shown by the circles in FIG.

The still image signal for one screen written in the memory M in this way is composed of a plurality of (16 in the illustrated case) pixel groups Gl, G2 . . . each including the same n pixels.・
..., divided into G16.

Here, each of these pixel groups Gl, G2 .・・・・・・G
Among the n pixels constituting IB, the same numbers 1, 2, . . . . is indicated by adding n, and when pixels with the same number are read out from the memory M and put together, n divided still images obtained by roughening the original still image are obtained, as shown in FIG. 11. (11, +21
...... (nJ will be formed. Then, these n divided still images (11, +2], ...
... The pixel data constituting fnl is sequentially recorded on a magnetic tape by a digital audio chip recorder.

Figure 12(a) shows the recording format on tape T when still images 1 and 2 for one screen are recorded consecutively, and each screen is divided into four images as n-4. Still image +11. +21 (3+, +41 is recorded).

That is, at the beginning of the recording position of each still image 1 and 2,
A header signal is recorded in two helical tracks (-1 frame) to distinguish each still image from other still images, and to add additional information and use it as search information.Following the header signal, Divided still image full, +21.
(31 (41 each has 2 helical tracks (-1
frame).

When reproducing the still image signal recorded on the tape T in this way, each divided still image [1, +
21. (3), (Each pixel data obtained by reproducing 4+ is recorded at the location of the memory M corresponding to the original original still image. In other words, each divided still image obtained in the form shown in FIG. Image (11, +21. +31. (4+
The pixel data is returned to the recording position of the memory M corresponding to the original still image shown in FIG. 10 and recorded. By sequentially reading out the pixel data recorded in this memory M, the original still image signal can be reproduced and displayed as an image.

In addition, in a search state in which the tape T is played back at high speed and a still image is viewed quickly, as shown in FIG. Subsequently, the divided still image (1) is read and recorded in the memory, and the image is displayed. By displaying this divided still image (1), the searcher can know the general content of the original image. Then, the remaining divided still images +21. (31, (41 does not need to be viewed, so the tape T is run at high speed and after a predetermined period of time has elapsed, the tape T is run again in a normal playback state to display the next still image. As a result, since the tape T is running at high speed, the speed of quick viewing can be increased and the search time can be shortened.

However, with the conventional search means as described above, the recording time for one screen's worth of still image signals is approximately several seconds, so even if the tape T is run at high speed, it will immediately switch to the playback state. Therefore, the speed of the tape T during high-speed running cannot be sufficiently increased, and as a result,
A problem has arisen in that the quick viewing speed in the search state is at most three times faster than in normal playback. In addition, since the running speed of the tape T changes drastically in a short period of time,
The wear and tear of the mechanical parts is large, shortening the life of the system, and the change in tension on the tape T is also large, resulting in the inconvenience that recorded signals tend to deteriorate.

(Problems to be Solved by the Invention) As described above, in the conventional image recording and reproducing apparatus that attempts to digitize still image signals and record and reproduce them on tape,
The problem is that the search speed for searching for a desired still image, that is, the quick viewing speed is slow, and the load on the mechanism and the tape is large, resulting in poor reliability.

Therefore, the present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide an extremely good image recording and reproducing device that improves quick viewing speed and can be fully put to practical use without adding unnecessary loads to the mechanism or tape. The purpose is to

[Structure of the Invention] (Means for Solving the Problems) An image recording and reproducing device according to the present invention has a rotating head and uses a helical scanning method to record a digitized still image signal on a tape, and also records a digitized still image signal on a tape. It is aimed at those who play the.

Then, the still image is divided into a plurality of pixel groups each having the same number of pixels, and pixel signals at corresponding positions of each of these divided pixel groups are respectively extracted to form a plurality of divided still images. The recording means records the pixel signals constituting the divided still images sequentially on the tape for each divided still image, and the recording means reads the pixel signals recorded on the tape by running the tape at high speed. A high-speed reproduction means for traversing a plurality of helical tracks formed on a tape and combining pixel signals constituting a plurality of divided still images partially read from each helical track to constitute one divided still image. The apparatus is configured to display one divided still image formed by a high-speed reproduction means.

(Function) According to the above configuration, the still image recorded on the tape can be viewed quickly by viewing one divided still image formed by the high-speed playback means while the tape is in the high-speed playback state. Therefore, the quick viewing speed can be improved. In addition, unlike in the prior art, since reproducing running and high-speed running are not performed alternately, unnecessary loads are not applied to the mechanical section or the tape, and the tape can be put to practical use.

(Example).

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, 11 is an input terminal to which an analog still image signal is supplied. This input terminal 1
The still image signal supplied to 1 is an A/D (analog/
After being converted into digital data by a digital conversion circuit 12, one screen worth of pixel data is written into a memory 13. As explained earlier in FIG. 10, this memory 13 is
It has memory elements designated by vertical and horizontal addresses, and image data corresponding one-to-one is written to each memory element. In addition, each pixel data recorded in the memory 13 is the aforementioned n divided still images (11, i2+, . . .
..., (n) are read out sequentially.

Here, pixel data is written to and read from the memory 13 by selectively selecting the recording address and the reproduction address output from the recording address generation circuit 14 and the reproduction address generation circuit 15, respectively, using the switch 16 depending on the writing and reading times. This is done by supplying the data to the memory 13. In this case, the A/D conversion circuit 12 and recording address generation circuit 14 synchronize with the tarok signal output from the synchronization detection clock generation circuit 17 to which the still image signal supplied to the input terminal 11 is supplied.
It performs A/D conversion operations, recording address generation, etc.

Each divided still image f11. read from the memory 13 is then read out from the memory 13. The pixel data for each (21..., (n)) is interleaved in the interleave processing circuit 18, added with a predetermined parity code for error correction processing in the error correction processing circuit 19, and then The block generating circuit 20 converts the data output from the error correction processing circuit 19 into a block-by-block format suitable for recording and playback in a digital audio tape recorder. In this case, each block converted by the block generation circuit 20 is given a block number output from the block number generation circuit 21.

The data outputted from the block generation circuit 20 and converted into a block-by-block format in this way is combined into continuous data, and
After being subjected to digital modulation processing necessary for magnetic recording, the data is helically recorded onto the tape 26 via two recording/reproducing heads 24 and 25 installed on the rotary cylinder 23.

In the recording operation state described above, the rotary cylinder 23 is fixed at a constant rotational speed, and the tape 26 is rotated between the pinch roller 27 and a predetermined guide roller 282.
It is running at a constant speed by 9th grade. Note that the recording operation described above is totally controlled by the recording timing generation circuit 30.

Here, as is well known in the digital audio recorder, two recording/reproducing heads 24.2 are used during recording.
The helical track formed by tape 26
The recording and reproducing heads 24 are arranged alternately on the
The recording/reproducing head 24 traces the helical track formed by the recording/reproducing head 25, and the recording/reproducing head 25 traces the helical track formed by the recording/reproducing head 25. The two helical tracks formed by the two recording/reproducing heads 24 and 25 are collectively referred to as one frame. Among these, one helical track consists of 128 blocks, and one helical track consists of 128 blocks.
As shown in Figure 2, the block receives an 8-bit synchronization signal 5YNC, a 24-bit control signal, and a 256-bit
It consists of bit data.

The control signals are WtW2. It consists of 8-bit data called P. Of these, data W2, as shown in Figure 3, indicates the program number (0 to 127) in its lower 7 bits BO-86, and the most significant bit B7 indicates the distinction from the subcode area. ing. Further, the data Wl is recorded with a frame address representing a frame number only when the block number of the corresponding data W2 is 0 or an even number.
By reading this frame address, it is possible to know which frame in one helical track it is. Furthermore, data P is WI
+W2, which is a parity code for error correction of data Wl and W2.

Here, the 256-bit data is divided into units of 8 bits called one symbol, and one block of data is made up of 32 symbols. Now, if the block number is 1 (-0 to 127) and the symbol number is j (-0 to 31), and any one symbol in one helical track is expressed as Dlj, then the arrangement of each symbol in one helical track is is as shown in FIG. That is, one vertical column in FIG. 4 indicates symbols (0 to 31) in one block, and there are block numbers 0 to 127 and 128 from the left in the figure.

Note that each symbol in one block is recorded and reproduced from top to bottom in FIG.

Furthermore, an eight-symbol error correction code P is added to the end of two adjacent blocks. Further, in addition to the error correction code P, another error correction code Q is added to block numbers 52 to 75. In this case, as shown in FIG. 5, the error correction code P is such that 4 symbols are added to each of the even and odd symbols in two adjacent blocks, and the above symbol numbers are even and odd. and odd numbered symbols are 4-symbol error correction code P
This allows error detection and correction to be performed separately for each. Furthermore, the error correction code Q has a block number of 0.4 for each symbol arranged horizontally in FIG.
,8. ... symbol and block number 2
．． 6,10. ... symbol and block number 1.5.9. 6 for symbols with block numbers 3.7, 11゜... excluding block numbers 52 to 75.
Each symbol is added, and errors can be detected and corrected individually.

Here, if an arbitrary divided still image is (i) and each pixel data is ir (rml~n), then tape 2
The recording format of each pixel data ir on the 6th
The result will be as shown in the figure. However, in reality, the arrangement of each pixel data ir is interleaved as described above, so it is not recorded in the order shown in FIG. 6, but the recording order of each pixel data ir is Since the frame remains the same even if the frame changes, it can be easily restored by a predetermined conversion operation. For example, if a ROM or the like is used, the position information of each reproduced pixel data IR is set as an address in the ROM, and the position information of each pixel data IR before interleaving processing is stored in that address, conversion can be easily performed. . Note that each pixel data ir of the divided still image (i) is usually composed of an 8-bit Y (luminance) signal and an 8-bit Y (luminance) signal.
Although it is combined with a bit C (color) signal,
These are regularly arranged in the format shown in FIG. 4 at the stage of interleaving processing.

Next, reproduction of the tape 26 will be explained. That is,
Each reproduction signal obtained from the recording and reproduction heads 24 and 25 is
After being amplified by the regenerative amplification circuit 31 and subjected to digital demodulation processing corresponding to the digital modulation processing previously performed by the digital modulation circuit 22 in the digital demodulation circuit 32, the signal is supplied to the block regeneration circuit 33 and processed in block units. Data playback is performed. The reproduced data output from this block reproduction circuit 33 is supplied to an error detection and correction circuit 34. This error detection and correction circuit 34 detects errors in symbols in one block based on error correction codes (P) and (Q) and performs correction processing, and when error correction processing is impossible, outputs an error flag F.

The data and error flag F output from the error detection and correction circuit 34 are sent to the deinterleave processing circuit 35.
A deinterleaving process is performed to remove the interleaving process previously performed by the interleaving process circuit 18. Here, since the block number and data arrangement within the block are known in advance, it is possible to know which data in one frame it is, and also to know which position of the divided still image (IT) the data is. The output of the deinterleave processing circuit 35 is exactly the same as the readout output of the memory 13 during recording.

Thereafter, the divided still images (11, (21,...inJ
Each pixel data is written to the memory 36. In this case, the memory 36 stores divided still images +11 (2+
, . . . The pixel data divided into (n) units are rearranged and written at positions constituting the original still image. The address at this time may be the same as the reproduction address at the time of recording.

Each pixel data written in this memory 36 is sequentially read and compared and converted into an analog signal by a D/A (digital/analog) conversion circuit 38 via a switch 37, thereby converting it into an original still image signal. It is reproduced and taken out from the output terminal 39.

Note that writing and reading pixel data to and from the memory 36 is performed by selectively using a switch 42 to select the recording address and reproduction address output from the recording address generation circuit 40 and the reproduction address generation circuit 41, respectively, depending on the writing and reading operations. This is done by supplying the memory 36.

On the other hand, each divided still image (11, (2+, ...... (nl
The pixel data of is supplied to the quick reference memory 43. This quick reference memory 43 stores each divided still image (11, +
21 ...... (n) has a capacity for recording one disc, and the recording address and reproduction address outputted from the recording address generation circuit 44 and the reproduction address generation circuit 45, respectively, are controlled by the switch 46. Writing and reading operations are performed by being selectively supplied depending on writing and reading. In this case, the write and read operations of the quick reference memory 43 are controlled based on the read/write signal R/W output from the deinterleave processing circuit 35. The pixel data read from the quick-view memory 43 is guided to the D/A conversion circuit 38 selectively with the pixel data read from the memory 36 by a switch 37.

Here, the reproduction signal output from the reproduction amplification circuit 31 is supplied to a clock signal reproduction circuit 47. The clock signal reproduction circuit 47 reproduces a clock signal for data reproduction based on the input reproduction signal and outputs it to the reproduction timing signal generation circuit 48. The reproduction timing signal generation circuit 48 generates the timing signals necessary for the reproduction address generation circuits 41 and 45 based on the input clock signal, and also generates the timing signals necessary for the block timing generation circuit 49. be. The block timing generation circuit 49 detects the synchronization signal 5YNC of the block and counts the clock signals output from the clock signal generation circuit 47 using this detection time as a starting point, thereby generating all the symbols in the block. Identify the position and block regeneration circuit 33. It generates various timing signals necessary for controlling the deinterleave processing circuit 35 and recording address generation circuits 40 and 44.

In addition, in the normal reproduction state as described above, the reproduction signal output from the reproduction amplifier circuit 31 and the rotation cylinder 23
A tack signal T representing the rotational speed of the rotary cylinder 23 is supplied to the comparator circuit 50, and an error signal is compared with a predetermined reference signal.
The rotation speed is controlled. At this time, the reproduction signal output from the reproduction amplifier circuit 31 is simultaneously supplied to the ATF (automatic track finding) signal generation circuit 51, and the helical track already formed on the tape 26 and the recorded It is used to generate a relative position detection signal with respect to the trajectory traced by the playback heads 24 and 25 on the tape 26. This relative position detection signal is selected by the switch 52 and used to control the rotational speed of the pinch roller 27, so that the running speed of the tape 26 is controlled to be constant.

Furthermore, the high speed running state of the tape 26 will be explained.

First, when a fast forward or rewind operator (not shown) is operated to request high-speed running of the tape 26, the switch 52 is switched to the timing generation circuit 53 side.

This timing generation circuit 53 generates a high-speed drive signal F/R when high-speed running of the tape 26 is requested. When this high-speed drive signal F/R is selected by a switch 52, the pinch roller 27 is rotated. By being subject to speed control, the tape 26 is run at high speed.

Next, a case will be described in which the tape 26 is played back at high speed to quickly view still images. That is, when the quick reference switch (not shown) is operated, the switch 52 is switched to the timing generation circuit 53 side, and the timing generation circuit 53 outputs the high-speed drive signal F/R. Therefore, the tape 26 is run at high speed while being in contact with the surface of the rotating cylinder 23. Furthermore, when the quick reference switch is operated, a switch 54 connected to the timing generation circuit 53 is turned on. Then, the timing generation circuit 53 turns on the switch 55 that bypasses the error detection and correction circuit 34, and also turns on the switch 37 that selects each output data of the memory 36 and the quick reference memory 43 to the quick reference memory 43 side. Switch. Note that at this time, the rotating cylinder 23 is being rotated at the same speed as during normal reproduction.

That is, when the rotational speed of the rotary cylinder 23 remains the same as during normal reproduction, and the running speed of the tape 26 is increased, the trajectory when each recording/reproducing head 24, 25 traces on the tape 26 is as shown in FIG. It begins to cross the helical track as shown by arrow A. In this case, among the helical tracks formed on the tape 26, the recording/reproducing head 2
If the helical track corresponding to T25.4 is T24, and the helical track corresponding to the recording/reproducing head 25 is 725, then the recording/reproducing head 24.25 is connected to the uncorresponding helical track T25. Even if T24 is traced, the signal is not picked up, so the effective portion G of the reproduced signal obtained from each recording/reproducing head 24.degree. 25 is discontinuous, as shown in FIG. Here, the valid part means a signal when all two blocks of data can be read and error correction is possible, and other parts are invalid.

In other words, the reproduction signal obtained from each recording/reproduction head 2425 in the quick viewing state is transmitted to the reproduction amplification circuit 31.
After passing through the digital demodulation circuit 32 and the block reproduction circuit 33, the signal bypasses the error detection and correction circuit 34 by the switch 55 and is supplied to the deinterleave processing circuit 35.

In this case, the error detection and correction circuit 34 performs error detection using an error correction code (P) on the data output from the block reproduction circuit 33, and when an error is detected, the error flag F is sent to the deinterleaving processing circuit 33. I am trying to output it to . This is because the error detection using the error correction code (P) is for two adjacent blocks, so the recording/reproducing head 24.25
This is because even if the signal is reproduced so that it crosses the helical track, error detection can be performed with some degree of reliability. On the other hand, since error detection using an error correction code (Ql) covers the entire block of one frame, it is meaningless when the recording/reproducing head 24 or 25 is used to perform reproduction across a helical track. Because it will be.

Each divided still image +11. is output from the deinterleave processing circuit 35. f2),...(n
The pixel data of l is written into the quick reference memory 43. In this case, of the pixel data output from the deinterleave processing circuit 35, only those determined to be valid (not including those with the error flag F attached) are written into the quick reference memory 43. That is, the pixel data of each part of a plurality of divided still images are collected and recorded in the quick viewing memory 43 to form one image.

Then, as the tape 26 continues to run at high speed,
Pixel data written to the same position in the quick reference memory 43 is sequentially rewritten with newly obtained pixel data.

On the other hand, the written pixel data is sequentially read out from the quick reference memory 43 at a predetermined timing, and the switch 37
The data is then taken out from the output terminal 39 via the D/A conversion circuit 38 and is provided for image display, where it is possible to quickly view the image by playing back the tape 26 at high speed.

Here, the deinterleave circuit 35 is configured as shown in FIG. 9. That is, the write clock, which is one of the timing signals outputted from the block timing generation circuit 49, is supplied to the counter 57 via the control terminal 56, and the count value of the counter 57 is used as a recording address via the switch 58. The image data supplied to the input terminal 60 is supplied to the memory 59.
to be recorded. After that, the block timing generation circuit 49
A read clock, which is one of the timing signals output from the ROM 61, is supplied to the counter 57 via the control terminal 56, and data is read from the ROM 61 using the count value of the counter 57 as a playback address. The switch 58 uses the data as the playback address.
The image data is supplied to the memory 59 via the output terminal 62, and the image data recorded in the memory 59 is taken out from the output terminal 62.

Furthermore, if the number of pixels in one divided still image is large and cannot be recorded in one frame, one divided still image may be recorded in two frames. In this case, interleave processing and deinterleave processing are performed over two frames. That is, pixel data may be distributed and recorded in two frames, error detection and correction during reproduction may be performed in units of frames, and deinterleaving processing may be performed in units of two frames.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As described in detail above, the present invention provides an extremely good image recording and reproducing device that improves quick viewing speed and can be fully put to practical use without adding unnecessary loads to the mechanism or tape. can do.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image recording and reproducing apparatus according to the present invention, FIG. 2 is a diagram showing the data structure of one block, and FIG. 3 is a diagram showing details of control signals in one block. , FIG. 4 is a diagram showing a state in which all data symbols in one helical track are arranged together, FIG. 5 is a diagram for explaining the error correction code of the same data symbol, and FIG. Figure 7 shows the recording format of pixel data on tape, Figure 7 shows the relationship between the helical track and the trajectory of the recording/playback head during high-speed playback, and Figure 8 shows the effectiveness of block data obtained during high-speed playback. FIG. 9 is a block diagram showing the details of the deinterleaving processing circuit of the same embodiment, and FIGS. 10 and 11 are diagrams for explaining how one screen of still images is divided into multiple divided still images. FIG. 12 is a diagram for explaining the conventional search means. 11... Input terminal, 12... A/D conversion circuit, 13
...Memory, 14... Recording address generation circuit, 15
...Reproduction address generation circuit, 16...Switch, 1
7... Synchronization detection clock generation circuit, 18... Interleave processing circuit, 19... Error correction processing circuit, 2
0...Block generation circuit, 21...Block number generation circuit, 22...Digital modulation circuit, 23...
Rotating cylinder, 24.25... Recording/reproducing head, 26
...Tape, 27...Pinch roller, 28.29.
...Guide roller, 30...Record timing generation circuit, 31...Reproduction amplification circuit, 32...Digital demodulation circuit, 33...Block reproduction circuit, 34...' error detection and correction circuit, 35. ...Deinterleave processing circuit,
36...Memory, 37...Switch, 38...D
/A conversion circuit, 39...output terminal, 40...recording address generation circuit, 41...reproduction address generation circuit, 4
2...Switch, 43...Memory for quick reference, 44...
- Recording address generation circuit, 45-0. Reproduction address generation circuit, 46... switch, 47... clock signal generation circuit, 48... reproduction timing signal generation circuit, 49
...Block timing generation degree circuit, 5'0... Comparison circuit, 51... ATF signal generation circuit, 52... Switch, 53... Timing generation circuit, 54.55.
...Switch, 56...Control terminal, 57...Counter, 58...Switch, 59...Memory, 60...
・Input terminal, 61...ROM, 62...output terminal.

Claims (1)

[Claims] In an image recording and reproducing apparatus that has a rotating head and uses a helical scan method to record a digitized still image signal on a tape and also plays back the tape, the still image is recorded in a plurality of pixel groups each having the same number of pixels. The pixel signals at corresponding positions of each of these divided pixel groups are extracted to form a plurality of divided still images, and the pixel signals constituting the plurality of divided still images are divided into each divided still image. a recording means for sequentially helically recording the tape on the tape; and a recording means for reading the pixel signals recorded on the tape by running the tape at high speed, and a reproducing head reads a plurality of helical tracks formed on the tape. and high-speed reproduction means for composing one divided still image by combining pixel signals constituting the plurality of divided still images partially read from each helical track by traversing the helical track, the high-speed reproduction means comprising: An image recording and reproducing apparatus characterized in that it is configured to display a single divided still image obtained by dividing the image.