JPH03283080A - Semiconductor memory of bitlinf multi-time crossing - Google Patents

Abstract

PURPOSE: To reduce noise interference by making complimentary bit lines intersect each other, and decreasing the differential effect of undesirable signals induced therein. CONSTITUTION: A pair of complimentary bit lines 26 and 28 intersects each other at a point 46 so that one section of the bit line 26 is adjacent to a data bus conductor 24, and one section of the bit line 28 is also adjacent to the conductor 24. Therefore, an undesirable signal entering the upper bit line section 26 due to parasitic capacity 38 has a same intensity as an undesirable signal entering the upper section of bit line 28 due to parasitic capacity 40. Similarly, parasitic capacities 42 and 44 connect voltages of a same intensity to each lower section of the bit lines 26 and 28 respectively. And the intersected bit lines 26 and 28 induce undesirable signals in both bit lines 26 and 28 and reduces the differential effect. Thus, noise interference in memory is reduced.

Description

[Detailed description of the invention]

[0001]

[Industrial application field]

TECHNICAL FIELD The present invention relates to semiconductor memories, and in particular to complementary bits.
A method and apparatus for reducing noise interference in line-based memories. [0002]

[Conventional technology and its problems]

Efforts continue to develop semiconductor memories that are less sensitive to internally and externally generated noise signals. As the cell size of each generation of memory decreases, the voltage representing a stored digital 1 or O also decreases. Therefore, if a noise signal enters the low-level signal line of the memory, it will adversely affect the reliability of the memory. [0003] In well-known core memories that use toroidal magnetic cores as memory elements, bit line wire pairs that carry input current and output power to the magnetic core assembly are twisted together while the wires carry small data signals. This reduced electromagnetic interference. In this way, undesired signals are induced in both wires of the bit line with the same strength. If the amplitude of the signals induced in both wires is the same, then when the state of the magnetic core changes, even with common mode noise, the differential sense amplifier
The small analog signals generated can be easily detected. [0004] For semiconductor memories, which are currently mostly used, problems caused by induced noise signals cannot be easily solved. The problem in semiconductor memories is even more severe when metal or polysilicon conductive lines are separated by only a few microns. If such a close signal line carries a 5 volt logic signal, for example, that signal may be capacitively coupled to another signal line, such as a memory bit line. Semiconductor memory sense amplifiers have become extremely complex in order to be extremely sensitive to memory read signals while being highly rejective to noise signals on the bit lines. [0005] In microprocessor chips that have bidirectional data and address buses connected to other circuits on the chip, the potential for noise interference with the microprocessor memory located on the chip increases. In modern microprocessor designs, it is advantageous to create memory at a subsurface level and data or address lines above the memory. This is advantageous both from the standpoint of connecting the data bit lines to the memory inputs and from the standpoint of connecting the outputs of the memory to the data lines. Space is also saved. This type of configuration typically has the potential to induce unwanted electrical signals from the data or address lines to the bit lines of the memory. [0006] This noise interference problem is complicated in memory designs that use complementary bit line configurations. This type of memory requires two low level signal bit lines per cell, both for writing data to the cell and for reading data from the cell. High level logic signal transitions on the upper conductor, or on the conductor adjacent to the complementary bit line, are capacitively coupled to the bit line by a disproportionate amount. In this case, the differential sense amplifier cannot distinguish between the induced noise and the legitimate signal read from the memory cell. [0007] As can be seen from the above, there is a need for a semiconductor memory structure that reduces susceptibility to memory bit line induced noise signals. In this regard, there is a need for a complementary bit line structure that reduces the effects of bit line induced noise signals. [0008]

[Summary of the invention]

In accordance with the present invention, a complementary bit line memory structure is disclosed that substantially reduces or eliminates the disadvantages associated with corresponding prior art circuits. According to the memory structure of the present invention, the metal or polysilicon conducting complementary bit lines are
Crossovers are made where unwanted signals may be induced. In split or partitioned memory designs, it is preferred to have complementary bit lines intersect at a point between memory cell sections for electrical balancing purposes. When crossed, each negative bit line is exposed to the same noise potential, so the bit line
The differential level of unwanted noise signals in the line pair is reduced. [0009] The intersection of complementary bit lines causes the crossing member to
This is accomplished by forming it as a polysilicon conductive line. An elongated bit line is located on a second level isolated from the polysilicon member by silicon dioxide;
or made as an upper metal conductor. Contacts are made through the silicon dioxide to connect the polysilicon member to the appropriate ends of the metal bit lines to form a crossed bit line. [0010] Another technical advantage of the present invention comprises cross-connected bit line pull-up means that operate in conjunction with crossed bit lines. One bit line drives a P-channel transistor that can drive the other bit line to a logic high level. Similarly, the other bit line is connected to pull up the one bit line through a P-channel transistor. Therefore, when reading a memory cell causes one bit line to go slightly low positive, the other bit line is automatically pulled up by the pull-up means.
Provides positive voltage feedback for memory cell read operations. This positive feedback enhances the effectiveness of differential cell readout. Unwanted negative voltages induced on both bit lines of the crossed complementary pair are also suppressed by being pulled back to a high voltage by the cross-coupled pull-up transistors. [0011] The noise immunity of the memory cell can be further enhanced by using an N-channel transistor in series with the bit line in the column or word line select portion of the memory. By using N-channel transistors as column select devices in the bit lines, noise signals whose amplitude is less than the limiting voltage of the N-channel transistors cannot be interpreted as legitimate signals read from the memory. [0012] Other features and advantages will become apparent from the following detailed description of the preferred embodiments of the invention, which are illustrated in the accompanying drawings. In the drawings, the same reference numbers indicate the same elements throughout the figures. [0013]

【Example】

The principles and concepts of the invention are best understood by referring first to FIG. 1 of the drawings, which illustrates an example of an application in which the invention may be advantageously practiced. Microprocessor circuit 10, integrated on a single piece of silicon, has random access memory 12 connected to a data bus 14 that is shared by many other circuits in microprocessor 10. Memory 12 is shown in dashed lines and is formed in an integrated circuit beneath several conductors forming data bus 14. Data bus 14 is shown as a 32-bit bus typical of current microprocessor designs. [0014] For purposes of illustration, an arithmetic logic unit (ALU) 16 is connected to memory 12 and other data passing circuitry 18 . The memory has an input 20 and an output 22 connected to a conductor 24 of the data path 14. data bus 1
4 may be a normal bidirectional bus to which many other circuits of the microprocessor 10 are connected. [0015] The conductors of data bus 14 carry high speed logic signals that require only a few nanoseconds for rising and falling transitions. Since the electric signal has such sharp rise and fall times, it easily interferes with adjacent circuits such as the memory 12 on the lower side. The problem is complicated when forming the entire structure into a single integrated circuit because parasitic capacitance may exist between the conductors of data bus 14 and adjacent circuitry integrated on chip 10. . [0016] The portion of the memory 12 connected to 0 and 22 is shown. Specifically illustrated are complementary bit lines including bit line 26 (BL) and its complement line 28 (BL). It should be understood that memories typically include a larger number of complementary bit lines than shown. Bit lines 26,28 carry the signals written to the memory cells by write decode circuit 32, one cell being designated by the reference numeral 30. Memory cell 30 can be written to by clocking word line 34. Other cells connected to the bit line are accessed by other similar word lines. bit·
The data present on lines 26,28 are stored in the selected cell 30 of the memory. Typically, a memory includes multiple word lines 34 for accessing one of multiple cells 30 connected to bit line pairs 26,28. Write decode circuit 32 decodes the memory address and writes it to conductor 2 of data bus 14.
4 to the selected complementary bit line 26.28. At the intersection of word line 34 and bit line pair 26.28, a particular memory
Data can be written to the cell 30. [0017] Memory cell 30 is again read by activating word line 34, at which time the differential voltage is
Output on lines 26.28. The voltage difference is on the order of 5 volts and is detected by sense amplifier 36. When sense amplifier transistor 36 senses a voltage difference between bit lines 26, 28 of the order of the threshold voltage, a logic high level is output on output conductor 22. Sense amplifier 36 begins to detect a one or zero when the bit line voltage difference is a fraction of the total voltage width. Therefore, electrical noise interference must be kept to a minimum in order to provide a reliable readout of the memory. It is also important to understand that, depending on the microprocessor's shared bus structure, data bus 14 typically actively carries high level data signals while memory cell 30 is being read. It is. As a result, the signals on data bus 14 are capacitively coupled to the bit lines of memory 12 as noise interference. [0018] FIG. 2 shows data bus conductors 24 and bit lines 26.
．． The parasitic capacitance between 28 and 28 is 38.40. Parasitic capacitance 4
2.44 also data bus conductor 24 and bit line 26
．． 28 is shown in the figure. In accordance with an important feature of the present invention, complementary pairs of bit lines 26,28 are arranged such that one section of bit lines 26 is connected to data bus conductor 2.
4, one section of bit line 28 also intersects adjacent conductor 24. bit line 2
6.28 intersect at point 46 without physically touching. Because the bit lines are crossed, the undesired signal that enters the upper bit line section 26 due to parasitic capacitance 38 is generally of the same strength as the undesired signal that enters the upper section of bit line 28 due to parasitic capacitance 40. It is. [0019] Similarly, parasitic capacitance 42.44 is connected to bit line 26.44.
Connect voltages of substantially the same strength in each of the lower sections of 28. The undesirable voltage induced on the bit lines 26, 28 varies depending on the value of the parasitic capacitances 38-44, which values are not easily controlled. Crossed bit lines 26.28 induce undesired signals on both bit lines 26.28, reducing their differential effects. The crossed bit lines are connected to complementary bit lines and sense amplifiers 36 of the type shown.
Increase the noise margin of memory types that utilize [0020] FIGS. 3 and 4 are simplified illustrations of other configurations for crossing complementary bit lines to reduce the effects of unwanted signals induced therein. Two adjacent bit lines (BL, BL2) are shown in FIG. 3 as adjacent bit lines formed on a semiconductor chip. It will be appreciated that to the extent that parasitic capacitance exists between various adjacent bits, undesirable voltages may be induced therebetween. In the embodiment of FIG. 3, capacitors 52-58 represent the parasitic capacitance connected between the bit line pair BL, BL2. [0021] JP-A-3-283080 (g) The signal on the bit line conductor 50 of L is induced to the side of the crossed bit line 60, 62 of BL2. Similarly, the signal carried by bit line conductor 48 of BLl is transmitted by the crossed bit line conductor 60 of BL2.
．． 62 is also induced. The effect of having twice as many bit line crossings in BLl as compared to BL is that the noise connected between bit line pairs BL, BL2 is proportionately present in the individual pairs 48, 50, 60.62 The differential voltage is reduced to substantially zero. In other words, if a positive voltage is applied by bit line 48 to bit line 6
0 and a corresponding positive voltage is induced on bit line 62 by bit line 48, then the differential voltage induced between bit lines 60, 62 is zero. This crossed bit line configuration produces similar results on bit lines 60, 62 with respect to the voltage induced by bit line 50. Similarly,
Bit line 60.62 connects bit line 48.
The voltage induced at 50 becomes a net zero induced voltage. Therefore, for common mode noise voltages present on both bit lines of a pair, such signals will be transparent to many bit line sensing circuits. [0022] The crossing pattern of bit lines BL, BL2 is symmetrical, with crossing points or points 64, 66 being laterally adjacent. This may be advantageous in integrated circuit fabrication where it is desired to connect circuitry such as bit line biasing or pull-up circuits to side pairs of bit lines. The bias or pull-up common circuit forms polysilicon or other conductive material overlying the intersection points 64, 66, and connects the circuit to the crossed bit lines 48, which lie directly below it.
50, 60, and 62. In the embodiment of FIG. 3, the pattern designated BLl is repeated alternately for odd numbered bit lines. Similarly, the crossing pattern shown at BL2 is repeated for even numbered bit lines. [0023] The crossing pattern shown in FIG. 4 can be utilized for complementary bit line memories that do not require crossing symmetry. For example, bit lie of complementary pair BL4. As a result, the signal voltage present on bit line 68 is induced on both bit lines 72, 74 of complementary pair BL5. Similarly, the other bit line 7 of complementary pair BL4
A voltage of 6 may be induced in the sections of both bit lines 72, 74 of BL5 that intersect near intersection 72. As mentioned above, the bits with the configuration shown in FIG.
Although there are no common or symmetrical crossing points between line pairs, each bit line BL4. The differential voltage induced in BL5 eventually decreases. Also, fabrication of such a structure is simpler since there are fewer intersections than the embodiment shown in FIG. Many other crossover patterns can be devised by those skilled in the art. [0024] FIGS. 4 and 6 illustrate top and cross-sectional views of a portion of an integrated memory circuit and illustrate a method of manufacturing complementary bit line intersections. Bit line crossing member 8o may be formed of polysilicon in a traditional manner to provide a conductor for carrying signals between sections 84 and 82 of bit line BL. Bit line sections 82 , 84 may be constructed of metal insulated from polysilicon cross member 80 by a silicon dioxide insulating layer 86 . Electrical contact 88°90 is silicon dioxide 8
6 and from the metal bit line section 82 to the polysilicon cross member 80 and from the cross member 80 to the other metal bit line section 84.
Complete the electrical path to. [0025] The bit line section 91.92 forming the bit line BL is also connected to the underlying polysilicon cross member 9.
4 are formed of metal separated by an oxide insulating layer. When forming bit line crossing member 80, it is important that the bit line BL and its complementary line BL are in electrical contact. [0026] According to another technical feature of the invention, a cross-connected transistor pull-up is provided at the intersection of the crossed bit lines BL, BL. Fabrication of cross-connected transistors at bit line intersections can be conveniently performed. To this end, a source region 96 and a drain region 98 of a P-channel transistor 100 are formed on the surface of an N-type substrate 102. Metal bit line section 82 includes an extension 104 with a contact 106 to the underlying transistor source region 96. The metal supply voltage rail or bus 108 also has a contact 109 to the underlying transistor drain region 98. Source region 96 and drain region 98 are heavily doped with P 2 semiconductor impurities. other bit line B
L polysilicon cross member 94 forms the gate electrode of transistor 100. Transistor 100 is therefore a P-channel transistor whose gate is connected to bit line BL and whose source is connected to bit line BL.
and its drain is connected to the supply voltage. Therefore, the power on bit line BL is
When pulled lower than that of L, the latter bit line is pulled up to the supply voltage. [0027] A second P-channel transistor 110 is formed in substrate 102 in a manner comparable to that of transistor 100. However, the base of transistor 110 is connected to bit line BL through polysilicon cross member 80, and its source 112 is connected to bit line BL. The drain regions 98 of transistors 100 110 are common and connected to supply rail 108 . Transistor 110 operates in a similar manner to transistor 100, with P-channel transistor 110 conducting when the voltage on bit line BL is lower than that on bit line BL. The bit line BL is
This brings it up to the supply voltage. Like the bit line structure, fabrication of the transistor structure of FIG. 6 is accomplished using conventional integrated circuit fabrication techniques. However, manufacturing methods can be used to form the intersection and the associated circuitry underneath. [0028] FIG. 7 is a circuit diagram illustrating the cross-connect pullup feature of the present invention that can be conveniently utilized in conjunction with the crossed bit line feature. In the circuit diagram of FIG. 7, the data input logic signal and its complement are provided to a pair of N-channel transistors 114 and 116. Inverter 118
provides the complement of the signal on logic data in to transistor 114. The write signal on input 120 is provided to the gate terminal of each transistor 114,116. A pair of cross-coupled pull-up transistors 122, 124, different from those described above, are connected between bit line segments 126, 134. Transistors 122, 124, as described in more detail below.
is the sense amplifier 1 used for the complementary bit line above.
25. N-channel transistor 13 in series with bit line segments 126, 128
0 is connected. Similarly, N-channel transistor 132 connects bit line segment 134,1
36 are connected in series. A column select input 138 is connected to the gates of each of transistors 130, 132 to select a particular column of a typical memory. N-channel transistor 140,
142 connects memory cell 144 between bit line segments 128 and 136. [0029] Word line input 146 drives the respective gates of transistors 140 and 142 to retrieve or store data in storage cell 144 during a read or write operation. The bit lines 128, 136 form an intersection 148 where the upper bit line section 128 is connected to the lower bit line section 150 and the other lower bit line section 136 is connected to the other upper bit line section 150. - connected to line section 152; The crossed complementary bit lines are tangibly formed such that the voltage induced therein has a component common to both bit lines of the pair. Bit line section 128 forms part of a complementary bit pair parallel to and adjacent to bit line section 136. Bit line section 128 extends adjacent bit line section 136 a desired distance until the two lines intersect at point 148. Bit line section 12
8 are on one side of sections 136, and upon crossing, these sections are laterally flipped and further extended the desired distance in parallel-adjacent relationship. Although both bit line sections are recursed to form an intersection 148, one bit line of the pair can extend directly into the path, while the other can traverse it back and forth. to form a parallel adjacency relationship. [0030] A pair of cross-connected pull-up P-channel transistors 154, 156 are connected between bit line sections 150, 152, as described above. Bit line sections 150, 152 extend through the other half of the memory section to the right of the figure. In the other half of this memory section, the memory storage element 158 includes a respective transistor 160,
162 to bit lines 152 and 150. Word line input 164 is connected to transistor 16
0,162 gates and the selected memory
Write to cell 158. [0031] As described above, P-channel pull-up transistor 1
54 and 156 operate in conjunction with the bi-node line intersection 148 to enhance the noise immunity of the memory during read and write operations. The drain terminals of each transistor 154, 156 are connected together to the supply voltage cc, and their respective source terminals are connected to bit lines 152, 150. The gate terminal of transistor 154 coupled to bit line 152 is connected to bit line segment 15.
Connected to 0. The gate of transistor 156 is similarly connected to the other bit line segment 152. Transistors 154 and 156 are P-channel transistors.
transistors, which are rendered conductive when their respective gates are driven to a voltage lower than that present on the bit line connected to their respective source terminals. As a result, when a lower voltage on line 150 appears on bit line segment 152,
The transistor 156 becomes conductive and the supply voltage ■cc
is connected to bit line segment 150. Similarly, a lower voltage on line 152
When appearing on line segment 150, transistor 154 is conductive and pulls supply voltage vcc from bit to bit.
Connect to line segment 152. In this way, pull-up transistor 154,1
56 facilitates reliable determination by sense amplifier 125 of the logic state of a memory read by pulling one bit line up to the supply voltage, while the memory cell pulls the other bit line towards a logic zero level. pull to. [0032] Cross-connected pull-up transistors 154, 156
With , the positive feedback generated between bit lines 150, 152 increases the noise immunity of the memory during reads and writes. The storage element of memory cell 158 typically includes a pair of cross-connected transistors forming a flip-flop. Before performing a storage operation for a particular memory cell, the associated bit line is precharged by transistors 166, 168. A signal is applied to the PC line of the precharge transistor 166°168, turning it on momentarily to vc
c supply voltage to bit lines 150,152. During a read operation, word line 164 is clocked to cause transistors 160 and 162 to conduct. Depending on whether a 1 or an O is stored in memory cell 158, a voltage somewhat less than Vcc is connected to one of bit line segments 150 or 152. For example, in a memory with a supply voltage (Vcc) of 5 volts, if differential sense amplifier 125 initially senses approximately 5.00 volts on bit line segment 152, then a lower voltage is detected on bit line segment 152. If detected on 150, then a zero, for example, is assumed to have been stored in memory cell 158. The voltage may be set to 1 if 1 is previously applied to memory cell 1.
The opposite would be true if the 58th year was full of words. [0033] In the above example, bit line segment) 150,1
The differential amplifier begins to provide a reliable output when the voltage difference between 52 and 52 is on the order of the limiting voltage of the transistor (FET). As mentioned above, cross-coupled pull-up transistors 154, 156 are provided to help provide reliable sense amplifier operation for differentiating memory cell read voltages corresponding to 1 or O bits. For example, if bit line 152 is at a one transistor limit voltage below vcc, for example 4.00 volts, transistor 156 is rendered conductive, causing bit line segment 150 to be pulled up to 5 volts. Guarantee. Similarly, if a cell read forces bit line segment 150 to a critical voltage below vcc, transistor 154 conducts and raises the other bit line 152 to Vcc. This feature protects the memory cell 13 by ensuring that electrical noise appearing on bit lines that are not brought to a low voltage by a cell read is muffled by an aggressive pull up to the supply voltage.
Increase the differential read voltage of 4. [0034] A similar cross-connected pull-up configuration consists of P-channel transistors 122, 124 connected across bit line segments 126° 134. Similar to transistors 154 and 156, transistors 122 and 124 provide voltage control when one bit line segment is brought to a lower positive voltage.
The segments are cross-connected to bring them to cc voltage. This is the situation when one memory cell on a bit line is selected and read. A sense amplifier function is also realized in this way. Other sense amplifiers of the more sensitive or differential type can be used with the present invention. [0035] The active pull-ups of bit line sections 126, 134 are connected to column select transistors 130,
This is important because these sections are isolated from the pull-up of bit line sections 150, 152 when 132 is turned off. Therefore, without the pull-up by transistors 122, 124, bit line sections 126, 134, 128, 136
The noise immunity during this period is lost to some extent. Cross-coupled pull-ups by P-channel transistors 122 and 124 also provide a full logic low or logic high voltage to the data output through inverter 127. Inverter 127, along with transistors 122, 124, provides sense amplifier functionality that can drive other circuits at full logic levels. [0036] According to another feature of the invention, column select transistors 130, 132 are configured as N-channel devices to improve read reliability of signal voltages on bit lines 128, 136. The transistors 130 and 132 are
Formed as an N-channel device, it accepts small signal voltage changes as long as the voltage is within the transistor limit voltage range of the level on column select line 138.
Do not propagate line segments 128 to 136. For example, if the limit voltage of transistor 122 is about 1 volt and a clock signal of about 5 volts is applied to column select line 11 open +3--S, jU25U (1ts) 138, transistor 130 12
It will not conduct until the voltage on 8 reaches about 4 volts. Therefore, in this example, there is approximately 1 volt margin for noise to appear on bit line 128 without transistor 130 conducting. [0037] When transistors 114 and 116 are turned off and word line 146 and column select line 138 are clocked, the contents of memory cell 144 are read and placed on complementary bit lines 128 and 136. Output. The read voltage on that bit line is returned to the appropriate logic high and low levels by cross-coupled pull-up transistors 122124. As mentioned above, transistors 122 and 124 act as sense amplifiers that generate a complete digital signal from the memory cell read signal. The output of inverter 127 provides drive capability to the data output to drive the other circuit. [0038] Also, as described above, data bits and their complementary bits are connected to respective N-channel transistors 114, 11.
6 writes the data bit to the desired cell of the complementary bit line. Although N-channel transistors are inherently excellent switching transistors, they are not designed to provide rapid drain recovery at the upper end of the supply voltage. However, P-channel devices provide superior fast recovery to the supply voltage rail, thereby compensating for the shortcomings of N-channel devices. Therefore, P-channel transistors 122, 124
operates in conjunction with N-channel transistors 114, 116 to provide a beneficial combination for fast switching and perfect pull-up to the supply voltage. Therefore, during a write operation, one of bit lines 126 or 136 is P
It is ensured that one of the channel transistors 122 or 124 is quickly brought to the supply voltage cc. The foregoing is a P-channel pull-up transistor 15
This also holds true for N-channel transistors 130, 132 operating in conjunction with 4,156 X/). [0039] A complementary bit line structure with characteristics is disclosed. For example, crossed bit line structures have been disclosed that reduce the susceptibility of memory circuits to interference from unwanted electrical signals. A cross-coupled pull-up circuit is also disclosed that operates in conjunction with the crossed bit lines to provide positive feedback so that differential signals on the bit lines remain clear. This can improve the operation of the sense amplifier. The use of N-channel column select transistors placed in series with each bit line of a complementary pair is also disclosed to improve the noise margin of the memory circuit. A cross-coupled pull-up circuit consisting of P-channel transistors is also employed to provide a complete logic level signal to the memory cell during a write operation or to the data output inverter during a read operation. [0040] Although the invention has been disclosed above in connection with MO3 type memories, the principles and concepts of the invention are equally advantageously applicable to bipolar type complementary bit line memories. For example, the N-channel and P-channel devices described above can be interchanged if the bit line is pulled low instead of first being precharged high. It should be understood that many other changes in detail may be made as engineering choices without departing from the scope of the invention as set forth in the claims. [0041] In connection with the above description, the following items are disclosed. [0042] (1) The semiconductor memory according to claim 1, wherein the intersection has a horizontal component perpendicular to the bit line. [0043] (2) The semiconductor memory according to item (1) above, wherein the pair of 1-bit lines includes a plurality of the lateral components. [0044] (3) The semiconductor memory according to item (2) above, wherein the other bit line of the pair includes a plurality of lateral components. [0045] (4) The semiconductor memory according to item (3) above, wherein the horizontal component of the other bit line is adjacent to the horizontal side of each horizontal component of the one bit line. . [0046] (5) An output is connected to one bit line of the pair, an input is connected to the other bit line of the pair, and when the other bit line is brought to a second voltage, the first
5. A semiconductor memory as claimed in claim 1, further comprising pull-up means for pulling the bit line to a first voltage. [0047] (6) An input is connected to the one bit line and an output is connected to the other bit line, and when the one bit line is set to a second voltage, the other bit line is set to the first voltage. The semiconductor memory according to item (5) above, further comprising cross-connected pull-up means for pulling a voltage. [0048] (7) Clause (6) above, wherein said cross-connected pull-up means comprises a pair of P-channel transistors commonly connected to terminals connected to said first voltage. The semiconductor memory described. [0049] (8) A bit line structure for use in semiconductor memory having a plurality of storage cells forming regularly arranged columns, each cell having a first port on a first side thereof. and a second port on a second side thereof, said first and second ports being for communicating data signals with respective storage cells; [0050] of said plurality of cells; a first bit line connected to the first port of a portion of the cells and connected to the second port of the remaining cells of the plurality of cells; [0051] the first bit line of the plurality of cells; a portion of which is connected to the second port, and the remaining cells of the plurality of cells are connected to the second port;
A bit line structure connected to a port, wherein the first and second bit lines intersect at a point to reduce differential levels of unwanted noise signals. [0052] (9) The bit line structure of paragraph (8), wherein the portion of memory cells is approximately half of the regular column of memory cells. [0053] (10) The bit line structure according to item (9) above, wherein the cells in the part are adjacent to each other. [0054] (11) The above-mentioned (9th) cell characterized in that the part of the cells is every other cell in the regular column.
) Bit line structure described in section 2. [0055] (12) a first transistor having a conduction channel connected between a voltage source and the first bit line and having an input connected to the second bit line; a second transistor having a conduction channel connected between the second bit line and the first bit line, the second transistor having an input connected to the first bit line. The bit line structure described in paragraph (9). [0056] (13) The first and second transistors are P-channel transistors.
The bit line structure according to item [0057] (12) above, characterized in that it is composed of a transistor. [0058] (14) An apparatus for reducing noise interference in a semiconductor memory, the apparatus comprising: a first set of regularly arranged storage cells each having a first and a second input/output port; a second set of regularly arranged storage cells having a second input/output port; [0059] a first bit line and a second bit line intersecting at a crossing point electrically isolated from each other; and the first
a bit line is connected to a first input/output port of the first set of storage cells and a second input/output port of the second set of storage cells;
the second bit line is connected to a second power/output port of the first set of storage cells and to the first power/output port of the second set of storage cells; A first P-channel transistor having a conduction channel connected between a voltage source and the first bit line, and an input connected to the second bit line; a second P-channel transistor having a conduction channel connected between the bit line and an input connected to the first bit line. [0061] (15) further comprising first and second N-channel transistors, each of which is connected in series with the first and second bit lines, respectively, the N-channel transistor forming a column select function; The memory device according to item (14) above. [0062] (16) further comprising third and fourth N-channel transistors, each of which is connected in series with the first and second bit lines, respectively;
16. The memory device according to item (15), wherein an N-channel transistor connects data to the first and second sets of storage cells during a write operation of the memory. [0063] (17) connected between the first and second bit lines, insulated from the first memory cell and connected to the first bit line;
and a pull-up circuit isolated from the second N-channel transistor, the pull-up circuit comprising:
a P-channel transistor having a conduction channel connected between a voltage source and the first bit line and an input connected to the second bit line; 17. A memory device according to claim 16, characterized in that it comprises a second P-channel transistor having a conduction channel connected between the two P-channel transistors and an input connected to the first bit line. [0064] (18) further comprising a sense amplifier for sensing a signal read from a selected one of the storage cells, the sense amplifier distributing signals from the third and fourth P-channel transistors and the buffer inverter. The memory device according to item (17) above. [0065] (19) An active pull-up circuit for use in a semiconductor memory having complementary bit lines, the circuit being connected between the bit lines and capable of generating an opposite polarity signal in response to a signal on one bit line. a first transistor connected to the other bit line; connected between the bit lines, and connecting an opposite polarity signal to the one bit line in response to a signal on the other bit line; circuit. [0066] (20) The active transistor according to item (19) above, wherein the first and second transistors are field effect transistors having conduction channels, and each of the channels is connected to a constant voltage. pull-up circuit. [0067] (21) The active pull-up circuit according to item (20) above, wherein the transistor is a P-channel device. [0068] (22) The first transistor includes an input connected to the output of the second transistor, and the second transistor includes an input connected to the output of the first transistor. The active pull-up circuit according to item (19) above. [0069] (23) F on N channels in series with each said bit line.
ET) further comprising a transistor, the first and second
The active pull-up circuit according to item (19) above, wherein the transistor is a P-channel FET (P-channel FET) transistor. [0070] (24) further comprising second and third P-channel transistors connected to a bit line and functioning similarly to the first and second transistors, wherein the first and second transistor pairs are connected to the N-channel transistors; - The active device according to item (23) above, characterized in that one side of the transistor is connected to the bit line, and the third and fourth transistors are connected to the bit line on the opposite side. pull-up circuit. [0071] (25) The N-channel transistor is one of the memory
and further comprising an N-channel transistor operative to select the storage cells of the column and further connected in series with each said bit line to provide write operations for a plurality of cells associated with the bit line. The active pull-up circuit according to item (25) above. [0072] (26) The active pull-up circuit according to the above item (19), wherein the bit line includes a crossing section. [0073] (27) The bit line is formed in an integrated circuit, and the first and second transistors are formed in a semiconductor material below the bit line and connected perpendicularly thereto. The active pull-up circuit according to item (26) above, characterized in that the active pull-up circuit is formed. [0074] (28) A method of fabricating intersecting bit lines in a semiconductor memory using complementary bit lines, the method comprising: forming a first conductive connection on a semiconductor material; and forming a second conductive connection on the semiconductor material. forming a conductive connection member; forming an insulating layer on the first and second connection members; forming a first elongated conductive bit line of two sections on the insulating layer; forming a second elongated conductive bit line on the insulating layer, said second bit line consisting of two sections, one section of each of said first and second bit lines being adjacent; and adjoining each other section of the second bit line; [0076] connecting the first section of the first bit line to the first connecting member; connecting the section to the first connecting member;
A method comprising the steps of connecting said first section of a bit line to said second connecting member and connecting said other section of said first bit line to said second connecting member. [0077] (29) The method of item (28) above, wherein the first and second connecting members are generally parallel to each other. [0078] (30) The method of (30) above, further comprising the step of forming a circuit that resides at least partially below the intersection of the bit lines and connecting the rotation thereof to the bit lines.
28) The method described in section 28). [0079] (31)) A first region defining a source region of the transistor.
forming a semiconductor region under the insulating layer; connecting the source region to the first bit through the insulating layer;
a second semiconductor region remote from the source region is formed under the insulating layer, the second region having a drain region to which a voltage source can be supplied; forming a portion of the second connection member between the source region and the drain region, the portion defining a gate conductor of the transistor; 30) The method described in section 30). [00801 (32) A third semiconductor region separated from the second region is formed under the insulating layer, the third region defining a source region of the second transistor; connecting to the first section of the second bit line through the insulating layer; further comprising forming a portion of the first connecting member between the source region and the drain region of the second transistor; 32. The method according to item (31), wherein the portion of the first connecting member defines a gate conductor of the second transistor. [0081] (33) The method according to item [0082] (31) above, wherein the transistor is made as a P-channel transistor. [0083] (34) The above (3) characterized in that the second transistor is made as a P-channel transistor.
2) Method described in section 2). [0084] (35) forming a conductor on the insulating layer extending transversely to the first and second bit lines between the one section and the other section; The above-mentioned No. (31) further comprising:
) Method described in section. [0085] (36) The method according to item (35), further comprising the step of connecting the conductor to the drain region and supplying a voltage to the region. [0086] (37) A method of improving noise insensitivity of a semiconductor memory having complementary bit lines, wherein noise induced in the bit lines is common to both lines of the complementary bit pair. [0087] (38) A method characterized in that the points of intersection of one bit line pair are arranged adjacently so that the net effect of the voltage induced between the bit line pair is reduced. Item (37) above, further comprising the step of arranging the bit lines at intersections of the bit line pairs.
The method described in section. [0088] (39) The method of item (37), further comprising the step of forming the crossed bit lines when the bit lines are adjacent to other signal transmission conductors. [0089] (40) The method according to the above item (39), wherein the bit line is formed under the other signal transmission conductor.

[Brief explanation of drawings]

1 shows a microprocessor in which the invention can be advantageously applied; FIG.

FIG. 2 is a schematic diagram of a representative memory structure showing the crossing of complementary bit line pairs.

FIG. 3 illustrates another technique for intersecting alternating columns of complementary bit lines in different patterns.

FIG. 4 shows yet another pattern of intersecting alternating columns of complementary bit lines.

FIG. 5 illustrates a semiconductor structure effective for crossing complementary bit lines.

6 is a cross-sectional view of the semiconductor structure of FIG. 5 taken along line 6--6; FIG.

FIG. 7 is a circuit diagram of a crossed bit line incorporating cross-connected pull-up transistors.

[Explanation of symbols]

10 Microprocessor chip 14 Data bus 20.24 Conductor 26.28 Bit line 30 Memory cell 34 Word line 38.40, 42.44 Parasitic capacitance 80 Cross member 96 Source area 98 Drain area 100.110) Ransistor

【Document name】

[Figure 1] drawing

[Figure 2]

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

[Figure 7]

Claims (3)

[Claims] 1. A semiconductor memory comprising: an array of memory cells arranged in rows and columns; and first and second bit lines extending in directions parallel to each other; These bit lines are associated with memory cells in the first column for conveying data from a selected memory cell in the first column of the array in the manner of a differential signal therebetween. It is;
and third and fourth bits extending in parallel directions to each other.
lines, these bit lines for conveying data from a selected memory cell in a second column adjacent to the first column in the array in the manner of a difference signal between the two. associated with said second column of memory cells; and said first and second bit lines are
intersecting each other multiple times along said parallel directions, such that each of the first and second bit lines is one distance from said third bit line along said parallel directions. and the third and fourth bit lines similarly intersect each other multiple times along the parallel directions, thereby making the first and second bit lines A semiconductor memory characterized in that each of the bit lines is also close to the fourth bit line while maintaining a substantially equal distance therebetween. 2. At least one location where the first and second bit lines intersect is laterally adjacent to a location where the third and fourth bit lines intersect. 1
) semiconductor memory. 3. The method according to claim 1, wherein none of the locations where the first and second bit lines intersect are laterally adjacent to the locations where the third and fourth bit lines intersect. )
semiconductor memory.