JPH03282804A - Microcomputer - Google Patents

Abstract

PURPOSE:To obtain a wide application range of a microcomputer by discriminating whether reset is inputted with an oscillator stopped or oscillated and switching the state to the CPU operation state immediately after release of reset in the case of reset input with the oscillator not stopped. CONSTITUTION:A power-on flag 14 is cleared by a CPU 1 in the instruction execution state, namely, in the oscillating state of an oscillator 3. When a reset signal RST is made active in this state, the CPU 1 is initialized, and a CPU operation clock is not outputted to the CPU because a mask control signal MSK is active. The reset signal RST is made inactive, the CPU operation clock is outputted to the CPU 1 because the mask control signal MSK is made inactive, and the state is switched to the CPU operation state after release of reset. Thus, a wise application range of the microcomputer is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reset control circuit for a microcomputer, and more particularly to a control circuit for oscillation stabilization time after reset release.

[Prior Art] A single-chip microcomputer usually has a built-in oscillator, and a clock is generated by connecting an external crystal oscillator, ceramic oscillator, etc. to the oscillator. Additionally, recent microcomputers often have built-in standby functions such as stop mode that reduce power consumption. Stop mode is a mode that stops the operation of the entire microcomputer by stopping the oscillator.For microcomputers realized using complementary metal oxide film semiconductors, stopping the oscillator causes all operating clocks in the microcomputer to stop. It is possible to achieve ultra-low power consumption with only leakage current. This standby state is generally canceled by a reset input or an external interrupt manually. As a characteristic of an oscillator, it takes a specific oscillation stabilization time (for example, several msec to several tens of msec) depending on the type of connected oscillator until the output of the oscillator stabilizes from a state where the oscillator is stopped. It is necessary to secure it.

FIG. 2 is a block diagram of a conventional example of this type of microcomputer.

A crystal oscillator, etc. (not shown) is connected to the oscillator connection terminals 10 and 11.
The output f8 of the oscillator 3 is input to a counter 2 for measuring oscillation stabilization time (hereinafter abbreviated as counter 2) and an AND gate 9.

MSK is the mask control signal of the output f of the oscillator 3, A
It is input to one side of the ND gate 9. The output fcpu of the AND gate 9 is the C input to the central processing unit (hereinafter abbreviated as rcPUJ) 1 that has a built-in standby control function.
This is the reference clock for the PU operation clock. A reset signal RST is input to the CPUI via the reset input terminal 13. Similarly, reset signal RST is input to OR gates 7 and 8. From the external interrupt input terminal 12,
The external interrupt request signal INT is input to the external interrupt detection circuit 4, and its output, the interrupt request signal INTRQ, is ORed.
Input to gate 8 and CPUI. 5TOP is C
A stop control signal output from the PLII is manually input to the edge detection circuit 6. STP is a signal inputted to the oscillator 3 by the Q output of the RS flip-flop 5 to stop the oscillator 3, and is also input to the OR gate 7. The RS flip-flop 5 is set by the output of the edge detection circuit 6 and reset by the output of the OR gate 8. The output CLR of the OR gate 7 is input to the counter 2, and the counter 2 is cleared.

Next, the operation of the conventional example shown in FIG. 2 will be explained.

When the reset signal R5T is set to the active level "H" (high level) by the reset input, the CP
The UI is initialized and the stop control signal 5TOP is also cleared. When the reset signal RST is active, O
Since the output CLR of the R gate 7 is forcibly in the active state, the counter 2 is reset, and the output f of the oscillator 3 is
The mask control signal MSK is "L" (low level), and the CPU operation clock fcpu is also stopped.

On the other hand, the output STP of the RS flip-flop 5 becomes "L" when the reset signal R5T is active, so the oscillator 3
becomes an oscillating state. When the reset is released from the above-mentioned reset active state, that is, when the reset signal R3T falls from "H" to "L", the CLR which is the output of OR gate 7
h1 becomes ``h1'', the counter 2 is released from the clear state, and starts counting using the output fw of the oscillator 3 as an input clock. Counter 2 finishes counting the predetermined number of clocks, that is, finishes counting the oscillation stabilization time, and counter 2
When overflow occurs, the mask control signal MSK becomes “
When the reset signal R3T is input manually, the oscillation stabilization time is set in consideration of securing the oscillation stabilization time when the power is turned on. measurements are taken.

Next, when the CPU is in operation and an instruction is executed to set the microcomputer to stop mode in order to reduce power consumption, the stop control signal 5TOP goes to "H".
" level is output from the CPUI. The rise of this stop control signal 5TOP is detected by the edge detection circuit 6, and the flip-flop 5 is set by this output.
Its output STP becomes active. Then, oscillator 3
stops, and at the same time counter 2 is reset, the mass control signal MS becomes "L", and the CPU operation clock fe
pu stops and enters stop mode.

To cancel this stop mode, the external interrupt detection circuit 4 detects the rising or falling edge of the external interrupt signal INT and generates an interrupt request signal INTRQ. At this time, the RS flip-flop 5 is cleared, its output signal STP changes to "L", and the oscillator 3 starts oscillating. At the same time, the counter 2 is released from the reset state and the counting operation of the counter 2 is started. When the measurement of the predetermined oscillation stabilization time is completed, the counter 2 overflows and the mask control signal MSK becomes “
Then, the CPU operation clock fcpu is generated again.

[Problems to be Solved by the Invention] The conventional microcomputer reset control circuit described above always measures the oscillation stabilization time before the CPU actually starts operating after the reset is released. This method has the disadvantage that it cannot be applied to applications where a microcomputer needs to operate within a short period of time (for example, within 100 μsec).

SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer that can quickly shift to a CPU operating state after reset is released when a reset is input when the oscillator is not stopped.

[Means for Solving the Problems] The microcomputer of the present invention includes an oscillator that generates a reference clock for a CPU operation clock, and an oscillation stabilization time that counts the reference clock of the oscillator and ensures the oscillation stabilization time of the oscillator. an oscillator control circuit that stops the oscillator in response to a stop control signal output from the CPU and oscillates the oscillator in response to an external interrupt request signal or a CPU reset signal; and an oscillator control circuit that causes the oscillator to oscillate in response to an external interrupt request signal or a CPU reset signal; A counter control circuit that stores a power-on flag that stores the application of the power supply voltage to the microcomputer, and a reset signal that is inactive and the power-on flag does not store the application of the power supply voltage, or both the reset signal and the stop control signal are inactive. or when the reset signal is inactive and an overflow signal is output from the oscillation stabilization time measurement counter, the mask control signal is made inactive, and in other cases, the mask control signal is made active. It has a control signal generation circuit, and a gate circuit that outputs the reference clock to the CPU only when the mask control signal is inactive.

[Operation] The power-on flag is first cleared by the CPU in the instruction execution state, that is, in the oscillation state of the oscillator. When the reset signal becomes active in this state, the CPU is initialized and at the same time the mask control signal is active, so the CPU operation clock is not output to the CPU. When the reset signal becomes inactive, the mask control signal becomes inactive, so the CPU operating clock is output to the CPU, and the CPU can quickly shift to the CPU operating state after the reset is released.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a microcomputer according to an embodiment of the present invention. Components with the same symbols as in FIG. 2 have the same functions.

The power-on flag 14 is set to "H" by the CPU upon detecting the rise of the power supply voltage, and can also be cleared by a command (PONCL signal) from the CPU 1. Inverter 18 inverts reset signal R5T.

The RS flip-flop 15 is set by the output of the edge detection circuit 6 and reset by the overflow signal of the counter 2. The NOR gate 16 receives the output of the power-on hook 14 and the Q output of the RS flip-flop 15 as inputs. The OR gate 17 uses the overflow signal of the counter 2 and the output of the NOR gate 16 as input. AN
D gate 19 connects the output of NOR gate 17 and inverter 1.
The output of 8 is input, and the mask control signal MSK is ANDed.
output to gate 9.

Next, the operation of this embodiment will be explained.

First, consider a power-on reset as the first case. When the power supply voltage is turned on, the power-on flag 14 is set. When the power-on flag 14 is "H", the output of the NOR gate 16 is set to "L". Further, when the reset signal R3T is set to the active level "H" by a reset input at the same time as the power supply voltage is turned on or after the power supply voltage is turned on, the CPUI is initialized.

Furthermore, the output CLR of the OR gate 7 is the reset signal RS.
Since the counter 2 is forced to "H" by T, the counter 2 is reset and the mask control signal MS of the output fX of the oscillator 3 is fixed to "L", so the CPU operation clock fc
pu is also in a stopped state. On the other hand, the output STP of the flip-flop 5 becomes "L" and the oscillator 3 enters an oscillating state. When the reset is released from the above power-on reset state, that is, when the reset signal R3T falls, the output CLR of the OR gate 7 becomes "L" and the counter 2 outputs the output f of the oscillator 3.
8 as the input clock and starts counting operation. When the measurement of the oscillation stabilization time is completed and an overflow occurs and the output of the counter 2 changes to "H", the output of the OR gate 17 changes to "H", the mask control of the output f8 of the oscillator 3 is released, and the CPU operation clock A leakage Lpu is generated and the CPU
I starts working. At the same time, the RS flip-flop 15 is cleared.

Next, consider a second case in which a reset is input while the instruction is being executed, that is, the oscillator 3 is in an oscillating state. CPU1
In the instruction execution state, first, the instruction to clear the power-on flag 14 is executed. At this time, the clear signal PONCL of the power-on flag 14 becomes active, and the output of the power-on flag 14 is set to "L". Therefore, in this case, since the output of the NOR gate 16 is "H", the output of the OR gate 17 is always "H".
is set to In this state, the reset signal R3T
When the CPU 1 becomes active again, the CPU 1 is initialized and at the same time, since the output of the inverter 18 is "L" (the reset signal RST is "H"), the mask control signal MS of the output f8 of the oscillator 3 is It becomes "L" and the CPU operation clock fcpu is stopped. Reset signal R3T
changes from "H" to "L", the output of the inverter 18 changes from "L" to "L", and the mask control signal MSK changes from "L" to "L".
changes to “H” and the CPU operation clock falls again.
+ is generated.

In the third case, the stop state is reset by the signal R5T.
Consider the case of canceling by

Assume that an instruction for setting the stop mode is executed while the CPU is in an instruction execution state.

At this time, the stop control signal STOP or “L” is sent from the CPUI.
” to “H”, the rising edge of this signal 5TOP is detected by the edge detection circuit 6, and the RS flip-flops 5 and 15 are set.Then, the oscillator stop signal ST
P becomes "H", the oscillator 3 stops, and the counter 2 is reset. At the same time, the output of the NOR gate 16 is “
Eventually, the output of the OR gate 17 becomes "L" and the mask control signal MS also becomes "L", and the CPU operating clock fcpu stops. In this state, the reset signal R3T is set to "H". When the flip-flop 5 is reset, the oscillator stop signal STP becomes "L" and oscillation starts.Then, the reset signal R3T is changed from "H" to "L".
When the output of the OR gate 7 changes from "H" to "L" and the reset is released, the counter 2 starts operating. The measurement of the oscillation stabilization time is finished, and the output of counter 2 is “
When the output of the OR gate 17 becomes "L", the mask control signal MS also becomes "H".Then, the CPU
The operating clock fcpu starts operating. At the same time, the RS flip-flop 15 is cleared and the NOR gate 1
The output of OR gate 17 is set to "H", and the output of OR gate 17 is also fixed to "H".

[Effects of the Invention] As explained above, the present invention distinguishes whether the oscillator is a reset input when the oscillator is stopped or the oscillator is in an oscillating state, and the reset input is performed when the oscillator is not stopped. In the input mode, the microcomputer can be used in a wider range of applications by quickly transitioning to the CPU operating state after the reset is released.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microcomputer according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. 1.-CPU, 2.. Counter for measuring oscillation stabilization time, 3.. Oscillator, 4.. External interrupt detection circuit, 5.
...RS flip-flop, 6...edge detection circuit,
7.8...OR gate, 9-A N D gate, 10
゜11... Oscillator connection terminal, 12-... External interrupt input terminal, 13... Reset input terminal, 14... Power-on flag, 15-RS flip-flop, 16-...
・NOR gate, 17...OR gate, 18...inverter, 19-AND gate, 5TOP-stop control signal, STP-...output of RS flip-flop 5, INT-...interrupt signal, INTRQ - Interrupt signal, RST - Reset signal, output of CLR-OR gate 7, MS... mask control signal, f, - Output of oscillator 3, fc, - Output of A N D gate 9.

Claims (1)

[Scope of Claims] 1. In a microcomputer, an oscillator that generates a reference clock for a CPU operation clock; an oscillation stabilization time counter that counts the reference clock of the oscillator to ensure the oscillation stabilization time of the oscillator; , an oscillator control circuit that stops the oscillator in response to a stop control signal output from the CPU and oscillates the oscillator in response to an external interrupt request signal or a reset signal of the CPU; and a counter control circuit that clears the counter in response to the reset signal or the stop control signal. The circuit, the power-on flag that memorizes the application of the power supply voltage to the microcomputer, and whether the reset signal is inactive and the power-on flag does not store the application of the power supply voltage, or whether the reset signal and stop control signal are both inactive. Mask control that makes the mask control signal inactive in either of the cases when the reset signal is inactive and an overflow signal is output from the oscillation stabilization time measurement counter, and activates the mask control signal in other cases. A microcomputer comprising: a signal generation circuit; and a gate circuit that outputs the reference clock to a CPU only when a mask control signal is inactive.