JPH03280526A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent dust from being transferred and to contrive the improvement of the yield of lithography of a finely formed pattern and the improvement of reliability of products by a method wherein mask patterns of the same kind are respectively exposed on the same chip a plurality of times using masks on which a plurality of mask patterns of the same kind are formed. CONSTITUTION:Alignment marks (b) and (b') situated on a mask 11 are aligned to alignment marks (a) and (a') provided on a stage 13 in such a way that while the marks are seen through a microscope 20, the stage 13 is moved. Then, an alignment mark on a wafer is aligned to an alignment mark (c) situated on the mask 11 and a first time exposure is performed. Then, the wafer stage is moved by one chip in a direction X (Y) and thereafter, a second time exposure is performed. Lastly, the stage is moved by one chip in the direction X (Y) and a third time exposure is performed. By such a way as the above, mask patterns of the same kind are exposed on the same position on the wafer several times and dusts adhered on the mask are prevented from being transferred.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a pattern transfer method in a wafer process.

Prevents transfer of dust attached to the mask during exposure.

The purpose is to improve the yield of miniaturized pattern lamination lithography and the reliability of products.

1) Using a mask formed with multiple mask patterns of the same type, the pattern shape is overlapped at the same position on the wafer and each mask pattern is exposed multiple times, which eliminates the transfer of dust attached to the mask. Configure to prevent. 2)
The configuration is such that the total amount of energy of the irradiation light in the plurality of exposures is divided and exposed for each exposure so that a proper exposure is achieved in all the exposures.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of transferring a pattern during a wafer process.

In the wafer process for semiconductor integrated circuits, which are becoming increasingly finer each year, the size of dust that causes pattern defects is becoming smaller, and it is becoming increasingly difficult to prevent dust from being transferred onto masks.

Additionally, it is difficult to completely remove dust from the mask by cleaning, etc.

Therefore, the present invention can be used as a pattern transfer method that eliminates the influence of dust.

[Conventional technology]

In conventional exposure, after aligning the mask and wafer, exposure is performed without moving them between them.

Therefore, dust and the like attached to the mask are transferred to the resist film deposited on the wafer.

[Problem to be solved by the invention]

Therefore, during exposure, the transferred pattern becomes defective due to the transferred image such as dust on the mask, which lowers the manufacturing yield.

Furthermore, it is extremely difficult to completely eliminate fine dust on the mask.

An object of the present invention is to prevent transfer of dust attached to a mask during exposure.

[Means to solve the problem] What is the solution to the above problem?

1) Using a mask formed with multiple mask patterns of the same type, the process involves overlapping the pattern shapes at the same position on the wafer and exposing each mask pattern multiple times to prevent the transfer of dust attached to the mask. 2) A method for manufacturing a semiconductor device in which the total amount of energy of the irradiation light in the multiple exposures is divided and exposed for each exposure so that the total amount of energy is a proper exposure. This is achieved by

[Effect]

The present invention uses a mask in which a plurality of mask patterns of the same type are formed and exposes each mask pattern to the same chip multiple times to prevent dust transfer.

This is because the probability that dust will adhere to the same location on each mask pattern is extremely low, and even if unexposed areas due to dust remain after exposure using the first mask pattern.

In the exposure using the next mask pattern, the probability that dust will adhere to the same position is small, so this method takes advantage of the fact that the unexposed area is exposed.

If the number of such exposures is repeated, the probability of dust transfer approaches zero, but in practice, two to three times is sufficient.

At this time, the total amount of exposure energy is divided for each exposure so that proper exposure is achieved in all exposures.

FIGS. 1(a) to 1fdl are diagrams explaining the principle of the present invention.

FIG. 1 fa) is a plan view of the mask, and A, B, and C are chip patterns, and the same mask pattern is formed.

Figure 1 ('b) to (dl are mask patterns A, respectively)
It is a schematic cross-sectional view when the same chip is sequentially exposed using BC.

In the figure, 1 is an unexposed part of the resist, 2 is an exposed part of the resist, 3 is light transmitted through the mask, and 4 is dust.

5 is a light-shielding film of the mask, and 6 is a transparent substrate of the mask made of quartz.

〔Example〕

FIGS. 2(a) and 2(b) are a sectional view of an exposure apparatus and a plan view of a wafer stage section, respectively, explaining an embodiment of the present invention.

In the figure, 11 is a mask, 12 is a mirror projection exposure device, 13 is a wafer stage, 14 is an optical path, and 15 is a mirror.

In the embodiment, a mirror projection exposure apparatus on a boat is modified in the following points in order to apply the present invention.

■ Enables alignment of the mask and device.

To do this, an alignment mark is provided on the stage and the mask is aligned with it.

■ Move the wafer stage in the X and Y directions for one chip (approximately 20
mm) to be movable.

By this modification and by forming the mask used to have one more row of chip patterns in both the X and Y directions, the number of exposures can be divided into a maximum of four times.

Furthermore, by aligning the mask and the device, the mask and wafer only need to be aligned once, and throughput can be prevented from decreasing.

FIG. 3 is a perspective view showing an example of an optical path for alignment according to the embodiment.

In the figure, 11 is a mask, 13 is a stage, and Ll.

L2 is a light path exiting from two alignment lamps whose mutual spacing is variable, 16 to 19 are reflecting mirrors, and 20 is a prism.

21 is a microscope.

In addition to 9 normal alignment marks, alignment marks a, a' are placed on the stage in order to carry out the embodiment.
and alignment marks b, b' at corresponding positions on the mask.
will be established.

Next, the process order of the example will be explained using FIG. 3.

■ Align the mask and device.

Alignment mark a placed on the stage.

a' and alignment mark b on the mask.

b' while looking at the microscope 20 by moving the stage 13.

■ Align the wafer and mask.

Align the alignment mark on the wafer with the alignment mark C on the mask.

■ Perform the first exposure.

■ Move the wafer stage by 1,000 knobs in the X (Y) direction.

■ Perform the second exposure.

■ Move the wafer stage one chip in the X (Y) direction.

■ Perform the third exposure.

As described above, the same type of mask pattern can be exposed multiple times at the same position on the wafer to prevent dust attached to the mask from being transferred.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to prevent the transfer of dust attached to a mask during exposure, and it is possible to improve the yield of fine pattern lithography and the reliability of products.

[Brief explanation of drawings]

FIGS. 1(a) to 1Cd) are diagrams explaining the principle of the present invention. Figures 2 (al) and (b) are a cross-sectional view of an exposure apparatus and a plan view of a wafer stage section, explaining an embodiment of the present invention. Figure 3 is a perspective view showing an example of an optical path for alignment in the embodiment. In the figure: 1 is the unexposed part of the resist. 2 is the exposed part of the resist. 3 is the transmitted light of the mask. 4 is dust. 5 is the light-shielding film of the mask. 6 is the transparent substrate A, B, and C of the mask are the same. Mask pattern (chip pattern) 11 is a mask. 12 is a mirror projection exposure device. 13 is a wafer stage. 14 is an optical path, 15 is a mirror 16 to 19 are reflecting mirrors, 20 is a prism. 21 is a microscope. Ll, L2 are mutual Light path emitted from two alignment lamps with variable spacing. a, a' are alignment marks on the stage. b, b' are alignment marks on the mask at the corresponding positions of a, a'. Ir-;'''1 ↓ Xiongshiji Iku 11 Poor theory B Tsukizuro fζ outfit nvh (Bhi. 7 Ehasu thousand-ji 0 flat face mouth

Claims (1)

[Claims] 1) Using a mask in which a plurality of the same type of mask patterns are formed, the pattern shapes are overlapped at the same position on the wafer and each mask pattern is exposed multiple times, A method for manufacturing a semiconductor device, characterized in that transfer of attached dust is prevented. 2) The method of manufacturing a semiconductor device according to claim 1, wherein the exposure is divided for each exposure so that the total amount of energy of the irradiation light in the plurality of exposures is a proper exposure.