JPH03280427A - Semiconductor transducer and manufacture thereof - Google Patents
Semiconductor transducer and manufacture thereofInfo
- Publication number
- JPH03280427A JPH03280427A JP7897090A JP7897090A JPH03280427A JP H03280427 A JPH03280427 A JP H03280427A JP 7897090 A JP7897090 A JP 7897090A JP 7897090 A JP7897090 A JP 7897090A JP H03280427 A JPH03280427 A JP H03280427A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- substrate
- layer
- insulating layer
- crystal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000013078 crystal Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 20
- 150000002500 ions Chemical class 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000012212 insulator Substances 0.000 claims abstract 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000000866 electrolytic etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
本発明は単結晶半導体を用いてマイクロマシーンニング
により制作されるトランスデユーサ（センサおよびアク
チュエータの紛称）の高性能およびその新規な製法に間
するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is directed to high performance transducers (commonly referred to as sensors and actuators) manufactured by micromachining using single crystal semiconductors, and to novel manufacturing methods. It is something to do.
［従来技術］
種々のトランスデユーサにおいてシリコンを薄片化しダ
イアフラムを形成する場合、ダイアフラムの厚さを制御
することが重要である。従来はｐ型基板に必要な厚さの
ｎ型単結晶層をエピタキシャル法で形成し、にＯＨ溶液
を用いて裏面から電解エツチングによりｐ型部分を除去
していたが、ｎ型部分を陽極として用いる必要上、基板
にリート線を付けなければならず、これが量産上の欠点
となっていた。[Prior Art] When slicing silicon to form diaphragms in various transducers, it is important to control the thickness of the diaphragms. Conventionally, an n-type single crystal layer with the thickness required for a p-type substrate was formed by an epitaxial method, and the p-type portion was removed by electrolytic etching from the back side using an OH solution. In order to use it, it was necessary to attach a wire to the board, which was a drawback in mass production.
ピエゾ抵抗効果を用いるトランスデユーサは一般にはピ
エゾ抵抗を ｐ−ｎ接合で分離しているので高温で用い
ることはできなく、高温用として誘電分離法が用いられ
ている。従来の方法とし・で、ＳＯ５（Ｓｉｌｉｃｏｎ
Ｏｎ ５ａｐｐｈｉｒｅの略て、絶縁物であるサファ
イア基板上にシリコン単結晶ＮＭを形成したもの）を用
いていたがサファイア基板を厚さを制御し乍ら薄片化す
ることは困難であった。他の方法としてシリコン基板と
シリコン基板を貼り合わせて誘電分離する方法があるが
、貼り合わせ技術は高度であり、量産には不向きてあっ
た。Transducers using the piezoresistance effect generally separate the piezoresistors with a pn junction, so they cannot be used at high temperatures, and a dielectric isolation method is used for high temperatures. In the conventional method, SO5 (Silicon
However, it was difficult to control the thickness of the sapphire substrate and make it into thin pieces. Another method is to bond two silicon substrates together to achieve dielectric isolation, but the bonding technology is sophisticated and unsuitable for mass production.
種々のトランスデユーサで、最近、シリコン基板上に酸
化膜を形成し、その上に多結晶シリコン薄膜を成長させ
た後、酸化膜をエツチングで除去して、シリコン基板か
ら部分的あるいは完全に分離した多結晶薄膜を構造材料
として用い、センサの片持ちはり、両持ちはり、ブリッ
ジ、ダイアフラムとして使われたり、アクチュエータの
ロータやステータとして使われている。しかし、ノリコ
ン多結晶は、単結晶シリコンに比較して機械的強度が弱
く、破壊し易かったり、繰返し応力にも特性劣化を示す
。また、基板と膜との熱膨張係数の差により、製作時に
内部応力が生し、初期ひずみが生し、基板の形状と適合
しないため、摩擦率が大きかったり、温度変化により摩
擦率が変化する欠点があった。Recently, in various transducers, an oxide film is formed on a silicon substrate, a polycrystalline silicon thin film is grown on top of the oxide film, and then the oxide film is removed by etching to partially or completely separate it from the silicon substrate. Polycrystalline thin films are used as structural materials for cantilever beams, double-sided beams, bridges, and diaphragms in sensors, as well as rotors and stators for actuators. However, Noricon polycrystal has weaker mechanical strength than single-crystal silicon, is easily broken, and exhibits characteristic deterioration under repeated stress. In addition, due to the difference in thermal expansion coefficient between the substrate and the film, internal stress occurs during manufacturing, initial strain occurs, and it does not match the shape of the substrate, resulting in a high friction coefficient or a change in friction coefficient due to temperature changes. There were drawbacks.
［発明の目的および構成コ
本発明は、上記従来の欠点を除去し得る新規な構造を有
する半導体トランスデユーサおよびその製法を提供する
ものである。この目的を達成するために、原理的にはＬ
ＳＩ製造に用いられる ＳＩＭＯＸ （Ｓｅｐａｒａｔ
ｉｏｎ ｂｙ １Ｍｐｌａｎｔｅｄ ＯＸｙｇｅｎ）技
術を用いるものである。[Objective and Structure of the Invention] The present invention provides a semiconductor transducer having a novel structure capable of eliminating the above-mentioned conventional drawbacks, and a method for manufacturing the same. To achieve this purpose, in principle, L
SIMOX (Separate) used in SI manufacturing
ion by 1Mplanted OXygen) technology.
以下に本発明を実施例について図面に基づいて詳しく説
明する。The present invention will be described in detail below with reference to the drawings.
［実施例］
第１図は本発明による半導体トランスデユーサの一実施
例の製造工程を説明するための図である。[Embodiment] FIG. 1 is a diagram for explaining the manufacturing process of an embodiment of a semiconductor transducer according to the present invention.
（００１）面をもったｎ型シリコン基板１にイオン種１
２（０）をイオン注入し、埋め込まれた絶縁層３を形成
する。絶縁層３の上には基板ｌの一部であったノリコン
単結晶屡４が残存する。単結晶層４の厚みを犬とする必
要がある場合ここはエピタキシャル成長を行ない、これ
を可能にする。基板ｌおよび単結晶Ｎ４の表面に熱酸化
などにより酸化シリコンＭ５および５′を形成し１、膜
５の部分に正方形の窓６を開けた後、ＫＯＨを用いて基
板１をエツチングして空間部７を形成する。空間部７が
絶縁層３（酸化シリコン）に達すると ＫＯ）ｌのエツ
チング速度の比が概略５ｉ（１００）面： ５ｉ０２＝
１：１０００のため、絶縁層３をエッチ・ストップとし
て用い、必要な厚さにダイアプラムを形成することがで
きる。このダイアフラムをピエゾ抵抗形トランスデユー
サとして用いる場合には単結晶層４の一部にＢイオンを
注入、してｐ型の４個の抵抗を形成し、ブリッジ回路を
構成するか、１個の四端子素子を形成する。容量型トラ
ンスデユーサとして用いる場合は、絶縁層３あるいは膜
５′に金属蒸着層を形成し電極として用いる。単結晶層
４の中にＩＣ回路を形成することも可能である。Ion species 1 are placed on an n-type silicon substrate 1 with a (001) plane.
2(0) is ion-implanted to form a buried insulating layer 3. On the insulating layer 3, the Noricon single crystal layer 4, which was part of the substrate 1, remains. If it is necessary to increase the thickness of the single crystal layer 4, epitaxial growth is performed here to make this possible. Silicon oxides M5 and 5' are formed on the surfaces of the substrate 1 and the single crystal N4 by thermal oxidation, etc. 1. After opening a square window 6 in the film 5, the substrate 1 is etched using KOH to form the space. form 7. When the space 7 reaches the insulating layer 3 (silicon oxide), the etching rate ratio of KO)l is approximately 5i (100) plane: 5i02=
1:1000, the insulating layer 3 can be used as an etch stop to form a diaphragm to the required thickness. When this diaphragm is used as a piezoresistive transducer, B ions are implanted into a part of the single crystal layer 4 to form four p-type resistors to form a bridge circuit, or one A four-terminal element is formed. When used as a capacitive transducer, a metal vapor deposition layer is formed on the insulating layer 3 or film 5' and used as an electrode. It is also possible to form an IC circuit within the single crystal layer 4.
第２図は本発明による高温用ピエゾ抵抗形トランスデユ
ーサの実施例の説明である。第１図のシリコン単結晶４
を選択エツチングにより絶縁層３上に島上半導体領域８
を形成し、該島状半導体領域表面に熱酸化膜９を前記絶
縁層３と境界を作ることなく連続的に形成する。次に通
常のフォトリソグラフィと選択エツチングにより、熱酸
化膜９に穴あけを行ない、さらにこの上に電極金属１゜
を形成し、島状半導体８をピエゾ抵抗素子として完成さ
せる。島状半導体８の不純物濃度を基板ｌの不純物濃度
より高くする必要がある場合には、熱酸化膜９形成前に
不純物となるイオンを注入して、これを可能にする。そ
の後、基板１の裏面より、ＫＯＨ溶液を用いて空閏部７
を形成する。FIG. 2 is an illustration of an embodiment of a high temperature piezoresistive transducer according to the present invention. Silicon single crystal 4 in Figure 1
An island semiconductor region 8 is formed on the insulating layer 3 by selective etching.
A thermal oxide film 9 is continuously formed on the surface of the island-shaped semiconductor region without forming a boundary with the insulating layer 3. Next, a hole is made in the thermal oxide film 9 by ordinary photolithography and selective etching, and an electrode metal 1° is further formed thereon to complete the island-shaped semiconductor 8 as a piezoresistive element. If it is necessary to make the impurity concentration of the island-shaped semiconductor 8 higher than the impurity concentration of the substrate 1, this is made possible by implanting ions as impurities before forming the thermal oxide film 9. After that, from the back side of the substrate 1, use a KOH solution to fill the air gap 7.
form.
第３図は本発明によりシリコン単結晶の片持ちはりを形
成した略図である。先ず部分的に絶縁層３のある基板を
用い、該絶縁層の端部に相当する単結晶層４の表面より
フォトリソグラフィとＣＦ４のプラズマエツチングにて
単結晶層４に絶縁層３に達する穴１１をあけ、続いてＣ
Ｆ４４８４にてプラズマエツチングで絶縁層３を除去し
、片持ちはりを単結晶層４て形成した。片持ちはり下の
空間を拡げる必要のある場合は更にＣＦ、にてプラズマ
エツチングを行なう。両持ちはり、マイクロブリッジ等
も同じ製法で形成可能である。これらを共振形圧カドラ
ンスデューサ、加速度トランスデユーサ、ガス濃度トラ
ンスデユーサやマイクロスイッチにも利用できる。FIG. 3 is a schematic diagram of a silicon single crystal cantilever formed according to the present invention. First, using a substrate having a partially insulating layer 3, a hole 11 reaching the insulating layer 3 is formed in the single crystal layer 4 by photolithography and CF4 plasma etching from the surface of the single crystal layer 4 corresponding to the edge of the insulating layer. Open, then C
The insulating layer 3 was removed by plasma etching using F4484, and a cantilever beam was formed using the single crystal layer 4. If it is necessary to expand the space under the cantilever beam, plasma etching is further performed using CF. Double-sided beams, microbridges, etc. can also be formed using the same manufacturing method. These can also be used in resonant pressure quadrature transducers, acceleration transducers, gas concentration transducers, and microswitches.
第４図は本発明による半導体アクチュエータの実施例の
工程を説明するための図である。基板としては第一図の
ものを用い、不必要な部分の単結晶層４と埋込絶縁層３
をそれぞれ、ＣＦ、およびＣＦ４＋）１２のプラズマエ
ッチで除去し、その後熱酸化膜５を作成し、回転の中心
となる部分に多結晶シリコンでベアリング１２を作成し
、その後絶縁層３と熱酸化膜５を同時に犠牲層エツチン
グで除去し、単結晶層４を基板から分離してロータとし
て用いる。ステータはｌの表面に作成する。FIG. 4 is a diagram for explaining the process of an embodiment of the semiconductor actuator according to the present invention. The substrate shown in Figure 1 is used, and the unnecessary portions of the single crystal layer 4 and the buried insulating layer 3 are
are removed by plasma etching of CF and CF4+) 12 respectively, then a thermal oxide film 5 is created, a bearing 12 is created from polycrystalline silicon at the center of rotation, and then an insulating layer 3 and a thermal oxide film are removed. 5 is simultaneously removed by sacrificial layer etching, and the single crystal layer 4 is separated from the substrate and used as a rotor. The stator is made on the surface of l.
第５図は本発明によるプラナ−形半導体圧カドランスデ
ューサの実施例を説明するための図である。第１図に示
した基板の表面に酸化膜９を形成し、エツチング用Ｗ４
１３をホトレジストて形成し、該満より、埋込まれた絶
縁層３をエツチングで除去し、単結晶Ｎ４にてダイアフ
ラムを形成し、その後、該エツチング用溝を真空中で封
じる。単結晶層４の表面にはピエゾ抵抗素子１４を形成
して、圧カドランスデューサを製作する。ここでは−個
のトランスデユーサより記してないが同一工程で、縦横
に同一のトランスデユーサのアレイが形成される。FIG. 5 is a diagram for explaining an embodiment of a planar type semiconductor pressure quadrature transducer according to the present invention. An oxide film 9 is formed on the surface of the substrate shown in FIG.
13 is formed by photoresist, the buried insulating layer 3 is removed by etching, a diaphragm is formed from single crystal N4, and then the etching groove is sealed in a vacuum. A piezoresistive element 14 is formed on the surface of the single crystal layer 4 to produce a pressure quadrature transducer. Although not shown here, an array of identical transducers is formed vertically and horizontally in the same process.
第６図は本発明による振動形半導体トランスデユーサの
実施例を説明するための図である。第一図の基板を用い
振動子となる両持ちはりを作成する場所にその大きさに
相当する第２の埋込絶縁層３゛を形成し、第２の単結晶
層４′の表面に第２の埋込絶縁層の上部にそれと同一寸
法の酸化Ｍ９を形成し、その上に多結晶シリコン膜１２
をＣＶＤ法で形成し、それにエツチング用穴を設け、埋
込絶縁層３′と酸化膜９を同時にエツチングで除去し、
第２の単結晶Ｎ４“て両持ちはりを形成し、真空中で開
口部を単結晶シリコンまたは多結晶シリコンで封しる。FIG. 6 is a diagram for explaining an embodiment of a vibrating semiconductor transducer according to the present invention. Using the substrate shown in Figure 1, a second buried insulating layer 3' corresponding to the size of the beam is formed at the location where the double-sided beam serving as the vibrator is to be created, and a second buried insulating layer 3' is formed on the surface of the second single crystal layer 4'. An oxide M9 having the same dimensions as the buried insulating layer 2 is formed on top of the buried insulating layer 2, and a polycrystalline silicon film 12 is formed on it.
is formed by the CVD method, an etching hole is formed in it, and the buried insulating layer 3' and the oxide film 9 are removed by etching at the same time.
A double-sided beam is formed using the second single crystal N4'', and the opening is sealed with single crystal silicon or polycrystalline silicon in a vacuum.
その後、裏面から に０■液を用いてエツチングを行な
いダイヤフラムを形成する。Thereafter, etching is performed from the back side using a 0.5mm solution to form a diaphragm.
この場合、埋込絶ＲＮ３をエッチ・ストップとして用い
る。この埋込絶縁層３は前述した如く、ダイヤフラム厚
さの制御に補助的に用いるもので、これがなくても本質
的に変らない。In this case, buried RN3 is used as an etch stop. As described above, this buried insulating layer 3 is used auxiliary to control the diaphragm thickness, and there is essentially no change even without it.
〔発明の効果コ
以上説明したように、本発明に
よればＳ Ｉ ＭＯＸの技術を用いて、複雑な構造のト
ランスデユーサも埋込み絶縁層を犠牲層として用いたり
、エッチ・ストップとして用いることにより、容易に精
度良く製作でき、また、力を受ける部分を単結晶層て作
成てきるのて信頼性が優れたトランスデユーサを実現す
ることができる。[Effects of the Invention] As explained above, according to the present invention, by using the S I MOX technology, even a transducer with a complex structure can be made by using the buried insulating layer as a sacrificial layer or as an etch stop. It is possible to realize a transducer that can be easily manufactured with high precision, and has excellent reliability because the portion that receives force is made of a single crystal layer.
第１図は本発明の要部の製造工程を示す図、第２図、第
３図、第４図、第５図、および第６図は第１図をより具
体的に製作する工程および構造を示す。
１−ｍ−シリコン基板、２−ｍ−注入イオン、３−一一
理込まれた絶縁層、５．５゛−−−シリコン酸化膜、６
−−−異方性エツチ用窓、７−−−エツチされた部分、
８−一一島状単結晶層、９−ｍ−熱酸化膜、１０−ｍ−
電極、１１−一一犠牲層エッチング用穴、１２−ｍ−多
結晶シリコン、１３−一一犠牲層エッチング用溝、１４
−一一ビエゾ抵抗素子。Fig. 1 is a diagram showing the manufacturing process of the main part of the present invention, Fig. 2, Fig. 3, Fig. 4, Fig. 5, and Fig. 6 are diagrams showing the manufacturing process and structure of Fig. 1 in more detail. shows. 1-m-silicon substrate, 2-m-implanted ions, 3-11 insulating layer, 5.5゛---silicon oxide film, 6
--- Window for anisotropic etching, 7 --- Etched portion,
8-11 island-shaped single crystal layer, 9-m-thermal oxide film, 10-m-
Electrode, 11-11 hole for sacrificial layer etching, 12-m-polycrystalline silicon, 13-11 groove for sacrificial layer etching, 14
-11 viezoresistive element.
Claims (8)
合して絶縁物を形成する元素のイオンを注入することに
より当該基板表面から深さ方向に単結晶層、絶縁層、単
結晶層を基板全面あるいは基板の一部に形成せしめた基
板、または上記表面上に追加的に単結晶層を成長させた
基板を用いることを特徴とする半導体トランスデューサ
。(1) A single crystal layer, an insulating layer, and a single crystal layer are formed in the depth direction from the surface of the substrate by implanting ions of an element that combines with the semiconductor component to form an insulator from the surface of the single crystal semiconductor substrate. A semiconductor transducer characterized by using a substrate formed on the entire surface or a part of the substrate, or a substrate on which a single crystal layer is additionally grown on the surface.
フラムを形成する工程と当該絶縁層をエッチ・ストップ
として用いることを特徴とする特許請求の範囲第１項記
載の半導体トランスデューサの製造方法。2. The method of manufacturing a semiconductor transducer according to claim 1, comprising: (2) forming a diaphragm by etching the substrate into a thin piece from the back surface, and using the insulating layer as an etch stop.
いは前記ダイアフラムの表面または裏面に金属電極を設
けることを特徴とする特許請求の範囲第１項記載の半導
体トランスデューサ。(3) The semiconductor transducer according to claim 1, wherein the surface single crystal layer is used as an active layer, or a metal electrode is provided on the front or back surface of the diaphragm.
晶領域表面に絶縁層が前記絶縁層の面と連結して形成さ
れ、該島状領域を活性層として用い、且つ裏面をエッチ
ングにより薄片化しダイアフラムを形成することを特徴
とする特許請求の範囲第１項記載の半導体トランスデュ
ーサ。(4) the front single crystal layer is formed in the form of an island, an insulating layer is formed on the surface of the island-like single crystal region connected to the surface of the insulating layer, the island-like region is used as an active layer; 2. The semiconductor transducer according to claim 1, wherein the diaphragm is formed by etching the semiconductor transducer into a thin section.
結晶層と、裏面単結晶層を分離するか両層の間に空間を
形成し、または上記分離層に面した両単結晶層を追加的
にエッチングしたことを特徴とする特許請求の範囲第１
項記載の半導体トランスデューサ。(5) Either the insulating layer of the substrate is removed by etching to separate the front single crystal layer and the back single crystal layer, or a space is formed between the two layers, or both single crystal layers facing the separation layer are separated. Claim 1 characterized in that it is additionally etched.
Semiconductor transducer described in Section 1.
結晶層を形成し、該絶縁層および前記イオン注入で形成
された絶縁層をエッチングで除去して、表面単結晶層を
裏面単結晶層および最上面の多結晶層から分離するか、
表面単結晶層の上下、あるいは周囲の一部に空間を形成
し、または上記空間を追加的にエッチングしたことを特
徴とする半導体トランスデューサの製法。(6) Forming an insulating layer on the surface of the substrate, forming a polycrystalline layer on the insulating layer, and removing the insulating layer and the insulating layer formed by the ion implantation by etching to form a surface single crystal layer. separated from the back monocrystalline layer and the top polycrystalline layer, or
A method for manufacturing a semiconductor transducer, characterized in that a space is formed above and below a surface single crystal layer, or in a part of the periphery, or the space is additionally etched.
の半導体トランスデューサにおいて、空間部形成に用い
たエッチング用開口部を真空状態で封じて前記空間部を
真空に保持したことを特徴とする半導体トランスデュー
サ。(7) In the semiconductor transducer according to claim 1, 5, or 6, the etching opening used for forming the space is sealed in a vacuum state to maintain the space in a vacuum. Characteristic semiconductor transducer.
当該半導体成分と化合して絶縁物を形成する原素のイオ
ンを注入することにより当該基板表面から深さ方向に単
結晶層、絶縁層、上記単結晶層、上記絶縁層、上記単結
晶層を基板全面あるいは基板の一部に形成せしめた基板
、または上記表面上に追加的に単結晶を成長させた基板
を用い、両絶縁層をエッチングで除去して三つの単結晶
層を分離したことを特徴とする半導体トランスデューサ
。(8) A single crystal layer is formed in the depth direction from the surface of the substrate by further implanting from the surface into the substrate according to claim 1, ions of an element that combines with the semiconductor component to form an insulator. Using an insulating layer, the above-mentioned single crystal layer, the above-mentioned insulating layer, a substrate on which the above-mentioned single-crystal layer is formed on the entire surface or a part of the substrate, or a substrate on which a single crystal is additionally grown on the above-mentioned surface, both insulating layers can be formed. A semiconductor transducer characterized by separating three single crystal layers by removing the layers by etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7897090A JPH03280427A (en) | 1990-03-29 | 1990-03-29 | Semiconductor transducer and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7897090A JPH03280427A (en) | 1990-03-29 | 1990-03-29 | Semiconductor transducer and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03280427A true JPH03280427A (en) | 1991-12-11 |
Family
ID=13676759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7897090A Pending JPH03280427A (en) | 1990-03-29 | 1990-03-29 | Semiconductor transducer and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03280427A (en) |
-
1990
- 1990-03-29 JP JP7897090A patent/JPH03280427A/en active Pending
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