JPH03280090A - Gradation display circuit for display device - Google Patents

Gradation display circuit for display device

Info

Publication number
JPH03280090A
JPH03280090A JP2082001A JP8200190A JPH03280090A JP H03280090 A JPH03280090 A JP H03280090A JP 2082001 A JP2082001 A JP 2082001A JP 8200190 A JP8200190 A JP 8200190A JP H03280090 A JPH03280090 A JP H03280090A
Authority
JP
Japan
Prior art keywords
circuit
signal
thinned
inputted
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2082001A
Other languages
Japanese (ja)
Inventor
Kenichi Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2082001A priority Critical patent/JPH03280090A/en
Publication of JPH03280090A publication Critical patent/JPH03280090A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make a proper gradational display on any panel by varying a thinning-out frequency with data in display dot units and controlling ON/OFF data in the dot units with a weighted signal.
CONSTITUTION: Data G0-G7 on a thinned-out pattern is inputted to a register circuit 21 and stored with a set signal S1. This thinned-out pattern is set in a shift register 22 with a vertical synchronizing signal Vsyc, shifted, clock by clock, with a dot clock signal DCK, and outputted to a selector circuit 24. The vertical synchronizing signal Vsyc is inputted to a ringer counter circuit 23, and an 'H' output signal is generated as one of parallel outputs and inputted to the selector circuit 24. The selector circuit 24 is a selecting circuit consisting of AND and OR circuits, so its output W1-W7 is generated a thinned-out pattern waveform which is shifted in one-dot timing, frame by frame. Consequently, the proper gradational display can be made on any panel.
COPYRIGHT: (C)1991,JPO&Japio
JP2082001A 1990-03-29 1990-03-29 Gradation display circuit for display device Pending JPH03280090A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2082001A JPH03280090A (en) 1990-03-29 1990-03-29 Gradation display circuit for display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2082001A JPH03280090A (en) 1990-03-29 1990-03-29 Gradation display circuit for display device

Publications (1)

Publication Number Publication Date
JPH03280090A true JPH03280090A (en) 1991-12-11

Family

ID=13762265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2082001A Pending JPH03280090A (en) 1990-03-29 1990-03-29 Gradation display circuit for display device

Country Status (1)

Country Link
JP (1) JPH03280090A (en)

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