JPH03280090A - Gradation display circuit for display device - Google Patents

Abstract

PURPOSE:To make a proper gradational display on any panel by varying a thinning-out frequency with data in display dot units and controlling ON/OFF data in the dot units with a weighted signal. CONSTITUTION:Data G0-G7 on a thinned-out pattern is inputted to a register circuit 21 and stored with a set signal S1. This thinned-out pattern is set in a shift register 22 with a vertical synchronizing signal Vsyc, shifted, clock by clock, with a dot clock signal DCK, and outputted to a selector circuit 24. The vertical synchronizing signal Vsyc is inputted to a ringer counter circuit 23, and an 'H' output signal is generated as one of parallel outputs and inputted to the selector circuit 24. The selector circuit 24 is a selecting circuit consisting of AND and OR circuits, so its output W1-W7 is generated a thinned-out pattern waveform which is shifted in one-dot timing, frame by frame. Consequently, the proper gradational display can be made on any panel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a gradation display circuit for a flat display device.

[Summary of the invention]

The present invention aims to provide a display circuit that can directly display gradations using a conventional flat display device using a two-gradation display method. In other words, the gradation expression is weighted by decomposing multiple bits of display data for gradation expression, and the gradation level is determined by how many times the display data is driven by a conventional drive circuit within a unit time. This shows that.

[Prior Art] FIG. 4 is a circuit configuration diagram showing a conventional two-gradation display type flat display device system. In Figure 4, 41
4 is a personal computer, 42 is an interface circuit, and 43 is a flat display device such as a liquid crystal display. Video signals such as display data Do-D2, horizontal synchronization signal Hsyc, and vertical synchronization signal Vsyc from the personal computer 41 are input to the interface circuit 42.

An interface circuit 42 converts data DAT necessary for operating the flat display device from the video signal.
A, shift clock signal CL2, latch signal CL
This is a circuit for generating interface signals such as I, frame signal FRM, and polarity inversion signal M. The flat display device 43 includes a liquid crystal display element, a display element using plasma, etc., and a drive circuit for driving the display element. The drive circuit of the flat display device f1143 only performs a display ○N10FF drive operation on input display data, and does not itself have a gradation display function. Therefore, in order to display gradations, a density gradation means using ON10FF display of dots is used. Furthermore, it is conceivable that the drive circuit has a built-in drive circuit having a pulse width modulation function, but in this case, at least 3-bit parallel display data is required per display pixel. Since it is no longer possible to transfer display data in 4 or 8 bits in parallel like in a circuit, when driving a large flat display device, it is necessary to drive a device with an extremely fast data transfer speed of 4 or 8 times. A circuit is required. Furthermore, it may be possible to use a drive circuit that drives a liquid crystal display element incorporating an active element such as a TPT, but the display data handled in this case is an analog signal rather than a digital signal. Therefore, since the configurations of the interface circuits 42 themselves are different, it is impossible to generalize the functions.

Another method for displaying gradations is to display gradations by thinning out the display data for each frame and varying the number of times the ON display is driven.

[Problems to be Solved by the Invention] As stated above, the present invention solves the problem of turning on the conventional display dot.
10 FF When using a drive circuit for F display operation, if the gradation display operation is not possible and the amount of display information is not sufficient for one gradation display, use a drive circuit dedicated to gradation display. It is necessary to use a built-in drive circuit or a dedicated interface circuit, and there is a problem with versatility. 1. Coloring can be considered as a means of increasing the amount of displayed information, but in this case, In addition to problems with the versatility of drive circuits and interface circuits, manufacturing of color filters is a cost increase factor due to three times the number of drive circuits, a decrease in yield, and difficulties in mounting technology for connecting display elements and drive circuits. A number of problems arose.

The frame thinning method is effective for non-active liquid crystal display devices, but in the case of active devices that incorporate non-linear resistance two-terminal elements, the response speed is about 1/3 faster than that of non-active devices, which causes flickering. There are problems such as - becomes noticeable and it cannot be used as a gradation display method. Furthermore, the difference in the electrical characteristics of the active
Since the optical characteristics of individual panels differ due to various conditions such as differences in manufacturing processes, it has not been possible to display appropriate gradation on all panels with the same thinning rate.

[Means for Solving the Problems] The present invention has been made to solve the above-mentioned problems. The solution is not to use the conventional gradation control method using frequency modulation using frame thinning, but to change the frequency of thinning based on data in display dot units, and use the weighted signal to control ON10 in dot units.
It controls FF data. Furthermore, the thinning rate can be arbitrarily adjusted from the outside in order to match the optical characteristics of the panel.

[Effect 1] As mentioned above, since thinning is performed in units of display dots, which is the minimum time interval, gradation can be displayed without flickering as in conventional methods, even on panels with fast response speeds such as nonlinear two-terminal active panels. The 0 decimation rate can be adjusted by external means.
It can be matched to the characteristics of the panel.

[Example] FIG. 2 is a waveform diagram illustrating one embodiment of the present invention.

FIG. 2 shows a waveform diagram in the case of 3-near thinning. D
CK is a dotted black ivy.

For example, Wl is a thinning pattern waveform diagram within the frame 1 period. Similarly, W2 to Wl are frame 2
3 shows a thinning pattern waveform diagram of frame 7 from FIG.

In the waveform diagram from Wl to Wl, a level of °°H" means the display is ON, and a level of °"L means the display is OFF.Dot numbers 1, 2, 3...21 are the dots on the display panel. As can be seen from Figure 1, within the period from frame 1 to frame 7, the thinning pattern waveform repeatedly shifts by one dot for each frame, so each dot position is displayed OFF evenly three times.
I can understand what is happening.

FIG. 1 is a circuit diagram showing an embodiment for generating the thinning pattern waveform shown in FIG. In Figure 1, 2
1 is data G of the thinning pattern.

- A register circuit for storing G7, 22 is a shift register circuit, 23 is a ring counter circuit, and 24 is a selector circuit. is input to the register circuit 21, and data of the thinning pattern is stored in response to the set signal S1. The stored thinning pattern is output to the shift register circuit 22. The thinning pattern data GO is generated by the vertical synchronization signal Vsyc.
-07 is set in the shift register circuit 22. The data of the thinning pattern set by the dot clock signal DCK is shifted every clock and is output as parallel data to the selector circuit 24. On the other hand, the vertical synchronization signal Vsyc is input to the ring counter circuit 23. , one of its parallel outputs generates an output signal of °H'' and the selector circuit 24
is input. Since the selector circuit 24 is a selection circuit composed of an AND/OR circuit, its output Wl-W
Reference numeral 7 generates the thinning pattern waveform shown in FIG. 2, in which the timing of one dot is shifted for each frame.

FIG. 3 is a circuit diagram showing an embodiment of a gradation display data generation circuit using the thinning pattern generation circuit of FIG. 2 according to the present invention. In FIG. 3, DCK is a dot clock signal. Vsyc is a vertical synchronization signal. D
o, DI, and D2 are 3-pit display data. GO
-07 is thinning pattern data. 5l-57 are set signals for setting thinning pattern data Go-G7 in each register circuit. 31 is a decoder circuit for decoding the display data Do-D2. 32 to 37 indicate the thinning ratio of the thinning pattern waveform described above, for example, l: 2.3 near, 2:5.1+3,
This is a thinning pattern waveform generation circuit set to 1:4 and 1:6. 39 is the output Bl-B of the decoder circuit 31
7 and the outputs Fl-F6 of the thinning pattern waveform generation circuits 32-37.
It is a circuit. GSD is display data that has been thinned out and modulated to display one gradation, and the dot clock signal D synchronized with the 0 display data, which explains the operation of FIG.
CK and the vertical synchronization signal Vsyc are commonly input to the thinning pattern waveform generation circuit 32 or 637. The thinning ratios of the thinning pattern waveform generating circuits are different.

Then, each outputs F1 to F6 signals. Also,
The 3-bit display data is input to the decoder circuit 31 and outputs B7 from the decode output BO. The decoder output signals B1 to B7 and the output signals Fl to F6 of the thinning pattern waveform generation circuit are respectively fed to an AND/sum circuit 3.
9 is input. Output signal of the AND/sum circuit 39 -
GSD is a gradation control signal with data thinned out, which is input to the interface circuit as display data.If the decimation rate is not optimally matched due to panel characteristics, the gradation level may not be displayed linearly. In such a case, the above-described thinning pattern data GO-G7 and set signal S1-56
can be used to incorporate individual panel characteristics.

[Effects of the Invention] As described above, according to the present invention, thinning is performed for each dot, which is the smallest time unit, and the thinning timing is shifted for each frame (such as from Wl to W7 described above). )
Since this process is constantly repeated, it is possible to uniformly thin out the entire display screen. Therefore, it has become possible to perform gradation display without visually perceiving flicker even on an active panel with a fast response speed. Therefore, it has become possible to solve the problem of having to use a dedicated drive circuit for pulse width control, and to use the conventional monochrome flat display device, color display personal computer software can be used as is. This has many benefits, such as making it possible to In addition, thinning patterns can be set arbitrarily according to the characteristics of each individual panel, improving the gradation display linearity.
It has become possible to achieve excellent gradation display.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. Second
The figure is a waveform diagram showing an example of a thinning pattern generation waveform. FIG. 3 is a circuit diagram showing one embodiment of a gradation display data generation circuit. FIG. 4 is a diagram showing the system configuration of a conventional flat display device. 21 ・ ・ ・ ・ 22 ・ ・ ・ ・ 23 ・ ・ ・ ・ 24 ・ ・ ・ 32-37 ・ 31 ・ ・ ・ 39 ・ ・ ・ ・ 4 l ・ ・ ・ ・ ・ Register circuit shift register circuit ring counter circuit selector circuit thinning Pattern waveform generation circuit decoder circuit AND -OR circuit Personal computer 2 Interface circuit 43 ・・Flat type display device or higher

Claims (1)

[Scope of Claims] 1) In a display method for displaying gradation on a flat display device using a plurality of display data, the display data for expressing gradation, a decoding means for decoding the display data, and dots. A plurality of thinning pattern generating means for generating thinning patterns in units, a thinning rate of the thinning pattern generating means can be changed by external input means, and the output of the decoding means is the output of the thinning pattern generating means. A gradation display circuit comprising a configuration for selecting. 2) The pattern generating means includes a thinning pattern storage means for storing a pattern for thinning out driving in units of dots, an input means for inputting the output of the thinning pattern storage means, and a shifting means for shifting the timing of the input thinning pattern. 2. The gradation display circuit according to claim 1, further comprising select means for switching the output of said shift means at least every frame.