JPH0327911B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is an image display device that displays an image using a line raster consisting of a plurality of horizontal lines sequentially scanned in opposite directions.
It includes a video signal processing circuit that generates or transmits video information of one line in one direction and video information of the next line in the opposite direction, and a line deflection circuit that generates a line deflection current through a line deflection coil. , said video signal processing circuit has a readout memory and a clock oscillator for generating a clock signal for reading out video information from said readout memory, said clock oscillator having a control function for determining the readout instant for line deflection. a control loop comprising a counter for counting the pulses of the clock signal and means for supplying a first signal originating from said line deflection circuit and a second signal originating from said counter to a comparison stage. The present invention relates to an image display device having the present invention.

European Patent Application No. 51092 describes line deflection of an electron beam generated within an image display tube;
That is, an image display device is described in which the deflection in the horizontal direction is symmetrical, for example sinusoidal. Compared to asymmetrical, conventional sawtooth line deflections, in which the invisible retrace period is a fraction of the scan (sweep) period, symmetrical line deflections have a number of advantages, in particular lower power consumption. This has the advantage that the voltage load on the components in the line deflection circuit is low and the high-frequency radiation is low. These advantages can be achieved, for example, when using high line frequencies, which are higher than those specified by current television standards, with very short retrace periods for sawtooth deflection, e.g. on the order of 2 to 6 microseconds. This is especially important. For different line frequencies, an explanation of the power consumption and voltage load during sawtooth line deflection is given in the magazine "IEE Transactions on Consumer Electronics", August 1983, No. CE. -Volume 29, No. 3 (“IEEE Transactions
on Consumer Electronics”, Vol.CE−29, No.3”
Nos. 334-349.

In the device disclosed in the aforementioned European patent application, the comparison stage is constructed with a sample-and-hold circuit, in which the voltage present across the deflection coil is fed as a first signal. Supplied. This voltage is measured during the generation of the signal from the counter, which occurs once per cycle, and the measured value is maintained at a substantially constant value by operation of the control loop. In this way the video information is read out instantaneously, which is fixed relative to the line deflection. The position of the pixel to be read can be set using a variable resistor. This setting means is provided in the output card line of the sample-and-hold circuit and thus adjusts the control signal. Conventional devices also include memory in which data is stored for providing additional control signals. The linearity error is corrected by the setting means, so that the pixels of the various image lines which should be located at the same horizontal position are actually displayed along a vertical straight line.

The invention is based on the recognition that the above-mentioned object can only be achieved if certain conditions are met. If the amplitude of the voltage across the line deflection coil changes, the value held constant will no longer correspond to the appropriate pixel. This means that the video information is shifted horizontally in one direction for one line and in the opposite direction for the next line. Also, using a variable resistor to set the position of a pixel causes a voltage change and therefore a shift in the video information, similar to an amplitude change. Such changes in voltage across the deflection coil can be caused by roughness and/or temperature changes and aging phenomena. Furthermore, to correct raster distortion, the amplitude of the line deflection is modulated at the field frequency, so that the voltage across the line deflection coil changes during one field. Therefore, even if a pixel is adjusted to the proper position relative to a given pair of lines, and even if the aforementioned variations and phenomena described above do not exist, the pixel may be placed above or below or below said pair of lines. The positions of both corresponding pixels are no longer appropriate in the displayed image, and the vertical straight line that should be displayed is not displayed as a vertical straight line. As a result, jagged edges appear, giving the appearance of a rope coming undone.

The object of the invention is to provide an image display device of the above-mentioned type which does not have the above-mentioned disadvantages. In the device according to the invention, control similar to that in conventional devices is made independent of amplitude changes.

For this purpose, the present invention is an image display device that displays an image using a line raster consisting of a plurality of horizontal lines sequentially scanned in opposite directions, and this image display device displays one line of video information in one direction. a video signal processing circuit for generating or transmitting the next line's video information in the opposite direction; and a line deflection circuit for generating a line deflection current through a line deflection coil; a memory and a clock oscillator for generating a clock signal for reading video information from the readout memory, the clock oscillator being in a control loop that determines the readout instant for line deflection; In the image display device, the control loop has a counter for counting the pulses of the clock signal and means for supplying a first signal originating from the line deflection circuit and a second signal originating from the counter to a comparison stage. The comparison stage is a phase comparison stage, connected to this phase comparison stage is a zero-crossing point detector which produces said first signal at the moment when the line deflection current has approximately a zero value; an analog delay element is coupled to provide a second signal, the second signal being approximately coincident with the center clock pulse of the line, and the control loop is coupled to provide a second signal of It is characterized in that it is configured to produce almost simultaneously.

According to this measure according to the invention, the position of the half of the video information of each line is adjusted to the appropriate position with respect to the zero crossing point of the line deflection current. This zero-crossing point is only slightly dependent on the aforementioned variations, changes caused by temperature changes and aging phenomena, and is independent of amplitude changes. Since the delay element is provided in the control loop between the counter and the phase comparison stage and therefore in the input lead of this phase comparison stage, the setting of this delay element causes the first
and the time difference between the second signal and thus the position of the read video information relative to the line deflection current, but does not affect the amplitude of the deflection. It is therefore possible to find a setting for the delay element that causes the pixel to have the proper horizontal position. In order to make accurate settings, it is important that the delay element be an analog element.

In one embodiment of the device according to the invention, the start instant of displaying the video information is delayed with respect to the incoming line synchronization signal by a delay time adjustable by a control signal generated by said phase comparison stage. The control loop has two adjustable delay elements.

In another implementation according to the invention, the frequency of said clock oscillator can be controlled by a control signal generated by said comparison stage, and said counter has a length corresponding to two line periods. In the example, said delay element is preferably adapted to be adjustable such that the pixel at the center of the video information of the line approximately coincides with the point on the display screen where the line deflection has a zero value. .

Also in this case, the delay element is controllable by a second control signal generated by a second phase comparison stage, which includes the zero crossing detector and the second phase comparison stage. The image display device further includes a signal generator for generating a video signal having a level transition in the center of a line that cannot be seen during display. Advantageously, the second phase comparison stage is deactivated outside the line period. With this means, it becomes possible to perform automatic setting of the delay elements to compensate for time errors that may occur in the video signal processing circuit.

The invention will be explained with reference to the drawings.

In FIG. 1, 1 indicates a line deflection coil through which a line (horizontal) deflection current i _H flows during operation. This coil 1 is arranged in series with a capacitor 2, and the series network thus formed is connected to the output terminal of a power amplifier 3. One end of a negative feedback resistor 4 is connected in series with the series networks 1 and 2, and the other end of this negative feedback resistor is grounded. The connection point between the series networks 1, 2 and the resistor 4 is connected, if desired, via a negative feedback network, to the inverting input terminal of an amplifier 3, the non-inverting input terminal of which is supplied with a control signal. . Capacitor 2 isolates amplifier 3 and coil 1 from direct current. Elements 1 and 2 further constitute a series amplitude circuit with a tuned frequency approximately equal to one-half the line (horizontal) frequency, which line frequency is coupled to the electron beam generated in the image display tube (not shown). It is thus the number of horizontal scanning lines scanned every second on the display screen of the image display tube.

Amplifier 3 transmits its control signal with a frequency equal to half the line frequency to a current, as is known.
i Convert to _H. This current i _H varies sinusoidally as a function of time at half the line frequency. The control signal is a sinusoidal voltage generated by a sinusoidal oscillator 5. This oscillator 5 is synchronized in a known manner by an incoming line synchronization pulse. The reason for this is, for example, that this oscillator forms part of a line phase control loop. Alternatively, the oscillator 5 can have a line frequency, in which case the frequency of the oscillator signal is divided by 2 by a divider circuit, and the shape of the resulting signal is shaped by a shaping circuit into the desired sinusoidal shape. Make it. The phase control loop has a phase discriminator for comparing the phase of the incoming line synchronization signal with the oscillator signal and readjusting the oscillator as a function of the phase difference thereby determined. Since these synchronization problems can be easily solved by those skilled in the art, detailed explanation thereof will be omitted. The same as described above applies to the structure of elements 5 and 3.

In the above example of series resonance, the path through which the current i _H flows has an impedance of low ohmic resistance. The amplifier 3 acts as a voltage source with a low output impedance, compensating only a relatively small amount of power, in particular the power dissipated by the current i _H in said impedance and the resistor 4, and losses in the various elements of the circuit. It is necessary to generate the electricity required for the The current i _H flows in the direction shown in Figure 1 during one line period, i.e. half of one period, i.e. from the amplifier 3 to the coil 1, and during the next line period, i.e. during the next half of said one period. It flows in the opposite direction, ie back to the amplifier 3. Negative feedback is provided by the voltage present across the resistor 4, thereby stabilizing and linearizing the operation of the circuit. In a method different from that shown in FIG. 1, the amplifier 3 can be in the form of a self-oscillating output stage, in which case the oscillator 5 can be omitted.

The coil 1 can be provided in a parallel resonant circuit. In this case, coil 1 and resistor 4 are connected to amplifier 3
A capacitor 2 is placed in series between the output terminal of the
Place. If necessary, an isolation capacitor can be provided between the amplifier 3 and the resonant circuit.
The resonant circuit has a high impedance near the tuning frequency, and the amplifier 3 acts as a current source with a high output impedance. The current i _H flows in the direction from the capacitor 2 to the coil 1 during one line period and in the opposite direction back to the capacitor 2 during the next line period. This is satisfied during steady state conditions, as is the case in FIG. In this case too, the amplifier 3 generates a relatively small amount of power, in particular a power that compensates for the power dissipated in the aforementioned high impedance and the resistor 4 and the ohmic resistance of the coil 1 and other losses in the circuit. If desired, the coil 1 can be connected to the amplifier 3 in other ways not shown, for example by means of a transformer or an autotransformer. The only condition that must be met in this case is that the tuning must be done at half the line frequency.

To correct east-west (left-right) raster distortion,
By providing a modulator 6 in the drive lead of the amplifier 3 between the oscillator 5 and the amplifier 3, the circuit described above can be used at low signal levels and thus modulate the current i _H with only a small power consumption. make it possible. The modulator 6 is supplied with a field frequency signal V that changes as necessary for correction. For example, in order to correct pink tension (pincushion) distortion, the signal V
Let be a parabolic shape. The sinusoidal control voltage at half the line frequency supplied to the amplifier 3, and thus the current i _H , has an amplitude that varies with the field frequency and whose envelope has a parabolic shape with a maximum value in the middle of the field period. becomes. The modulator 6 can also be placed in the negative feedback path between the resistor 4 and the amplifier 3.

According to the above-described means, geometric errors in the displayed image can be corrected. The other correction to be made is known as the S correction. This correction compensates for geometrical errors caused by the fact that the radius of the spherical display screen is large. In a conventional line deflection circuit in which the deflection current has a sawtooth waveform, S correction is performed to make the change in the current S-shaped as a function of time. Because of this effect, the capacitance of the DC isolation capacitor placed in series with the line deflection coil is not made infinite. The coil forms a series resonant circuit together with this S correction capacitor, and the resonant frequency is one-majority of the line frequency.
The resulting S-shape deviates only slightly from the straight-line shape. This is satisfied during the line sweep period. During the retrace period, the coil and retrace capacitor form a parallel resonant circuit having a resonant frequency many times the line frequency. During retrace, the line deflection current varies according to this cosine function of time, particularly over half the period of the cosine function. S
By selecting the capacitor, the desired S correction means and thus the horizontal linearity can be set, and the capacitance of the retrace capacitor determines the duration of the retrace period.

In the circuit shown in FIG. 1 or in the previously described variants thereof, which are not shown, it is not possible to use the simple measures described above. Also, linearity correction using a variable series inductance cannot be used. The reason is that the value of the resonant frequency is fixed,
This is because it is the same for both deflection directions. The phase of the line deflection current is also fixed. The reason for this is that the line deflection current needs to be reduced to almost zero in the middle of the line sweep period when no deflection is required.
However, the amplitude of the line deflection current can be determined to correct for linearity. In Figure 2,
The solid curve shows the change in current i _H with respect to time. During a given line period, a given line, e.g. line n, is displayed in one direction, e.g. from left to right, and during a subsequent line period, line n+1 is displayed in the opposite direction, e.g. from right to left. . Both of these two line periods constitute one period of the sinusoidal function. The dashed curve in FIG. 2 is the same as the current i _H but exhibits a change in amplitude that is larger.
Both curves have centers M and N of each line period.
Both curves reach their extreme value at the transition from one line period to the next. That is, both these curves reach their minimum values at the beginning of line n and the end of line n+1;
The maximum value is reached at the end of line n.

The radius of the spherical display screen is known for a particular image display tube. The distance between the center point of this screen and the center of deflection is also known. The center of deflection is the point on the axis of symmetry of the display tube where the electron beam is thought to originate. Since we also know the width of the screen, measured along the horizontal centerline, and the duration of the active part of the line deflection current, i.e. the time during which the point at which the electron beam impinges on the screen is visible, the velocity at this point is determined. be done. It is therefore possible to determine a change in the line deflection current that allows a geometrically correct image to be obtained. This change was confirmed to have an S-shape. FIG. 2 shows that for a sinusoidal line deflection current, the curve of FIG. 2 can find an amplitude in the active part of the current that approximates the aforementioned S-shape as closely as possible. This point can be easily achieved due to the fact that the amplifier 3 has a setting characteristic for setting the gain. Therefore, by making the settings described above so that the amplitude of the current can be adapted to the curvature of the display screen, possible linearity errors can be minimized. Alternatively, the amplitude of the oscillator 5 may be set.

The image display device has a memory for processing the video signal in a known manner, in particular for displaying the video information on a display screen from left to right in one line and from right to left in subsequent lines. . These memories can easily be used for time compression or time expansion of video signals. The reason for this is that the read clock frequency and therefore the memory read speed is set. This setting ensures that video information is read out during a period corresponding to the active part of the horizontal deflection on the image screen. Therefore, the width of the displayed image is adjusted to match the linearity setting. This adjustment is a static adjustment. Additionally, the field frequency may be modulated to correct for east-west distortion of the preset readout clock frequency. This modulation must be small because a large change in the readout clock frequency will cause a change in the brightness of the displayed information. Furthermore,
This modulation may be superimposed with a slight frequency modulation to reduce horizontal linearity errors position-dependently. These fine adjustments cannot be used in place of the amplitude settings of the modulator 6 or amplifier 3.

As is clear from the above, the display of video information starts at a determined instant during the line period and ends at another determined instant, and the period between these two instants is the period of the line deflection current. 2, the center of the video information is displayed on the screen approximately at the center of the relevant line, i.e. according to the point M where the sine wave intersects the zero axis in FIG. This point must be satisfied regardless of the amplitude of the current _iH . Furthermore, it is desirable for said instants of line n to be exactly symmetrical with respect to the straight line L with the corresponding instants of line n+1. This straight line L constitutes the transition between line n and line n+1 in FIG. In this state, it is assumed that the change in current i _H is exactly mirror-symmetric. Without this symmetry, the points on the vertical line would not be exactly above or below each other on the display screen,
This is a very serious drawback. Another condition to be met is that the lines displayed on the display screen are parallel to each other and preferably horizontal, which can be achieved in a known manner by means of a stepped vertical deflection.

Achieving the desired symmetry means achieving a high Q for the resonant circuit at the output of the amplifier 3 and/or a high accuracy with respect to its input signal. The condition of symmetry also requires that the points on the display screen at which the display of video information begins are located one above the other, such that the value of the current i _H at the corresponding instant for line n is equal to the corresponding value for line n+1. It also means that. The same thing can be said for the end point of the display. Furthermore, the value of the current i _H at the starting instant is symmetrical about the zero axis with the value of the current i _H at the ending instant. It is assumed that the amplitude change caused by the east-west correction between line n and line n+1 is negligible. This means that the position of the point on the screen where the beam impinges clearly corresponds to the value of the line deflection current at this point, which in fact means that we can measure the value of the current i _H and This can be achieved by using the measurements to start and end the reading of information from the video signal processing memory.
For this purpose, for example, the peak value of the current can be measured. Such measurements need to be performed with high precision considering the large number of pixels per line. We have confirmed that this measurement is difficult in practice. Therefore, measurements are performed using other methods.

The voltage at the connection point between the deflection coil 1 and the resistor 4 is supplied to the inverting input terminal of an amplifier 7 acting as a comparison stage, the non-inverting terminal of this amplifier being connected to the connection point of the reference voltage. Since this reference voltage corresponds to the zero crossing point of the current _iH , in principle, the value of this reference voltage is zero. However, in reality, this reference voltage is
It differs from zero due to slight tolerances caused, for example, by field deflection currents in the magnetic material core of the deflection device. Under these circumstances, a signal, for example a pulse edge, is present at the output terminal of the amplifier 7 at the zero crossing point of the current i _H. This amplifier therefore functions as a zero crossing detector. This amplifier can be of known construction, for example a Schmitt trigger circuit.
Its output signal is fed to a phase comparator stage 8. In another known method, the zero crossing signal can be generated by a small transformer placed in series with the deflection coil 1.

The circuit of FIG. 1 also has a delay element 9, which is supplied with pulses at the line frequency, thereby introducing a variable delay time T. The pulse delayed by delay element 9 is sent to clock oscillator 1.
0 to operate this oscillator. This oscillator 10 produces a signal having a shift clock frequency which is used to read out a video readout memory having at least a readout function. For the reasons mentioned above, this frequency, which can be adjusted and/or modulated, is multiples of the line frequency. Its value depends on the number of pixels displayed. The oscillator 10 may be of known construction, for example a start-stop oscillator or a phase-controlled loop. The clock signal of oscillator 10 is also supplied to counter 11. Counter 11 counts the clock pulses originating from oscillator 10 until half of the pixels of a line have been read out from the video readout memory. For this purpose, counter 11
can be a counter with a length equal to half the number of samples per line. counter 11
A pulse edge is applied to the phase comparator stage 8 at the moment when the phase comparison stage 8 reaches its final counting position. A delay element 13 is arranged between the counter 11 and the phase comparison stage 8 to compensate for delays in the video signal processing channel.

The phase comparator stage 8 has a known construction, for example in the form of a phase discriminator, and generates an error signal depending on the time difference between the signals supplied to it, which is supplied via a loop filter 12 to a delay element 9. , controls the delay caused by this delay element. As is clear from this point, elements 8 to 13
constitutes a control loop which operates in such a way that the zero crossing signal generated by the detector 7 and the count signal of the counter 11 occur approximately simultaneously, in particular at the instant corresponding to point M in FIG. The line frequency synchronization signal f _H supplied to both the oscillator 5 and the delay element 9 is shown in FIG. Point A of the sine wave
Reading of video information from memory begins at an instant corresponding to . This instant is located a time T after the leading edge of the pulse, and this time T is controlled in the manner described above. Further, the reading of video information is completed at the instant corresponding to point B of the sine wave. Since the time interval between points A and M corresponds to half the video information, the time interval between points M and B also corresponds to half the video information, so points A and B are symmetric with respect to point M; Also, since the time interval between the leading edge of the line pulse and point M is approximately equal to the corresponding time interval on line n+1, the sine wave on line n+1 will be the same as the value at point B at the instant of the start of the read operation (point C). It has approximately the same value as at point A at the final instant of the read operation (point D). This means that line n+2 (not shown)
Since this also applies to , the conclusion that a vertical straight line to be displayed on the display screw is actually displayed as a vertical straight line is correct. Between points B and C no video information is displayed. In the corresponding time interval it is necessary to extinguish the electron beam, which extinguishment can be achieved by applying a pulse to the appropriate electrode of the picture display tube, the duration of this pulse being equal to the time interval mentioned above. be equal to

It should be noted that the control described above does not depend on amplitude changes, since the zero crossing point of the deflection current does not change. According to the control described above, the delay produced by the delay element 9 also causes phase errors of all kinds, e.g. due to incorrect tuning of the sine wave due to the above-mentioned magnetic effects caused in particular by the field deflection current, or There is also the advantage of compensating for small phase errors caused by phase changes between the current i _H and the incoming line signal, or both. The counter 11 is reset each time it reaches the aforementioned final counting position.
This reset occurs because a delayed or undelayed pulse at the line frequency is applied to the reset terminal R of the counter 11.

FIG. 3 synchronizes the video information with the line deflection rather than with the incoming line sync signal, and in particular allows the delay element 9 to be omitted since the clock oscillator 10 is controlled by the control signal of the filter 12. 1 shows an embodiment of a circuit according to the invention. In FIG. 3, elements corresponding to those in FIG. 1 are given the same reference numerals as in FIG. When the control loop is in steady state, the frequency of the clock signal is locked to the line frequency. The reason for this is that the phase discriminator 8
supplied to This is because a zero crossing pulse is generated for each positive or negative zero crossing point of the line deflection current. As in the case of FIG. 1, the signal of oscillator 10 is the clock signal for the video memory, and in this case the clock signal is generated continuously. Counter 11 generates a pulse representing half of one line period of video information and the phase of this pulse is compared with the phase of the zero crossing pulse.

The current i _H is plotted as a function of time in FIG. 4a, and the resulting horizontal deflection field is shown in FIG. 4b. Due to the hysteresis of the magnetic material around which the coil 1 is wound, the deflection field becomes zero a time τ ₁ after the current i _H has reached its zero value.
A delay is introduced by the zero-crossing detector 7, so that the pulse at the output of the zero-crossing detector 7 (the fourth
The leading edge of (see figure c) occurs a time τ ₂ after the zero crossing point of the current i _H . Phase discriminator 8 has a certain offset. That is, although the output signal of this phase discriminator exhibits a zero phase between the input signals, in reality the leading edge of the pulse generated by the delay element 13 (see FIG. occurs a time τ ₃ before the leading edge of the pulse supplied by . The delay element 13 introduces a delay time τ, so the counter 1
The leading edge of the output signal of 1 (see Fig. 4e) is shown in Fig. 4d.
occurs at an instant preceding the instant at which the leading edge of the pulse occurs by a time τ. In FIG. 4, various delay times are exaggerated.

The counter 11 is a counter 11 of the sinusoidal line deflection current.
It is a synchronous m counter that counts from n-1 to 0 during a period. The output of the counter 11 is connected to a programmable read-only memory 14, to which the signal of the oscillator 10 is supplied as a clock signal. The output signal of counter 11 is memory 1
This memory 14 supplies the address for a video memory 15 in which video information is stored. The address read from memory 14 reads video information from memory 15. The video signal is applied sequentially through a digital-to-analog converter 16, which is also supplied with the clock signal of the oscillator 10, a low-pass filter 17 and a video output amplifier 18 to the appropriate electrodes of the picture display tube. FIG. 4f shows the shape of this video signal for the simple case where the image to be displayed has a black-to-white level transition in the middle of the image display screen. In the first line drawn from left to right, for example line n in FIG. 2, the signal of FIG. 4 f initially has a low level;
After that, it transitions to a higher level. During line n+1 the video signal changes in opposite directions, lines n and n
During the line blanking period between +1, the signal has a low level corresponding to black. Since the delay time of the signals in elements 14-18 is not infinitely short, the video signal occurs some time after the corresponding counter signal. In particular, the center E of the transition in the signal of FIG.
occurs at an instant a time τ ₄ after the instant at which the leading edge of the pulse of FIG. 4e occurs.

The diagrams in FIGS. 4a to 4f show the time error introduced when the delay time τ caused by the delay element 3 is set to be τ=−τ ₁ +τ ₂ −τ ₃ +τ ₄ . This means that it will be fully compensated. In this case, point E in figure 4f is equal to point E in figure 4b.
A black-white level transition also occurs in the middle of the display screen at the moment when the value of the deflecting magnetic field becomes zero, in other words at the moment when the value of the deflecting magnetic field becomes zero. Due to the fact that sinusoids are symmetrical, the same as stated above holds true for the corresponding level transition in line n+1 and thus for all lines of the image. If the delay time τ is set incorrectly, Fig. 4 f
For example, the traffic signal may be shifted to the left. This is shown in dashed lines in FIG. 4f. The incorrect settings cause the black-to-white level transition to be shifted to the left for line n, and the black-to-white level transition to be shifted to the right for line n+1. In this case, the central vertical line appears on the display screen as having jagged edges, like a rope being unraveled. The delay time τ is adjustable and is set so that this jaggedness is reduced to approximately zero.

The above is satisfied if the control loop consisting of layer 8 and elements 10-13 is in synchronization, in which case the leading edges of the input signals of phase discriminator 8 (FIGS. 4c and d) coincide with each other. . When the loop is out of sync, for example when switching on the image display, the oscillator 10 generally does not have the appropriate frequency and the leading edges generally do not coincide. In these states, a control signal is obtained which changes the frequency of the oscillator 10 until the state shown in FIG. 4 is reached and this state is maintained. In this state, the oscillator 10 has the appropriate frequency and the output signal of the counter 11 has the value m-1 at an instant preceding the zero crossing point of the deflection field by a time τ ₄ . The reading of the video information from the memory 15 ends at an instant m/4 samples later than the aforementioned instant;
The counter 11 reads the video information of the same line.
starts at an instant m/4 samples earlier than the instant when counts the value m-1.

In both FIGS. 1 and 3, the reference numeral 13 designates an analog delay element of known type, for example a delay line or a phase network introducing a delay that can be set to continuous values. It is important that the delay element 13 be an analog element that can accurately set the delay time τ and thus maximize the horizontal resolution of the displayed image. It is clear that digital delay elements, such as counters, that are set to discrete values generally cannot be set to the precise values necessary to eliminate the jaggedness described above without increasing the clock frequency very high. .

However, since the sensitivity of sinusoidal line deflection to phase errors is high, it is often the case that setting the delay time once is insufficient. Horizontal resolution may also deteriorate due to temperature effects and aging reduction. The circuit of FIG. 3 has a control circuit that automatically sets the delay time, thus eliminating the drawbacks mentioned above. For this purpose, a black-to-white level transition is created at the center of one line per field. Such a video signal is on line n
and has the same shape as the signal shown in FIG. 4f for line n+1. For this purpose, select a line immediately before or after field blanking that is not visible on the display screen. The relevant digital signals are read out from a memory 20 , for example a ROM, addressed by memory 14 and fed via a changeover switch 19 to a digital-to-analog converter 16 . This switch 1
9 under the control of a keying signal generated by a signal generator 24 supplied with a line synchronization signal f _H and a field synchronization signal f _V and occurring during the line period during which said line transition takes place. Either the digital signal or the video signal in the memory 15 is selected. The output signal of the video output amplifier 18 is provided to a gating circuit 21 which transmits the output signal of the amplifier 18 in response to a keying signal of a signal generator 24. This output signal is present during the generation of the keying signal. This gate circuit 21 is connected to one input terminal of a phase discriminator 22, and the other input terminal of this phase discriminator 22 is connected to the output terminal of the zero crossing detector 7. During drawing of said line, the phase discriminator 22 measures the time difference between the black-white level transition in the video signal at the electrodes of the image display tube and the zero crossing point of the line deflection current. The analog information obtained thereby is stored in a memory element 23, for example a capacitor, and is supplied to the delay element 13 for setting the delay time τ. For this purpose, the delay element 13 has, for example, a control input for setting the voltage-dependent capacitance. The control described above automatically compensates for possible time errors in the video signal distribution, i.e. memory 15, digital-to-analog converter 16, filter 17 and amplifier 18. These components of the video signal distribution have larger variations than the components whose time errors are not automatically compensated, namely amplifier 7 and phase discriminator 8. Also, hysteresis that is not automatically compensated has only a small variation. The compensation is achieved by a fixed setting of the delay element 13.

In the practical example of the circuit, we set the line frequency to 31.250K
Hz, twice the broadcast line frequency (European standard system), and the total loss in the line deflection coil was 8.75 W instead of 15.2 W for sawtooth deflection with the same line frequency. The peak-to-peak voltage between both ends of the coil varies from about 2500V to about
Reduced to 700V. The power distribution of the circuit could be constructed as part of an integrated circuit, unlike in the case of sawtooth deflection. Also, high frequency radiation was significantly reduced. In the embodiment shown in FIG. 3, the length of the counter 11 is
We made it equal to m=1536 with a nominal clock frequency of 24MHz.

The invention can also be used for non-sinusoidal, eg triangular, symmetrical line deflections.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a part of an image display device, for example a television receiver, according to the invention, with control of the delay introduced by a delay element; FIG. 2 shows two successive line periods; 3 is a waveform diagram showing the line deflection current in FIG. 3 as a function of time; FIG. FIG. 3 is a diagram showing waveforms occurring in the circuit portion shown in the figure. 1... Line deflection coil, 2... Capacitor,
3... Power amplifier, 4... Negative feedback resistance, 5... Sine wave oscillator, 6... Modulator, 7... Amplifier (zero crossing detector) 8... Phase comparison stage (phase discriminator),
9, 13...Delay element, 10...Clock oscillator, 11...Counter, 12...Loop filter, 14...Read-only memory, 15...Video memory, 16...Digital-to-analog converter, 1
7... Low pass filter, 18... Video output amplifier, 19... Changeover switch, 20, 23...
Memory, 21...gate circuit, 22...phase discriminator, 23...memory element, 24...signal generator.

Claims (1)

[Scope of Claims] 1. An image display device that displays an image using a line raster consisting of a plurality of horizontal lines sequentially scanned in opposite directions, which image display device displays one line of video information in one direction. It comprises a video signal processing circuit for generating or transmitting the next line of video information in the opposite direction, and a line deflection circuit for generating a line deflection current through a line deflection coil, said video signal processing circuit being a readout memory and a line deflection circuit for generating a line deflection current through a line deflection coil. , a clock oscillator for generating a clock signal for reading video information from this readout memory, and this clock oscillator is provided in a control loop that determines the readout instant for line deflection; In an image display device comprising a counter for counting pulses of a clock signal, and means for supplying a first signal generated from the line deflection circuit and a second signal generated from the counter to a comparison stage, The stage is a phase comparison stage, connected to this phase comparison stage is a zero-crossing point detector which produces said first signal at the moment when the line deflection current has approximately a zero value; An analog delay element is coupled to provide two signals, the second signal being approximately coincident with the center clock pulse of the line, and the control loop is adapted to provide the first and second signals approximately coincident with the line center clock pulse. An image display device characterized in that it is configured to simultaneously display images. 2. In the image display device according to claim 1, the start instant of displaying the video information with respect to the incoming line synchronization signal can be adjusted by the control signal generated by the phase comparison stage. An image display device characterized in that said control loop has a second adjustable delay element that delays by a delay time. 3. The image display device according to claim 2, wherein the second adjustable delay element operates a clock oscillator so that the frequency of the clock signal is multiple times the line frequency, said counter has a length equal to half the number of samples of video information in one line;
An image display device, characterized in that it is adapted to count clock pulses generated to generate a signal, said counter being adapted to be reset by line frequency pulses. 4. An image display device according to claim 1, wherein the frequency of the clock oscillator is controllable by a control signal generated by the comparator stage, and the counter is In an image display device having a length corresponding to a line period, said delay element is arranged in such a way that the pixel at the center of the video information of the line approximately coincides with the point on the display screen where the line deflection has a zero value. An image display device characterized in that it is adjustable. 5. An image display device according to claim 4, in which said delay is arranged to reduce the jagged edges that vertical lines exhibit on the screen when level transitions in a video signal along a vertical line are displayed. An image display device characterized in that the elements are adjustable. 6. In the image display device according to claim 4, the delay element can be controlled by a second control signal generated by a second phase comparison stage, and The phase comparator stage is coupled to the zero-crossing detector and to the output of the video signal processing circuit, and the image display device further detects a video signal having a level transition in the center of a line that is not visible during display. Image display device, characterized in that it has a signal generator which generates a signal, the second phase comparison stage being deactivated outside this line period. 7. The image display device according to claim 1, wherein the reference signal supplied to the zero-crossing point detector can be selected.