JPH03278777A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To improve the S/W by transferring a signal charge from a vertical transfer CCD to a horizontal transmission CCD, applying plural pulses to a multiple gate electrode and transferring the charge to an output circuit. CONSTITUTION:A multiple gate electrode 7 is provided to a side wall of a horizontal transfer CCD 4 for each stage of the horizontal transfer CCD, the gate electrodes 7 are connected in common to a clock input terminal 8 and a signal charge is subject to avalanche multiplication between each multiple gate electrode 7 and the electrode of the horizontal transfer CCD 4. Thus, even when a photodiode area of a photodetector section is reduced, the signal output is not decreased and high S/W is ensured.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a solid-state device equipped with a charge-coupled device (hereinafter abbreviated as COD) that receives a plurality of signal charges in parallel and transfers the signal charges in series. The present invention relates to an imaging device, and particularly to a CCD type solid-state imaging device having a function of internally multiplying signal charges.

[Conventional technology]

An example of a conventional CCD type solid-state imaging device is shown in FIG. 4 and will be described.

Figure 4 shows a schematic configuration of a 3 x 3 pixel interline transfer type solid-state imaging device. In the figure, 1 is a photodiode as a light receiving element; It makes up the department. Further, 2 is a control gate that controls the signal charge of the photodiode 1 of each pixel, and 3 is a vertical transfer CCD that receives the signal charge of each photodiode 1 that passes through these control gates 2 and transfers it 711 times in series. , 4 is a horizontal transfer CCD that receives signal charges from each CCD 3 in parallel and sequentially transfers the signal electrodes in series; 5 is an output circuit that outputs the signal charges at the final stage of CCD 4; 6 is an output terminal.

Here, when light for imaging is incident on the photodiodes 1 of the light receiving section, signal charges corresponding to the intensity of the light are accumulated in each photodiode 1 for a certain period of time. After this period, the control gates 2 are all opened and the signal charges in each photoresistor 1 are transferred to the vertical transfer CCD 3. Therefore, the signal charges transferred to each vertical transfer CCD 3 are sequentially transferred to the horizontal transfer CCD 4 row by row. As a result, the charges transferred to this CCD 4 are transferred to the horizontal transfer COD until the signal charges of the next row are transferred to the horizontal transfer COD.
By being transferred to the output circuit 5, the signal charge is taken out from the output terminal 6 as a video signal.

[Problem to be solved by the invention]

Since the conventional solid-state imaging device is configured as described above, it is not possible to output an output greater than the signal charge accumulated in the photodiode of the light receiving section from the output terminal. That is, as the device becomes smaller or the number of pixels increases, the size of the photodiode inevitably becomes smaller, the signal output also decreases, and the S/N ratio deteriorates.

The present invention was made with the aim of solving all of the above-mentioned problems, and is a CCD-type solid-state imaging device that improves S by internally amplifying the signal obtained from the photodiode of the light receiving section. The purpose is to obtain equipment.

[Means to solve the problem]

In the solid-state imaging device according to the present invention, a multiplication gate electrode is provided on the side wall of a horizontal transfer COD, and after signal charges are transferred from a vertical transfer CCD to a horizontal transfer CCp, a plurality of multiplication gate electrodes are provided on the multiplication gate electrode. pulse is applied, and then the signal charge of the horizontal transfer COD is transferred toward the output circuit.

[Effect]

In the present invention, a pulse applied to the multiplication gate electrode provided on the side wall of the horizontal transfer CCD generates a high electric field between this gate electrode and the electrodes constituting the horizontal transfer COD, and charges are avalanche. The signal charges are multiplied and amplified.

Here, avalanche multiplication within the CCD is J, W.

Slotboom et al. #) rsURF to IEDM87
AcE IMPACT 10NIZATION IN
Reported as 5ILICON DEVICESJ. The principle is as follows.

That is, when a high clock voltage is applied between the electrodes, the charge is multiplied by avalanche due to the high electric field formed within the short distance between the electrodes. This multiplication coefficient M is expressed by the following equation.

M=@xp(anlld) (1
) d is the distance at which the above high electric field is applied, α is the electron ionization rate, J, W, Slotboom
According to et al., the following empirical formula has been obtained for surface channel type COD.

αH==2.45x 10'Xexp(-1,92xl
O'/E) (cm-":] (2) Here, E is the electric field strength mentioned above. To obtain 4000, use formula (2) to obtain 4000. E is approximately 3 1
Approximately 0.5 m/am is required. This value corresponds to the case where a potential difference of 15 V is applied to an inter-electrode distance of 0.5 μm, and is a value that is fully achievable with a surface channel type COD. Now, α. 4000cm-”, d 0゜5
When μm, (1) the multiplication coefficient M is approximately 1.22
become. Therefore, if the multiplication operation is repeated five times, the charge will be multiplied by 1.225=2.7 times.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a solid-state imaging device according to an embodiment of the present invention, and this example shows a Fi3×3 pixel-in-pixel interline transfer imaging device. The difference in Fig. 1 from the conventional example shown in Fig. 4 is that the horizontal transfer CC
Connect the multiplication gate electrode 7 to the wall of D4 and the horizontal transfer CO
D, and by connecting the gate electrodes 7 in common to a clock input terminal 8 and inputting a clock pulse of a predetermined voltage through the input terminal 8, it is possible to connect the gate electrodes 7 horizontally to each multiplication gate electrode 7. The signal charge is multiplied by 7 balances between the electrodes of the transfer CCD 4.

Note that the same reference numerals in the figures indicate the same or corresponding parts.

FIGS. 2(a) and 2(b) respectively show the cross-sectional structure along the line A-B in FIG. 1 and the potential distribution corresponding to one position, and the hatched portion indicates the signal charge Q.

In FIG. 2, 9 is a P-type semiconductor substrate, 10 is a gate oxide film made of 5i02 formed by thermal oxidation,
11 is a channel stop region, 31 is an electrode closest to the horizontal transfer CCD among the gate electrodes forming the vertical transfer CCD 3, and 41Fi is a gate electrode forming the horizontal transfer CCD i.

Further, FIG. 3 shows a part of the clock pulses for driving the solid-state imaging device shown in FIG. 1. φT shown in FIG. 3(,) is a pulse applied to the control gate 2, and φV shown in FIG. 3(b) is a pulse applied to the gate electrode 31 of the vertical transfer CCD 3.
H is a pulse applied to the electrode 41 of the horizontal transfer CCD 4, and φM shown in (d) is a pulse applied to the multiplication gate electrode 7. In the figure, 1v represents one frame period, IH represents one horizontal scanning period, THB represents a horizontal retrace period, and THE represents an effective horizontal scanning period. In addition, Fig. 2 (b
) is shown for the period during which the pulse φM is applied in FIG. 3, and the solid line e
shows when the φM pulse is in the rHJ state, and the broken line f shows when it is in the rLJ state.

Next, the operation will be explained.

In Fig. 3, Fig. 3 (&) applied every 1v period.
When the control gate 2 is opened by the pulse .phi. shown in FIG. 2, the signal charges accumulated in each photodiode 1 of the light receiving section are transferred all at once to the vertical transfer CCD 3.

The charges transferred to the CCD 3 are then transferred to the φH and φV pulses applied during the horizontal blanking period for each IH, as shown in Figures 3(b) and 3(c), for horizontal transfer for each row. Charges are sequentially transferred under the gate electrode 41 of the CCD 4. In this state, the pulse φM (φMl to φM5) in FIG. 3(d) applied to the multiplication gate electrode 7 causes the charge to be transferred to the horizontal transfer CCD 4 as shown in the potential distribution in FIG. 2(b). It moves back and forth under the gate electrode 41 and the multiplication gate T. At this time, if the pulse φM applied to the multiplication gate electrode 7 has a sufficient amplitude to cause avalanche multiplication as described above, the charge will be avalanche multiplied by the high electric field generated at distance d in FIG. be done. As a result, the signal charge is amplified. When the pulse application of φM is completed, the clock φH (FIG. 3(C)) applied to the transfer charge of the horizontal transfer CCD 4 causes
The amplified charges are output from the output circuit 5 and can be taken out from the output terminal 6 as a video signal.

In the above embodiment, an interline/transfer type solid-state imaging device has been described, but the present invention performs charge multiplication by an electrode added to a horizontal transfer CCD.
The CD section may have other configurations. For example, it is also applicable to frame transfer type or frame interline transfer type solid-state imaging devices.

It is also applicable to a so-called linear solid-state imaging device in which photodiodes arranged one-dimensionally are connected to a horizontal transfer CCD via a control gate.

〔Effect of the invention〕

As described above, according to the solid-state imaging device of the present invention, a charge multiplication gate electrode is provided on the side wall of the horizontal transfer COD, and a clock pulse applied to the charge multiplication gate electrode is connected to the horizontal transfer CCD electrode and the multiplication gate. Since the structure is configured to generate a high electric field between the electrodes and avalanche multiply the charge, the signal output will not decrease even if the area of the photodiode in the light receiving section decreases due to miniaturization of the device or increase in the number of pixels. First, it has the effect of ensuring a high S/N ratio.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing a solid-state imaging device using a 3×3 pixel interline transfer method according to an embodiment of the present invention, and FIG. 2 (Hata) and (b) are cross-sectional structures taken along A-B in FIG. 3 is a diagram showing a part of the driving clock pulse used to explain the operation of the embodiment in FIG. 1, and FIG. 4 is a diagram showing a 3×3 pixel interline according to the conventional example. 1 is a schematic configuration diagram showing a transfer type solid-state imaging device. 1...ll11 photodiode, 2...control gate, 3...CCD for φ vertical transfer, 4...COD for horizontal transfer, 5...output circuit, 7...φ multiplication gate electrode for horizontal transfer, 41... Electrode constituting the CCD for horizontal transfer.

Claims (1)

[Claims] In a solid-state imaging device equipped with a charge-coupled device that receives a plurality of signal charges in parallel and transfers the signal charges in series, a multiplication gate electrode is provided on a side wall of the charge-coupled device,
After inputting a signal charge to the charge-coupled device, a clock pulse is applied to the gate electrode to avalanche multiply the charge between the electrodes constituting the charge-coupled device and the gate electrode. solid-state imaging device.