JPH03273725A - Parallel processing type scrambler - Google Patents

Abstract

PURPOSE:To lower the processing speed to a signal having a fast transmission speed by carrying out a scramble after converting the signal carrying out the scramble into a parallel signal. CONSTITUTION:The input data (a) is inputted to a serial/parallel conversion part 2 and divided into two parallel data (b) and (c). The weight is applied to the data (b). Both data (b) and (c) are inputted to the exclusive OR gates 2 and 3 which perform the scrambles and then sent to a parallel/serial conversion part 8 and also to tube shift registers 4 and 5 as the scramble data (d) and (e). The outputs of both registers 4 and 5 send a scramble code (g) to the data (b) and at the same time a scramble code (h) is transmitted by the output of the register 5 and the data (x). Then the part 8 applies the weight to the data (d) and converts the weighted data into the serial data (f). Thus the scramble is carried out with an input signal turned into a double parallel form. As a result, the scramble processing is attained at a 1/2 processing speed to an input signal of a fast transmission speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scrambler, and particularly to a scrambler that processes parallel data.

[Conventional technology]

Conventional scramblers employ a system in which serial signal input data is sequentially input to the scrambler, and scrambling codes are sequentially output.

FIG. 3 shows an example of a conventional scrambler having a generator polynomial of l+X+X2. This scrambler is composed of a shift register 2L 22 and exclusive OR circuits 23 and 24, and input data of the serial signal is A, the output of the shift register 21 is B1, and the output of the shift register 22 is 01 scrambled data. When set to D, FIG. 4 shows how the data changes. In addition, in Figure 4, the ■ mark is 2
Shows base addition.

In this way, in the conventional scrambler, the input data A of the serial signal is subjected to the exclusive OR operation in the exclusive OR circuits 23 and 24 using the output of the shift register 2L 22.
This becomes scrambled data D and is sent out sequentially.

[Problem to be solved by the invention]

The conventional scrambling described above performs sequential scrambling processing at the transmission speed, so the logic gate delay time cannot be ignored for signals at high transmission speeds.
The disadvantage is that scrambling cannot be performed.

An object of the present invention is to provide a parallel processing type scrambler that does not have such drawbacks.

[Means to solve the problem]

The parallel processing type scrambler of the present invention includes a serial-to-parallel converter that divides human data into n parallel parts, and n scrambling exclusive logics that input each parallel signal and a scrambling code and output scrambled data. a sum gate; m shift registers that manually input the output of the exclusive OR gate to form an m-stage scrambler, and are arranged sequentially to a signal with a lower weight than a heavier signal among the parallel signals; The output of the register or the output of the shift register and the scrambler data are arranged so as to form a scrambling generating polynomial in descending order of the weight of the parallel signals, and connected to the exclusive OR for scrambling. It has n exclusive OR gates for feedback, and a parallel-to-serial converter that serializes the n pieces of scrambled data.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In this embodiment, the generator polynomial of the scrambler is 1+X1×2, and two inputs are parallelized.

This parallel processing type scrambler includes a serial-to-parallel converter 1 that divides serial input data a into two parallel signals, each parallel signal S, c, and a scrambler code g.

An exclusive OR gate 2.3 for scrambling inputs h and outputs scrambler data de, and a two-stage scrambler inputs scramble data d and e, which has a heavy parallel signal weight. Two shift registers 4.5 are arranged sequentially for the signal C lower than the signal C, a feedback exclusive OR gate 6 to which the output of the shift register 4 and the output of the shift register 5 are manually input, and the shift register 5. It is comprised of feedback exclusive OR data 1 to 7 into which the outputs of and scramble data d are input, and a parallel-to-serial converter 8 that serializes the scramble data d and e. Note that the feedback exclusive OR gate 6.7 receives parallel signals such as
Scrambling generator polynomial 1+X+ in descending order of weight of c
X2, and scramble codes g and h are placed in the exclusive OR gates 2.3 and 2.3, respectively.
supply.

Next, the operation of this embodiment will be explained with reference to FIG. Note that FIG. 2 shows data a, b, and c of FIG. 1.

It shows how d, e, f, and g change.

Input data a is input to the serial-parallel converter 2, where it is divided into two parallel data b and C, and weighting is given to data b. Parallel data b and C are input to an exclusive OR gate 2.3 that performs scrambling, and are sent to parallel-to-serial converter 8 and shift registers 4 and 5 as scramble data de, respectively. The output of the shift register 4.5 sends out a scramble code g to the input data b side, and the output of the shift register 5 and the scramble data d send out a scramble code. The parallel-to-serial converter 8 converts the scrambled data d and e into serial data f by weighting the data d.

As described above, according to this embodiment, since the input signals are scrambled by parallelizing them into two signals, it is possible to perform the scrambling process at half the processing speed for a human input signal having a high transmission speed.

〔Effect of the invention〕

As explained above, the present invention converts a signal to be scrambled into a parallel signal and performs scrambling.
For signals with high transmission speed, 1/n of processing speed
This has the effect of making it possible to reduce the speed and perform scrambling operations.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing how data changes in the scrambler of FIG. 1, and FIG. 3 is a diagram showing the configuration of a conventional scrambler. The figure shown in FIG. 4 is a diagram showing how data changes in the scrambler of FIG. 3. ■...Serial-parallel converter 2.3, 6.7...Exclusive OR gate 4.5...
Shift register 8...Parallel-serial converter a...Input data b, c...Parallel data de...Scramble data f...Output data gl h...Scrambling code

Claims (1)

[Claims] (1) A serial-to-parallel converter that divides input data into n parallel parts; n exclusive OR gates for scrambling that input each parallel signal and a scrambling code and output scrambled data; m shift registers that input the output of the OR gate to form an m-stage scrambler, and are arranged sequentially to signals with lower weights of the parallel signals; and the output of the shift register, or the shift register. n feedback exclusive logics that input the output of the parallel signal and the scrambler data, are arranged so as to configure a scrambling generating polynomial in descending order of the weight of the parallel signals, and are connected to the scrambling exclusive OR. A parallel processing type scrambler, comprising: a sum gate; and a parallel-to-serial converter that serializes the n pieces of scrambled data.