JPH03271903A - Speed control circuit - Google Patents

Abstract

PURPOSE:To accurately work an object and to perform the high-speed processing by driving a device with a driving pulse signal where a pulse signal for driving at a fixed speed and that for driving at an acceleration/deceleration are synthesized. CONSTITUTION:A pulse train dividing circuit 6 which divides a fundamental pulse train into first and second fundamental pulse trains different in phase, an acceleration/deceleration control circuit 4 which converts the first fundamental pulse train to an acceleration/deceleration pulse train in accordance with acceleration/deceleration pattern data, and an acceleration/deceleration setting circuit 5 which converts the acceleration/deceleration pulse train to the driving pulse signal are provided. A fixed speed control circuit 7 which converts the second fundamental pulse train to the driving pulse signal for fixed speed and a pulse train synthesizing circuit 8 which synthesizes both pulse signals are provided. The signal obtained by synthesizing the fixed-speed pulse signal and the acceleration/deceleration pulse signal is used for driving. Thus, the working device is smoothly operated to accurately perform working, and the processing is performed at a high speed because the acceleration/deceleration pattern data change processing is unnecessary.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speed control circuit that generates speed command pulses for controlling the speed of interpolation calculations in a numerical control device.

[Prior art 1] A speed control circuit of a conventional numerical control device that controls the speed of a driving body such as a motor based on numerical information to drive these and automatically generate a workpiece of a predetermined shape is The configuration is as shown in Figure 3, in which 10 is a basic pulse generation circuit, 11 is a speed $1Jll
cPtJ, 12 is an acceleration/deceleration pattern data generation circuit, 13
is an acceleration/deceleration control circuit, 14 is a speed setting circuit, f
@IIK is the highest frequency basic pulse train signal, fed is the acceleration/deceleration pulse train signal, and fowl is the speed control pulse signal.

Then, the pulse train for speed control is generated by the basic pulse generating circuit 10 as a basic pulse train signal f w corresponding to the maximum speed.
ax is generated and this signal f@IIX is sent to the acceleration/deceleration control circuit 13. At this time, the acceleration/deceleration pattern data generation circuit 12 generates an acceleration/deceleration pattern based on the acceleration/deceleration pattern data stored in the memory circuit in this circuit 12 based on the instruction from the speed control CPU II. Data is selected and sent to the acceleration/deceleration control circuit 13.

Then, the acceleration/deceleration control circuit 13 inputs this acceleration/deceleration pattern data, divides the frequency of the basic pulse train manually generated from the basic pulse generation circuit IO based on the data, performs acceleration/deceleration, and converts the acceleration/deceleration pulse train signals f and d into speeds. It is sent to the setting circuit 14. In this way, the acceleration/deceleration pattern data generation circuit 12
The acceleration/deceleration pulse train signal fed sent out from the speed setting circuit 14 is inputted to the speed setting circuit 14, frequency-divided into a speed control pulse signal fout of a desired frequency, and sent as a command pulse to an interpolation calculation circuit (not shown). As a result, the driving body is driven and a workpiece having a predetermined shape is produced.

In addition, although linear acceleration/deceleration is common as an acceleration/deceleration pattern, SI
N acceleration/deceleration patterns (patterns that change in a sinusoidal manner) and more complex acceleration/deceleration patterns are selected.

As an example of speed change in one control block, as shown in FIG. 4, starting from speed "0", reaching speed f, maintaining distance f for a certain period of time, and then starting deceleration, One block ends when the speed reaches "0".

Furthermore, depending on the relationship between the front and rear speed control blocks, the speed control block may have an initial speed f, as shown in FIG. 5, or a final speed fe, as shown in FIG.

In the conventional speed control circuit, the initial speed f and the final speed f
Even if e exists, if it changes linearly, accurate speed control can be performed, but if you have a SIN acceleration/deceleration pattern or a special acceleration/deceleration pattern, some of these acceleration/deceleration patterns Since these patterns are omitted, it may not be possible to produce a workpiece according to these patterns. In other words, the ideal acceleration/deceleration patterns shown in FIGS. 7 and 8 are partially omitted by this speed control circuit and become the acceleration/deceleration patterns shown in FIGS. 9 and 10. As a result, even though the acceleration/deceleration pattern was selected to be optimized for the load and machining shape, this speed change differs from the ideal shape, resulting in errors in the machining shape. .

In addition, in order to solve speed control in which this acceleration/deceleration pattern is omitted, the acceleration/deceleration pattern data must be recreated for each speed control block in the speed control CPU 11. This means that the processing of the speed control CPtJ11 is This means an increase in load (increase in processing time), and as a result, conventionally, the maximum speed value of the basic pulse train signal f@IIX is limited.

[Problem to be solved by the invention] When speed control is performed using the above-mentioned conventional speed control circuit,
Depending on the speed control block, a part of the acceleration/deceleration pattern may be omitted, making it difficult for the processing device to operate smoothly, resulting in an error in the processed shape. In addition, in order to solve this problem, if the speed control CPU II is made to recreate the acceleration/deceleration pattern data, the load on the speed control CPU II increases, and as a result, the maximum speed value of the basic pulse train signal is limited, and the There was a problem that it could not be processed.

[Means for Solving the Problems] In order to solve such problems, the speed control circuit according to the present invention includes a basic pulse generation circuit that generates a basic pulse train of a constant frequency, and an output from this basic pulse generation circuit. A pulse train dividing circuit divides and outputs a pulse train into a first basic pulse train and a second basic pulse train having mutually different phases, and stores acceleration/deceleration pattern data for accelerating and decelerating the driving body. An acceleration/deceleration pattern data generation circuit that sequentially outputs acceleration/deceleration pattern data, a first basic pulse train and acceleration/deceleration pattern data, and converts the first basic pulse train into an acceleration/deceleration pulse train according to the acceleration/deceleration pattern data. an acceleration/deceleration control circuit that outputs
An acceleration/deceleration speed setting circuit that converts the acceleration/deceleration pulse train into a pulse signal for driving the driving body at an acceleration/deceleration speed, and a second basic pulse train that is input and converted into a pulse signal for driving the driving body at a constant speed. It is equipped with a constant speed control circuit, and a pulse train synthesis circuit that inputs and synthesizes each pulse signal from the acceleration/deceleration speed setting circuit and the constant speed control circuit and outputs a driving pulse signal for the driving body.

[Operation] The driving body is driven by a driving pulse signal that is a combination of a pulse signal for driving the driving body at a constant speed and a pulse signal for driving the driving body at an acceleration/deceleration rate.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a speed control circuit according to the present invention. In the figure, 1 is a basic pulse generation circuit that generates a pulse train signal twice the speed of the basic pulse train signal, 2 is a speed control CPU, 3 is an acceleration/deceleration pattern data generation circuit that generates acceleration/deceleration pattern data, and 4 is an input. An acceleration/deceleration control circuit controls the speed of the speed change portion by controlling the speed of the basic pulse train signal based on acceleration/deceleration pattern data, and 5 is an acceleration/deceleration control circuit that divides the signal from the acceleration/deceleration control circuit 4 into a required frequency. A speed setting circuit, 6 is a pulse train dividing circuit which inputs a pulse train of twice the highest frequency from the basic pulse generating circuit l and divides it into two highest frequency basic pulse train signals with different phases, and 7 is a pulse train dividing circuit of the highest frequency. A constant speed control circuit that inputs a pulse train to control the speed of the speed-constant section.
8 is a pulse train synthesis circuit that synthesizes the pulse trains of the speed change portion and the constant speed portion. Further, 2f, , , , are basic pulse train signals having twice the frequency of the basic pulse train signal f, □, f□, 1. f...

2 is a basic pulse train signal, fmwb, each having a different phase.
is a pulse train signal corresponding to a speed change, and f ofraet is a pulse train signal corresponding to a constant speed.

In the basic pulse generating circuit 1, as shown in FIG. 2(a), a pulse train signal 2f at twice the maximum speed is generated.
The pulse train dividing circuit 6 receives the pulse train 2f-, , and generates the pulse train 2f-, , as shown in FIG. 2 (b) and (C).
As shown in the figure, pulse trains f, each having a different phase,
,,l and f-,,2.5. One of the pulse train signals f 1 , . In this way, the speed control pulse signal r0-t in one speed control block
(151!Dynamic pulse signal) is a pulse train signal f amb for a speed change and a pulse train signal f for a constant speed. frs
et and is divided and controlled.

On the other hand, in the acceleration/deceleration pattern data generation circuit 3, based on the speed control block switching instruction from the speed control CPU 2,
From the acceleration/deceleration pattern data stored in the memory of this circuit 3, acceleration/deceleration pattern data DATA, d are sequentially selected and output according to changes in acceleration/deceleration time. and,
This selected acceleration/deceleration pattern data DATA,...
The signal is sent to the acceleration/deceleration control circuit 4.

In this way, the acceleration/deceleration control circuit 4 converts the basic pulse train signals f, □1 sent from the pulse train dividing circuit 6 into an acceleration/deceleration pulse train according to the acceleration/deceleration pattern data D A T A -m sent out from the acceleration/deceleration pattern data generation circuit 3. The signal f@d is sent to the acceleration/deceleration speed setting circuit 5. That is, in the acceleration/deceleration control circuit 4, the basic pulse train signal f□xl is converted into acceleration/deceleration pattern data DATA, d.
The frequency is divided based on the frequency, and an addition/subtraction pulse train signal ft+d, which is the frequency-divided output, is generated.

In this acceleration/deceleration speed setting circuit 5, the speed control CP
Based on the instruction from U2, this acceleration/deceleration pulse train signal fsa
is frequency-divided into a pulse train signal f mob corresponding to a desired speed change.

Further, in the constant speed control circuit 7, the speed control CPU
Based on the speed control block switching instruction of No. 2, the basic pulse train fmllX2 is input to generate a signal with a frequency corresponding to a desired offset, that is, a pulse train signal fores of constant speed coal. , and this pulse train signal f off
set to the pulse train synthesis circuit 8.

In this way, the pulse train synthesis circuit 8 generates a pulse train signal fs++b corresponding to the speed change and a pulse train signal f having a constant speed. 1
1□, and speed control pulse train signal f0
．． , to an interpolation calculation circuit (not shown). As a result, the driving body is driven and a workpiece having a predetermined shape is produced. Note that the pulse train signal f sob for the speed change
Since the pulse train signal f_sob and the constant speed pulse train signal f_sob have different phases from each other, they can be easily synthesized by the pulse train synthesis circuit 8.

As explained above, the pulse train signal f for the speed change,
wb and a pulse train signal f of the unchanged speed. Fry. , and processing, data for acceleration/deceleration control can be generated without considering speed offset. Therefore, the same acceleration/deceleration pattern data can always be used regardless of the presence or absence of a speed offset, and as a result, acceleration/deceleration patterns are not omitted, and the processing time of the speed control CPU 2 for changing the data is reduced. This becomes unnecessary, and therefore processing can be performed using the basic pulse train signal at the highest speed, allowing high-speed processing to be performed.

[Effects of the Invention] As explained above, the speed control circuit according to the present invention drives a driving body with a drive pulse signal that is a combination of a pulse signal for driving at a constant speed and a pulse signal for driving at an acceleration/deceleration. As a result, the processing device having this driving body can operate smoothly, and the workpiece can therefore be processed accurately. Further, the acceleration/deceleration pattern data changing process executed by the speed control@CPU is unnecessary, and therefore processing can be performed using the basic pulse train signal at the highest speed, resulting in high-speed processing.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the speed control circuit of the present invention, Fig. 2 is a timing chart of this circuit, Fig. 3 is a block diagram of a conventional speed control circuit, and Fig. 4 shows initial speed and final speed. Figure 5 is a diagram explaining the linear velocity change when there is no initial velocity, Figure 6 is a diagram explaining the linear velocity change when the final velocity is present. In the diagram shown in Figure 7, there is an initial velocity,
A diagram illustrating the ideal speed change when an STN acceleration/deceleration pattern or a special acceleration/deceleration pattern is included. Figure 8 shows the ideal speed when a final speed exists and a SIN acceleration/deceleration pattern or a special acceleration/deceleration pattern is included. 9 is a diagram illustrating the speed change in the prior art when there is an initial velocity and includes a SIN acceleration/deceleration pattern or a special acceleration/deceleration pattern. FIG. It is a figure explaining the speed change of the prior art when an acceleration/deceleration pattern or a special acceleration/deceleration pattern is included. 1-...Basic pulse generation circuit, 2...Speed control C
P LJ, 3... Acceleration/deceleration pattern data generation circuit,
4...Acceleration/deceleration control circuit, 5...Acceleration/deceleration speed setting circuit, 6...Pulse train division circuit, 7...-
・Constant speed control circuit, 8--Pulse train synthesis circuit, 2f,, , f02,. . -... Pulse train signal for constant speed coal, fud... Acceleration/deceleration pulse train signal, f out... Speed control pulse signal.

Claims (1)

[Scope of Claim] In a speed control circuit of a numerical control device that generates a speed command pulse for controlling the speed of interpolation calculation, a basic pulse generation circuit that generates a basic pulse train of a constant frequency; A pulse train dividing circuit that divides and outputs a pulse train output from the circuit into a first basic pulse train and a second basic pulse train that have mutually different phases; and a pulse train dividing circuit that stores acceleration/deceleration pattern data for accelerating and decelerating a driving body. The first basic pulse train and the acceleration/deceleration pattern data are input to an acceleration/deceleration pattern data generation circuit that sequentially outputs the acceleration/deceleration pattern data, and the first basic pulse train is accelerated according to the acceleration/deceleration pattern data. an acceleration/deceleration control circuit that converts the acceleration/deceleration pulse train into a deceleration pulse train and outputs the deceleration pulse train; an acceleration/deceleration speed setting circuit that converts the acceleration/deceleration pulse train into a pulse signal for driving the driving body at an acceleration/deceleration speed; and an acceleration/deceleration speed setting circuit that receives the second basic pulse train. , a constant speed control circuit that converts into a pulse signal for driving the drive body at a constant speed, and a drive pulse signal for the drive body that inputs and synthesizes each pulse signal from the acceleration/deceleration speed setting circuit and the constant speed control circuit. A speed control circuit comprising: a pulse train synthesis circuit that outputs a pulse train synthesis circuit.