JPH03270951A - Driving device of thermal head - Google Patents

Abstract

PURPOSE:To enable printing from binary to specific gradation and high speed printing by a binary image data to be performed by a method wherein a latch circuit latching a lowest order bit is connected by branching to a memory means which stores the image data to the specific gradation. CONSTITUTION:M pieces of one bit binary image data D0 are prepared correspondingly to a heating element 5, are successively outputted from a control circuit 90A at timing of a clock CK, and are latched to respective latch circuit 1. Then, a latch pulse LATCH is outputted, and the data D0 is latched as a lowest order bit to a one bit latch circuit 2 from the latch circuit 1. Consequently, the data D0 and enable signals EN0-ENN-1 are successively applied to a gate 3. Since the gate 3 outputs a signal to make a driver 4 perform communication by a pulse width of D0.EN0, printing of binary image corresponding to a pulse width of a signal EN0 is performed. Then, binary image data D0 of a next line pixel is transferred to the latch circuit 1 during that time, and printing of the next line is performed in the same way. Therefore, a printing interval becomes T1, and high speed printing becomes capable of being performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a driving device for a thermal head that can be applied to, for example, a halftone facsimile machine.

(Conventional technology) A conventional thermal head driving device is shown in FIG.

The thermal head 100 includes a plurality of heat generating resistors 5 connected to a driver 4 that generate heat for pixel-based printing. In this figure, a drive circuit corresponding to one heating resistor 5 is shown.

The latch circuit 1 has an N-bit input and an N-bit output, and latches input data at the rising edge of the shift clock CK, for example. The input data is gradation data of up to N bits corresponding to a pixel. The latch circuits 1 are cascade-connected, and N-bit gradation data D□ to D
N-1 is being shifted. A gate 3 is branch-connected between each latch circuit 1 . Gate 3 has a control diagram Fl@
90, the weight (
N-bit enable signal E No with pulse width)
~ENN-1 are given sequentially. Therefore, the gate 3 receives the gradation data D□~DN− given from the latch circuit 1.
1, the enable signals ENo to ENN, , 1 are controlled to pass or not pass;

NEO+DI NEl-i-D2 NH3+...-
Driver 4 outputs a pulse width of rDH-INEN-1.
, thereby energizing and driving the heating resistor 5 (FIG. 4).

However, according to the above device, since the gate 3 is configured to directly receive the output of the latch circuit 1, while the heating resistor 5 is being driven, the cascaded latch circuits 1 are used as shift registers to obtain the grayscale data D. □ to DN-1 could not be transferred, which was an obstacle to increasing the printing speed. That is, during time T2 in FIG. 4, after the output of the enable signal ENN-1, the gray scale data ENo to ENNi
It takes time to transfer the information.

Therefore, as shown in FIG.
6 is provided, and the latch circuit l is used as a shift register to obtain gray scale data D. ~Transfer DN-1, then latch pulse LAT
CH is applied to the latch circuit 6 to latch the data on the latch circuit. Next, as explained in FIG. 4, the enable signal E N is applied.

~E N N-1 is applied to drive the heating resistor 5. At this time, since the data latched on the latch circuit is not used directly, the latch circuit l is provided with gradation data D□ to DN-1 corresponding to each pixel of the next line.
Transfer as shown in the diagram. For this reason, enable ENN
Immediately after applying -1, latch pulse LATCH is applied to transfer the contents of latch circuit 1 to latch circuit B6, and enable signals ENo to ENN-i are applied from enable signal E□ to print the next line. It becomes like this. Therefore, the printing interval between one line of strokes is T1, which is shorter than the printing interval of one line of strokes by the apparatus shown in FIG. 3, which is T2.

(Problem to be Solved by the Invention) However, in the thermal head driving device shown in FIG. A problem arises in that the size of the device increases.

Furthermore, the gradation data for printing halftones etc. is obtained by decoding the sent halftone data, and since this decoding takes time, even if the printing interval is shortened as described above. This does not result in shortening the overall printing time. On the other hand, the above-mentioned apparatus may also use binary image data, and in this case, it is required to shorten the printing interval since halftone data requires no time to decode.

The present invention was made in view of various demands for a thermal head drive device that can perform halftone printing, and its purpose is to be able to print from binary to predetermined gradations, and to Achieves high-speed printing when printing based on image data,
Moreover, it is an object of the present invention to provide a driving device for a thermal head that does not have a large structure.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a thermal head configured by a plurality of heating resistors that generate heat for pixel-based printing, and a predetermined temperature for each heating resistor. Storage means for storing image data up to the gradation level are connected in cascade, and an image data transfer means for sequentially transferring the image data in parallel is branch-connected between the cascaded storage means, and the output from the storage means is connected in a branch manner. a latch circuit that captures the least significant bit of the image data, a energization permission signal sending stage that sends out an energization permission signal that permits energization of each of the heating resistors, and a latch circuit that corresponds to each of the heating resistors. energization control means for controlling energization of the corresponding heat generating resistor based on an output other than the least significant bit outputted from the storage means and an energization permission signal given by the energization permission signal sending means; A driving device for the thermal head was constructed using the following.

(Function) According to the above configuration, since the storage means stores image data up to a predetermined gradation, printing up to halftones is possible, and a latch circuit that latches the least significant bit is branch-connected to this storage means. Therefore, in the case of binary image data, this latch circuit is latched to energize the heating resistor, and during this time the image data of the pixel for the next printing can be transferred to the storage means mentioned above. It is possible to increase the speed, and since it is an l-bit latch circuit, there is no need to increase the size of the conventional circuit.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

The second engineering drawing is a diagram showing the configuration of the present invention. Thermal head 10
A plurality of heating resistors 5 which generate heat when energized for pixel-based printing are connected to the driver 4 and arranged in a plurality. In this figure, only a drive circuit corresponding to one heating resistor 5 is shown. The latch circuit 1 has an N-bit input and an N-bit output, and has a shift clock CK.
Input data is latched, for example, at the rising edge of . The input data is binary image data D. and gradation data Do to DN-1 of up to N bits are given. The latch circuits 1 are connected in cascade and are sequentially supplied with shift clocks CK, so that N-bit gradation data D□ to DN-1 are shifted in parallel.

The output on each latch circuit is applied to the input of the latch circuit 1 at the next stage, and is branched, with the least significant bit being applied to the 1-bit latch circuit 2 and the remaining bits being applied to the gate 3. A latch pulse LATCH is applied to the 1-bit latch circuit 2, and, for example, the least significant bit D is output by the rising edge of the latch pulse LATCH. is latched and the output is given to gate 3. The control circuit 90A sequentially supplies N-bit enable signals E No to E N N-i with different weights (pulse widths) for l bits at a time, which are energization permission signals, to the gate 3 . Therefore, the gate 3 receives the gradation data Do to DN output from the latch circuit 1 and from the l-bit latch circuit 2.
-1, control is performed to pass or not pass enable signals ENo to ENNI.

The operation of halftone printing and the printing operation of binary image data by the thermal head drive device configured as described above will be explained with reference to FIG.

First, when printing in halftones, N-bit tone data D is used. ~M pieces of DN-1 are prepared corresponding to the heating resistors 5, and the control circuit 90A provides them at the timing of the clock CK.
The signals are sequentially output and latched by each latch circuit. next,
A latch pulse LATCH is output, the least significant bit of the latch circuit 1 is latched into the 1-bit latch #I2, and the gate 3 is given N-bit gradation data Do to DN-1. Therefore, enable signals ENo to ENNi are sequentially applied. Then, at gate 3, D□ -ENo 10, DI HEI'J1 +D2
・EN2 10--rDN-I HENN-1 A signal is output to the driver 4 to energize with a pulse width of Halftone printing is performed. Thereafter, since the next line is printed in the same manner, the printing interval becomes T2. However, as described above, in the case of halftone printing, decoding takes time, so this time T7 cannot be a factor that slows down the printing time.

When printing with binary image data, 1-bit binary image data D is used. are prepared in M pieces corresponding to the heating resistors 5, are sequentially output from the control circuit 90A at the timing of the clock CK, and are latched by each latch circuit. Next, a latch pulse LATCH is outputted to generate the binary image data D. is latched from latch 481 to 1-bit latch circuit 2 as the least significant bit. As a result, gate 3 has binary image data D□
is given, and here the gate 3 hay enable signal ENo~
ENN-1 is given sequentially. Then, at gate 3, D
A signal is output to cause the driver 4 to conduct electricity with a pulse width of o·E N o. Therefore, a binary image is printed according to the pulse width of the enable signal ENo. Then, while the enable signals ENo to ENN are sequentially applied, the binary image data Do of the pixels of the next line is transferred to the latch circuit #11. Thereafter, since the next line is printed in the same manner, the printing interval is T1. That is, high-speed printing can be achieved in the case of binary image data that requires no time to decode.

Thus, by using the same device and simply changing the sending timing of the latch pulse LATCH, it is possible to perform halftone printing and printing using higher speed binary image data. According to FIG. 2, since the pulse width of ENo is the narrowest, it is thought that it is not suitable for printing with binary image data, but this is just an example, and the enable signals EN0 to E
The pulse widths of NN- and NN- are set appropriately (the width of the pulses may be reversed from this example), and a suitable two-blemish image is realized by energizing D-EN□.

[Effects of the Invention] As explained above, according to the present invention, since the storage means stores image data up to a predetermined gradation, printing up to halftones is possible, and the storage means stores the least significant bit. Since the latch circuit that latches is branch-connected, in the case of binary image data, this latch circuit is latched and the heating resistor is energized, and during this time, the data related to the next printing is stored in the above storage means. Since it is possible to transfer pixel image data, the speed can be increased, and since it is a 1-bit latch circuit, it does not need to be any larger than conventional circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of an embodiment of the present invention.
3 and 5 are block diagrams of conventional thermal head drive devices, respectively, and FIGS. 4 and 6 are block diagrams of conventional thermal head drive devices, respectively.
3 is a time chart for explaining the operation of the conventional example shown in the figure. 1...Latch circuit 2...1 bit 3...Gate 4...Driver 5...Heating resistor
90A...Control circuit 100...Thermal head

Claims (1)

[Scope of Claims] A thermal head configured by a plurality of heating resistors that generate heat for pixel-based printing, and a storage means for storing image data up to a predetermined gradation for each of the heating resistors. are cascade-connected to sequentially transfer image data in parallel; and a latch that is branch-connected between the cascade-connected storage means and captures the least significant bit of the image data output from the storage means. a circuit; an energization permission signal sending means for sending an energization permission signal for permitting energization of each of the heat generating resistors; an output of a latch circuit corresponding to each of the heat generating resistors; and a least significant bit output from the storage means. 1. A driving device for a thermal head, comprising: an energization control means for controlling energization of a corresponding heating resistor based on an energization permission signal given from the energization permission signal sending means.