JPH03270428A - Automatic phase correcting circuit - Google Patents

Abstract

PURPOSE:To enable stable data transfer without depending on a distance with no control by storing the output of a delay detecting means into a storing means and controlling a selective circuit according to stored contents. CONSTITUTION:A timing generation circuit 1 generates the plural frame pulses of various phases and plural phase clocks corresponding to those frame pulses. For example, these plural frame pulses and phase clocks are composed of totally two groups advancing the phase clocks by a half clock. The selecting circuit 2 correspondently selects the frame pulses and clock pulses to be generated by the timing generation circuit 1, and a delay detecting means 4 discriminates whether the frame pulse from an external part is delayed or not in respect to the frame pulse generated from the timing pulse generation circuit 1 and delayed by a delay means 3. A storing means 5 stores the output of the delay detecting means 4 and according to the stored contents, the selective circuit 2 is controlled. In such a manner, the phase is automatically controlled and timing is selected so as to obtain the correct phase. Thus, manual work is not required and the stable data transfer is enabled.

Description

[Detailed Description of the Invention] [Summary] Regarding an automatic phase correction circuit that corrects the phase due to the distance between a transmitting circuit and a receiving circuit, an automatic phase correction circuit that performs stable data transfer without adjustment and independent of distance is provided. A timing generation circuit that generates a plurality of frame pulses with different phases and phase clocks corresponding to the frame pulses, and a timing generation circuit that generates a plurality of frame pulses and clock pulses generated by the timing generation circuit. A selection circuit to select, a delay detection means for determining whether an external frame pulse lags behind a frame pulse generated by the timing pulse generation circuit and delayed by the delay means, and an output of the delay detection means is stored. and storage means for controlling the selection circuit with the stored contents.

[Industrial application field]

The present invention relates to a data transmitting/receiving device, and more particularly to an automatic phase correction circuit that corrects the phase depending on the distance between a transmitting circuit and a receiving circuit.

[Conventional technology]

With the development of digital technology, large amounts of data have come to be handled. Along with this, digital signals have also become faster, making it possible to send and receive large amounts of data.

In the above-mentioned devices for transmitting and receiving data, a method is often used in which a plurality of data are transmitted in a so-called frame, which is a set of data.

FIG. 6 is a block diagram of the prior art. A timing controller (TIM CTL) 11 is included in the receiving device 10, and the frame pulse and clock pulse are sent to the driver DVI,
It is added to the transmitting device 13 via DV2. The transmitting device 13 receives frame pulses as well as clock pulses by receivers REC4 and REC5 and applies them to a timing (TIM) circuit 14. Although not shown, various types of data, frames, etc. to be sent are created by timing pulses generated by this timing circuit and outputted by a circuit to be described later.

The aforementioned clock pulses are received by the receiver REC5 and applied to the timing circuit 14, but are also sent back to the receiving device 10 via the driver DV5. Also, delay circuit DL1. It is applied to the clock terminals of the transmission registers 5-REG1 and 5-R2O3 via DL2 and the selection jumper circuit JP. Transmission register 5-REGI, 5-R2O3
launches a signal to be transmitted using a clock delayed by one of the delay circuits DLI and DL2 (selection is determined by a jumper), and sends frame pulses and data to the receiving device 10 via drivers DV3 to DV4. Then, on the receiving device side, the receiving register R-R
The data received by the EG is captured using the clock sent back.

There is no problem if the distance @1 between the transmitting device 13 and the receiving device 10 is shorter than the period of the transmitting clock, but if the clock becomes faster and the distance is long, the delay due to this distance Ml becomes a problem.

7 and 8 are timing charts of the conventional circuit. FIG. 7 shows the case where the distance l is short, and FIG. 8 shows the case where the distance l is long. Note that the signals ■' to O' correspond to each point on the circuit diagram. When the delay circuit DLI is used in a fixed manner, the delay will not be a problem if the distance l is short, and the delay will not be a problem if the distance l is short. 13 to the receiver register R-REG via the receiver REC2.
The data [phase]' taken in becomes data corresponding to the same address (T1 in FIG. 7), and normal data can be written into the memory (MEM) 12. This is because the distance l is short. In other words, the frame ■' output from the transmitting device 13 corresponding to the frame input from the driver DVI is captured with a delay of approximately 1 clock at the timing at which the transmitting register 5-REG1 captures the data and the timing at which the data is captured into the transmitting register 5-R2O3. is delayed by delay line DLI, and then the delayed signal is sent to driver DV3. It is sent to the receiving device 10 via DV4. Since the clock is similarly received by the receiver REC3 via the driver DV5 and taken into the register via the receiver REC2, a data delay due to this distance does not affect the receiving register R-REG. The data taken in by -REG is taken in at the point where the clock [phase]' rises before T1, and is taken in correspondingly by the write pulse O' generated by the timing controller 11.

On the other hand, when the distance l is long as shown in Fig. 8, for example, if the delay circuit is left as DLI, when the length l to be transmitted is short with respect to the transmitted clock ■' and frame pulse ■', The timing of taking in the transmission registers 5-REGl and 5-REG2 is delayed from the timing TO, and this delay delays the data and frame received on the receiving word 210 side, as well as the clock. Therefore, the pulse taken into the reception register R-REG becomes the target data, but the distance il! II! Because of the long time, a delay occurs in the entire data, and the addresses and write pulses generated by the timing controller 11 corresponding to the data to be loaded into the memory have different timings. That is, the data output from the reception register R-REG is delayed by one clock from the address [phase]' output from the timing controller 11, and different data is stored at different and incorrect addresses. In order to prevent timing errors due to the distance between the transmitting device 13 and the receiving device 11, conventionally a delay circuit DL2 is provided in addition to the delay circuit DLI shown in FIG. Prevents errors. That is, as shown in FIG. 9, even when the distance l is long, the delay circuits DL1. DL2 is selected by a jumper line to ensure error-free transfer.

[Problem to be solved by the invention]

As described above, conventionally, the distance is determined at the time of tax adjustment or installation, and the delay circuit DLI or delay circuit DL2 is selected by the jumper wire JP, and settings are made to enable stable data transfer.

With the conventional method described above, reliable data transfer is possible, but when replacing or installing a defective package, adjustments must be made each time, making it impossible to simply ship replacement parts and have the user install them. Ta. That is, P
There is a problem in that it is complicated to perform phase correction each time during maintenance such as KG replacement, and that adjustment requires a large amount of man-hours.

An object of the present invention is to provide an automatic phase correction circuit that performs stable data transfer without adjustment and independent of distance.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

The tying generation circuit 1 generates a plurality of frame pulses having different phases and a plurality of phase clocks corresponding to the frame pulses. For example, the plurality of frame pulses and the phase clock are more powerful than a total of two groups that are half a lock ahead of the phase clock.

The selection circuit 2 selects the frame pulse and the clock pulse generated by the timing generation circuit 1 in a corresponding manner.

The delay detection means 4 determines whether the external frame pulse is delayed with respect to the frame pulse generated by the timing pulse generation circuit 1 and delayed by the delay means 3.

The storage means 5 stores the output of the delay detection means 4 and controls the selection circuit 2 based on the stored contents.

[For production]

FIG. 1 is a block diagram of the principle of the present invention. The timing generation circuit 1 generates two groups of signals, for example, a basic frame pulse and clock, and a frame pulse and clock that are half a lock ahead of the basic clock as a reference. The selection means 2 selects these two groups of signals. First, the selection means 2 selects a basic frame pulse and clock. Then, a frame pulse applied from the outside is outputted from the timing generation circuit 1, and the delay detection means 4 detects whether it is delayed from the basic frame pulse passed through the delay means 3. This delay is detected by inputting the basic frame pulse through the delay means 3 into the launch circuit. As a result, when there is a delay, the selection means 2 selects the group that has a better chance of half a clock between the frame pulse and the clock. Also, if you are not late, leave it as is. Thereby, frame pulses and clocks corresponding to data sent from the outside can be obtained.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIGS. 3 to 5 are tying charts of the embodiment of the present invention. The receiving device 20 is a timing controller (TIM CTL) 2
1. This timing controller 21 outputs frame pulses and clock pulses of two phases in correspondence with each other.

Each frame pulse and clock pulse is divided into 0 phase P0 and 1 phase P according to its group.

When the power is turned on, the O-phase PO signal is selected. Therefore,
Frame selector SEL 1, clock selector SEL
2 selects the frame signal [phase] and clock signal [phase] output from the timing controller and sends the driver DV
11. It is added to the transmitting device 23 (■, ■) via the DV12 (■, ■). Driver DVII, Driver DV1
The frame pulse and clock pulse output from 2.
■ Receiver RECI4 of the transmitting device 23. RECI5
It is applied to the timing circuit (TIM) 24 via (■, ■). Then, for example, data and frame pulses to be transmitted are created by a circuit (not shown) (■, ■) and added to the transmission registers 5-REG4 and 5-REG5. Receiver RE
The clock received by C15 is further passed through a delay circuit DL.
■), transmission register 5-REG4,5-RE
It is also added to the clock input terminal of G5. Transmission register 5-
taken in by REG4゜5-REG5 (delay circuit DL
Transmission frames and data (taken in by the input clock via I) are sent to the driver DVI 1. ■, @l) is sent to the receiving device t20 via the DVI2 (Olo
). A clock is also sent from the receiver REC15 (0> to the transmitting device 23 via the driver DV13 ([phase]). This clock is received by the receiver REC13 and becomes the timing clock for the receiving register R-REG4. The frame is added to the reception register R-REG4 via REC12 and taken in by the clock received by the receiver REC13.Furthermore, the transmission frame is added to a circuit (not shown) via the receiver RECII, and is input to the flip-flop FF3.

On the other hand, the clock ([phase]) applied to the 0 terminal of clock selector SL2 is applied to flip-flops FFI and FF2. The flip-flops FFI and FF2 operate a two-stage shift register using an O-phase clock PO. The input of this flip-flop FFI has a phase PO
A frame pulse (0) corresponding to
2 causes a delay (o) of two clock pulses.

The output ([phase]) of the flip-flop FF2 is input to the clock terminal of the flip-flop FF3. In other words, the received frame to be sent is
The timing is delayed by a clock and is used as the timing for taking in the flip-flop FF3.

The transmission frame pulse sent from the transmitting device 23 is added to the input of the flip-flop FF3, and when the frame sent from the transmitting device is input earlier than the frame pulse delayed by two clocks, the flip-flop FF3 takes in that frame pulse. (Take in H level).

The output of flip-flop FF3 is an inverted output, so the output becomes O level (0). Therefore, OR gate (OR
) output (@) also becomes 0 level, and from then on the selector selects frame pulse (@l) and clock pulse [phase],
It is output to the transmitting device 23. These signals are sequentially output, but since the distance l is short, the flip-flop FF3 takes in the frame pulse signal output from the transmitting device, always takes in the H level, and outputs the 0 level. At this time, since the O level is always applied to the clock terminal of the counter CNT, the counter does not increment and its output (O)
becomes O level, and this state continues. That is, at timing T6 shown in FIG. 3, correct data corresponding to the address [phase] is taken into the memory 23 by the write pulse WO.

On the other hand, even if l is long and the output of flip-flop FF3 is at l level, the frame pulse output from the sending bag W23 is further delayed than the timing mentioned above.
This is further delayed than the phase 0 frame which is added with a clock delay, and the flip-flop FF3 takes in the same level (0 level). As a result, flip-flop FF3 becomes L level, and the output of OR gate OR (@)
is also at l level. At this time, the write pulse W (@) is manually applied to the address added to the memory 23, but the data corresponding to this address is delayed (4th TI)
. However, this situation is at the time of tax adjustment, etc., so there is no problem. Due to the above-mentioned operation, the output of the OR gate OR becomes L level, so the frame selector SLI and clock selector SL2 select the signal of one terminal, and one phase P1.
Select the frame pulse and clock pulse (see ◯ if Fig. 5 1 is long). This selected signal is output to the transmitter 23 as a frame pulse and a clock pulse. Incidentally, at this time, the frame pulse and the clock pulse are signals whose phase is advanced by half a cycle of the clock. By advancing the phase of the frame pulse and clock pulse, the frame and data output from the transmitting device 23. Furthermore, the clock is outputted from the transmitting device 23 by half a cycle, and the frame pulse is inputted earlier than the rising edge of the clock pulse of the flip-flop FF3. do. Therefore, the flip-flop FF3 takes in the l level, and its output (■) becomes the l level. As a result, when l is long in FIG. 4, the timing shown in (3) is performed again, and since the frame pulse is similarly delayed at this time, no frame pulse is taken in again, and the output of the flip-flop FF3 becomes high level. With this rise, the counter becomes "2" and its output (o) becomes L level. The output Ql of the counter CNT is applied to the enable terminal, and when the output Q1 reaches the L level, the counter becomes deceiver and remains at H level. As a result, the output of the OR gate (■
) is at L level, and the 1 side of the clock is always selected. That is, a frame pulse and a clock pulse that are half a clock faster are output from the transmitter, and a clock pulse and a frame pulse with the distance l corrected are output (dotted line in FIG. 5). Therefore, the human data of memory (MEM) 23 (
[phase]) is specified by the address (@〉 value) and is taken in by the write pulse W (@) (T).

Through the above-described operation, the phase is automatically corrected in the memory 23 regardless of whether the distance l between the devices is short or long. The target data can be stored at the target address. Note that when l is long, in case JliA, different data is temporarily fetched into a different address at timing T8, but this is done during tuning, for example, tax adjustment, and from then on, by setting the -degree counter. Selected according to the target phase.

Although the present invention has been explained above using embodiments, the present invention has two
It is also possible to obtain the best phase by selecting not only a single phase but also a plurality of phases.

Although the phase difference between the two pulses is a half cycle, the phase difference is not limited to a half cycle, and the lead or delay is not limited to this.

〔Effect of the invention〕

As described above, according to the present invention, the phase is automatically adjusted and the timing at which the correct phase should be obtained is selected, so that there is no need for manpower for tax adjustment, and adjustment can be easily performed.

[Brief explanation of drawings]

Figure 1 is a principle block diagram of the present invention, Figure 2 is a configuration diagram of an embodiment of the present invention, Figures 3, 4, and 5 are timing charts of the embodiment of the present invention, and Figure 6 is a conventional example. 7, 8, and 9 are timing charts of conventional circuits. DESCRIPTION OF SYMBOLS 1... Timing generation circuit, 2... Selection circuit, 3... Delay means, 4... Delay detection means, 5... Storage means.

Claims (1)

[Claims] 1) A timing generation circuit (1) that generates a plurality of frame pulses with different phases and a plurality of phase clocks corresponding to the frame pulses, and frame pulses and clock pulses generated by the timing generation circuit (1). Selection circuit (2) that selects in correspondence with
and a delay detection means (4) for determining whether an external frame pulse lags behind a frame pulse generated by the timing pulse generation circuit (1) and delayed by the delay means (3); and the delay detection means. An automatic phase correction circuit characterized by comprising a storage means (5) for storing the output of (4) and controlling the selection circuit (2) with the stored contents. 2) The delay detection means (4) is a latch circuit, which takes in the frame pulse applied from the outside with the output of the delay means (3), and also captures the basic frame pulse with the basic clock generated from the timing generation circuit (1). The automatic phase correction circuit according to claim 1, characterized in that the automatic phase correction circuit is delayed. 3) The timing generation circuit (1) outputs a basic frame pulse and a frame pulse delayed by half a clock with respect to the basic frame pulse, and the delay detection means (4) detects a delay in the frame pulse from the outside. 2. The automatic phase correction circuit according to claim 1, wherein said selection circuit (2) selects a frame pulse delayed by said half clock.