JPH03270294A - Multiplayer circuit board - Google Patents

Abstract

PURPOSE:To enhance reliability of connecting an interconnection pattern and insulation between input and output pads by extending an insulating film of a lowermost layer to an input/output pad forming region except the input/output pads to be formed. CONSTITUTION:An insulating film 20 of a first layer of an insulating layer of a lowermost layer is extended to the entire surface of the peripheral edge of a ceramic board 1 except input/output pads 3 to be formed. Accordingly, generation of residue of catalytic metal is prevented on the board 1 merely by adhering the metal 25 to the film 20 of the first layer at the time of pretreating of forming conductor patterns 30, 50 of a second layer, a third layer,... to obtain insulation between the pads 3. A fear of invading a miniaturized conductor pattern is reduced by quick etching the pattern of a thin film conductor layer. Thus, reliability of connecting the interconnection pattern and insulation between the pads is enhanced.

Description

[Detailed Description of the Invention] [Summary] A multilayer circuit board in which a multilayer wiring part in which insulating layers and conductor layers are alternately laminated is provided in the center of the board, and a semiconductor chip is mounted on this multilayer wiring part. The purpose of this research is to provide a multilayer circuit board with high reliability of connection between input and output pads, and high reliability of insulation between input and output pads. A circuit board in which input/output pads are provided in the center and arranged on the surface of the periphery of the ceramic substrate, and the lowermost insulating film is formed by extending to the input/output pad formation area excluding the input/output pads. shall be.

[Industrial application field]

The present invention relates to a multilayer circuit board in which a multilayer wiring section in which insulating layers and conductor layers are alternately laminated is provided in the center of the substrate, and a semiconductor chip is mounted on the multilayer wiring section.

As electronic devices become faster and more highly integrated, in recent years, insulating layers made of low dielectric constant materials and conductor pattern layers made of low resistivity conductive materials are alternately laminated on the surface of heat-resistant substrates such as ceramics. A multilayer circuit board is provided.

On the other hand, polyimide resin has a low dielectric constant, is suitable for high-speed signals, is heat resistant, and has a smooth surface, so it is widely used as an insulating layer for such multilayer circuit boards.

In addition, by making the width of these conductor patterns finer,
Dealing with high integration.

[Conventional technology]

FIG. 3 is a sectional view of a conventional example, and FIG. 4 is a perspective view of a multilayer circuit board.

In FIGS. 3 and 4, a square multilayer wiring section 2 is provided in the center of a square plate-shaped ceramic substrate 1.
Numerous in and out covers, on the peripheral surface of the.

3 is installed.

Each of the input/output pads 3 is connected to a first layer conductor pattern of the multilayer wiring section 2 via a thin film pattern (not shown).

The multilayer wiring section 2 includes, on the surface of the ceramic substrate 1, a 1N conductor pattern 10, a first layer insulating film 20, a second layer conductor pattern 30, a second layer insulating film 40, and a third layer conductor pattern. 50, a third layer insulating film 60, and a fourth layer conductor pattern 70, which is the uppermost conductor layer.

The laminated conductor patterns are connected by providing vias 90 at desired locations.

In addition, pads (not shown) that are connected to the fourth layer conductor pattern 70 or to the lower layer conductor pattern via vias are arranged on the upper surface of the uppermost insulating film, so that the semiconductor layer is formed on the surface of the multilayer wiring section 2. It's time to mount the chip.

The manufacturing process of the multilayer circuit board as described above will be explained with reference to FIG.

In FIG. 5, reference numeral 1 indicates a ceramic ink substrate in the form of a square plate.

■ Formation of conductor patterns, input/output pads, and first layer insulating film (see Figure 5 (a)) A gold Kl film such as copper is formed on the entire surface of the ceramic substrate 1 by vapor deposition, sputtering, or electroless plating. After that, etching is performed to provide a metal pattern as a base for the first layer conductor pattern and the input/output pad, and further electrolytic plating is performed to form the first layer conductor pattern 10 in the center of the ceramic substrate 1. Human output pads 3 are arranged and formed on the periphery.

Next, polyimide resin is applied to the entire surface of the ceramic substrate 1 using a spin code method, etc., and after the surface is flattened, it is heat treated (80''C to 100℃) to coat the entire surface of the ceramic substrate 1 with polyimide resin. A monomer insulating layer is provided, and the first layer conductor pattern 1 is formed using photolithography technology.
0 and the ceramic substrate 1
Patterning is performed to remove the monomer insulating layer from the frame-shaped portion around the periphery (including the top surface of the input/output pad 3).

Thereafter, heat treatment (350° C. to 400° C.) is performed to polymerize the polyimide resin in a monomer state, thereby forming the first layer insulating film 20 made of the polyimide resin in a polymer state.

■ Pretreatment for conductor layer formation (see Figure 5(b)) Pd, S
By immersing the ceramic substrate in a pretreatment agent containing the catalyst metal 25 such as n, etc., the catalyst metal 25 is attached to the entire surface of the ceramic substrate 1 including the surface of the first layer insulating film 20. This enables the formation of a thin film conductor layer in the next step.

■ Formation of a thin film conductor layer (see FIG. 5(C)) Copper is applied to the entire surface of the ceramic substrate 1, including the surface of the first layer insulating film 20, the inside of the via hole 21, and the surface of the input/output pad 3. A thin film conductor layer 31 is formed by electroless plating.

Further, at this time, the via hole 21 is filled with a conductive metal, so that the via hole 21 becomes a via 90.

■ Photoresist pattern formation (see Figure 5(d))
A photoresist 32 is applied to the entire surface of the thin film conductor layer 31, leveled and heat treated (80°C to 100”C).
After that, patterning is performed by photolithography to provide a photoresist pattern in which portions of the photoresist corresponding to the second layer conductor patterns are removed.

■ Conductor pattern type tc of the second layer (see Figure 5(e)) A copper film is laminated by electrolytically plating copper on the exposed top surface of the thin film conductor layer 31 in the photoresist pattern part. A second layer conductor pattern 30 having a desired thickness is provided.

■ Patterning of the WtM conductor layer (see Fig. 5(f)) After removing the photoresist 32 using an organic solvent, quick etching is performed to remove unnecessary thin film conductor layers, that is, the first layer of insulating film. Thin film conductor layer 31 on the surface of 20. Peeling off the thin film conductor layer 31 on the frame portion of the periphery of the ceramic substrate,
Buttering the thin film conductor layer.

By repeating the above-described steps, the second layer insulating film, the third layer conductor pattern, the third layer insulating film, and the fourth layer conductor pattern are formed on the second layer conductor pattern 30 in this order. A multilayer circuit board as shown in FIG. 3 is provided.

[Problem to be solved by the invention]

Incidentally, although the surface of the ceramic substrate 1 has been polished or otherwise smoothed in advance, when viewed microscopically, microcranks are present on the surface.

IN in this micro crack! The catalyst metal 25 used in the pre-treatment when forming the conductor layer has eaten into the space between the input and output pads 3 of the ceramic substrate 1 as shown in FIG. A residue of the catalyst metal 25 is generated.

In the case of multilayer circuit boards, this residue is generated and accumulated a number of times equal to the number of thin film conductor layers, that is, the number of conductor pattern layers from the second layer onwards, and as a result, conventional multilayer circuit boards have There was a problem that insulation was not ensured.

In order to remove this residue, it is possible to strengthen and prolong the quick etching for removing the IIM conductor layer, but if such a treatment is carried out, the fine conductor pattern will become even thinner and eroded. Otherwise, the film thickness of the conductor pattern becomes thinner and the conductor pattern deteriorates.

The present invention was created in view of these points, and aims to provide a multilayer circuit board with high reliability in connection of wiring patterns and high reliability in insulation between input and output pads. There is.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a multilayer wiring section 2 in which insulating layers and conductor layers are alternately laminated in the center of a ceramic substrate 1, as illustrated in FIG. In the circuit board on which input/output pads 3 are arranged on the surface of the peripheral edge of
20 is formed by extending to the entire surface of the peripheral edge of the ceramic substrate 1 excluding the input/output pads 3.

Further, as illustrated in FIG. 2, the lowermost insulating film 20 is formed by extending to the entire surface of the periphery of the ceramic substrate l so as to cover the periphery 3A of the input/output pad 3. .

[Effect]

As described above, the first layer insulating film 20 of the multilayer wiring section 2 is formed on the surface of the ceramic substrate 1 except for the input/output pad 3 portion.
is formed by stretching.

Therefore, during the pretreatment for forming conductor patterns in the second layer, third layer, fourth layer, . . . , the catalyst metal 25 only adheres to the surface of the first layer insulating film 20.

That is, since the generation of catalyst metal residue on the surface of the ceramic substrate is prevented, insulation between the input and output pads is ensured.

In addition, by quick etching the patterning of the thin film conductor layer, unnecessary portions of the FFL film conductor layer can be removed, so there is less risk of the fine conductor pattern being attacked and the reliability of wiring pattern connections is high. .

〔Example〕

The present invention will be specifically described below with reference to the drawings. Note that the same reference numerals indicate the same objects throughout the figures.

FIG. 1 is a sectional view of the first invention, and FIG. 2 is a sectional view of the second invention.

In FIG. 1, a square multilayer wiring section 2 is provided in the center of a ceramic substrate 1 in the shape of a square plate, and a large number of input/output pads 3 are arranged on the peripheral surface of the ceramic substrate 1.

Each of the input/output pads 3 is connected to a first layer conductor pattern of the multilayer wiring section 2 via a thin film pattern (not shown) formed on the surface of the ceramic substrate 1.

The multilayer wiring section 2 includes, on the surface of the ceramic substrate 1, a first layer conductor pattern 10, a first layer insulation M20, a second layer conductor pattern 30, a second layer insulation W140, and a third layer conductor pattern 50. , a third layer of insulating film 60, and a fourth layer of conductor pattern 70, which is the top conductor layer, are stacked in this order.

The conductor patterns laminated above and below are connected by providing vias 90 at desired locations, and the upper surface of the uppermost insulating film is connected to the conductor pattern 70 of the fourth layer or connected to the lower layer through the vias. A semiconductor chip is mounted on the surface of the multilayer wiring section 2 by arranging pads (not shown) connected to the conductor patterns.

On the other hand, the above-described first layer conductor pattern 10 and input/output pad 3 are formed at the same time in the same process.

In the present invention, this first layer insulating film 20 is extended around the four circumferences of the multilayer wiring section 2 to cover the entire surface of the peripheral edge of the ceramic substrate 1 excluding the input/output pads 3, that is, the input/output pad forming area. It was formed.

The first layer insulating film 20, which extends to the periphery of the ceramic substrate 1, that is, to the input/output pad forming area, is formed in the following manner.

Polyimide resin is applied to the entire surface of the ceramic substrate 1 using a spin code method or the like, and after the surface is flattened, heat treatment (
80''C to 100°C), a monomer insulating layer of polyimide resin is applied to the entire surface of the ceramic substrate 1, and then a via hole 21 portion connected to the conductor pattern 10 of the first layer is formed using photolithography technology. Then, patterning is performed to remove the monomer insulating layer on the surface of the input/output pad 3.

Then, the polyimide resin in the monomer state is polymerized by heat treatment (350° C. to 400° C.) to form the first layer insulating film 20 made of the polyimide resin in the polymer state.

According to the present invention, the insulating film 2 of the first layer of the multilayer wiring section 2 is formed on the surface of the ceramic substrate 1 except for the human output buff 13 portion.
0 is formed by stretching.

Therefore, during pre-treatment for forming conductor patterns in the second layer, third layer, fourth layer, etc., the catalytic metal is only attached to the surface of the first layer insulating film 20, and The generation of catalyst metal residue on the surface of the ceramic substrate is prevented.

In addition, since the thin film conductor layer can be patterned by quick etching, there is less risk of erosion of the fine conductor pattern.

The multilayer circuit board shown in FIG. 2 has the following features except that the first layer insulating film 20 is formed by extending to the entire surface of the peripheral edge of the ceramic substrate l so as to cover the peripheral edge 3pl of the input/output pad 3. It has the same structure as the multilayer circuit board shown in FIG.

In this way, since the peripheral edge 3^ of the input/output pad 3 is covered with the first layer of insulating film 20, the input/output pad 3 can be applied to a multilayer circuit board arranged close to each other, and the area between the input/output pads can be This has the advantage that insulation is reliably guaranteed.

〔Effect of the invention〕

As explained above, the present invention provides a multilayer circuit board in which a first layer of insulating film is formed also in the input/output pad forming area other than the multilayer wiring part, and the reliability of the connection between the wiring patterns of each conductor layer is improved. It has excellent practical effects, such as high reliability of insulation between the input and output covers and the throat.

[Brief explanation of drawings]

Fig. 1 is a sectional view of the first invention, Fig. 2 is a sectional view of the second invention, Fig. 3 is a sectional view of the conventional example, Fig. 4 is a perspective view of the multilayer circuit board, and Fig. 5 is the conventional example. It is a figure showing the manufacturing process of. In the figure, 1 is a ceramic substrate, 2 is a multilayer wiring part, 3 is an input/output pad, 3A is a peripheral part, 10 is a first layer conductor pattern, 20 is a first layer insulating film, 25 is a catalyst metal, 30 is a 2nd layer conductor pattern, 31 thin film conductor layer, 32 photoresist, 40 2nd layer insulating film, 50 3rd layer conductor pattern, 60 3rd layer insulating film, 70 4th layer The conductive patterns 90 and 90 indicate vias, respectively. Multi-layered? 6. Shaved view of the board. 4. Diagram showing the conventional manufacturing process.

Claims (2)

[Claims] (1) Multilayer wiring section (2
) is provided in the center of a ceramic substrate (1), and input/output pads (3) are arranged on the peripheral surface of the ceramic substrate (1), and the lowermost insulating film (20) A multilayer circuit board characterized in that it is formed by extending to an input/output pad formation area, excluding an output pad (3). (2) Multilayer wiring section in which insulating layers and conductor layers are laminated alternately (2
) is provided in the center of the ceramic substrate (1), and input/output pads (3) are arranged on the surface of the peripheral edge of the ceramic substrate (1). ) to cover
A multilayer circuit board characterized in that a lowermost insulating film (20) is formed extending to an input/output pad forming area.