JPH0326972A - Array tester - Google Patents

Abstract

PURPOSE:To enhance the efficiency of test work by classifying a large number of objects to be measured into some groups and judging the identity of the output data from the respective groups or the representative value thereof. CONSTITUTION:A plurality of objects S100 - S1FF to be measured are classified into some groups and the identities of the output data from the objects S100 - S1FF contained in the respective groups are inspected by the exclusive logical gates B10 - B1F allotted to the respective groups. When the same data is preliminarily written in all of the objects S100 - S1FF to be measured, if the objects S100 - S1FF are normal, outputs showing that the levels of all of input data are same are obtained from the exclusive logical gates B10 - B1F. Therefore, by inspecting the outputs of the exclusive logical gates B10 - B1F and one input thereof, it can be judged whether normal data are outputted from all of the objects S100 - S1FF to be measured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an array tester for determining the quality of a large number of measurement objects.

[Conventional technology] Conventional technology has been used to measure a large number of objects such as memory, etc. A circuit as shown in FIG. 3 is known as an array tester that determines whether the

8300 to S3■ in the figure are, for example, LM bit DRA
The objects to be measured are M, etc., and are arranged in a matrix of n rows and m columns.

To test these measurement objects S 300 to S1,, first, test the measurement objects S 300 to S. ■Write specific data to. And RAS (Row Ad
(dress Strobe) signal to the RAS signal line R
3 to the measuring object S.3. lo. ~83 m m+
C A S (Column
Address Strobe) signal is switched by the CAS switching circuit 3, and the CAS signal lines Cao to C3++ are switched.
A CAS signal is sequentially supplied to the objects to be measured S300 to S3 through + for each row.

In the row where the C A S signal is at a high level, the measurement target s
3oo to S3■ are in refresh mode, and no data is output. On the other hand, in the row where the CAS signal becomes low level in synchronization with the RAS signal, the object to be measured S aoo
Or is S3■ in read mode? The data is read out.

The read data is sent to data output lines D30 to D.
Input to comparators J30 to J1 via 3m,
Here, it is compared with data written in advance on each measurement object. When the CAS signal is switched n times, all measurement objects S
Tests from 300 to S3■ are completed.

[Problems to be Solved by the Invention] In recent years, as the degree of integration of semiconductor integrated circuits has improved, the capacity of semiconductor memories has also been increasing dramatically. In such a large capacity semiconductor memory, the test time is very long, and in some cases it may take nearly an hour.

In this case, in the conventional array tester described above, it is necessary to perform measurements n times by switching the CAS signal, so it takes nearly 10 hours to test a 10-row memory array, for example.

When conducting operational tests under specific stress conditions, where measurements take a long time, the measurement conditions may differ significantly between the start and end of the measurement, reducing the reliability of the measurements. There is a problem. Another problem is that the efficiency of measurement work is extremely low.

On the other hand, if an attempt was made to test all of these measurement objects in parallel, comparators equal to the number of measurement objects would be required, resulting in a problem in that the scale of the determination circuit would increase significantly.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide an array tester capable of measuring many objects to be measured in a short amount of time without increasing the scale of a determination circuit.

[Means for Solving the Problems] The array tester according to the present invention includes a means for simultaneously reading data from a plurality of grouped measurement objects, and a means for reading out data from a plurality of measurement objects in a group. A plurality of exclusive logic gates each check the identity of data read out from all measurement objects included in each group, and output values of these exclusive logic gates and data read out from i measurement objects in each group are checked. From which data are each of the above
+ a determination circuit for determining output data of a fixed object.

[Operation] According to the present invention, a plurality of measurement objects are classified into several groups, and the identity of output data from the measurement objects included in each group is determined by an exclusive logic gate assigned to each group. Verified.

Here, if the same data is written in advance to all the objects to be measured, if the objects to be measured are normal, an output indicating that the levels of all input data are the same is obtained from the exclusive logic gate. On the other hand, if even one abnormal measurement object exists in the group, no such output can be obtained from the exclusive logic gate. Therefore, by verifying the output of the exclusive logic gate and one of its inputs by the judgment circuit, it is possible to determine whether normal data is output from all measurement objects.
It can be determined whether abnormal data is included.

In the present invention, instead of determining the output data of all measurement objects one by one, whether the output data is included in a group? Since all output data in a group is judged from the same -+l of the output data of the fixed object and the representative value (one) of the output data, one judgment circuit is sufficient for each group. Therefore, the scale of the determination circuit will be almost the same as the current scale.

Also, measurements can be done all at once, so
The total measurement time corresponds to the test time of each individual measurement object.

Therefore, a large number of measurement objects can be measured in an extremely short time.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a diagram showing the configuration of an array tester according to a first embodiment of the present invention.

This array tester has IB rows arranged in a matrix! 6 columns, total of 256 measurement objects SIo. ~SIFF
test. The measurement objects 8 100 to SI2 are, for example, semiconductor memories such as 1M bit DRAM.

The RAS signal is commonly given to all the measurement objects SIOO to SIFF via the RAS signal line Ri.

The CAS signal is input to a CAS signal switching circuit 1. The CAS signal switching circuit i switches the CAS signal to CAS
A first mode in which the CAS signal is sequentially output to the signal lines CtO to CIF, and a CAS signal is output to the CAS signal line CI. ~CIF
It also has a second mode in which it outputs data simultaneously. C.A.S.
The signal lines C+o to ClF are connected to the measurement objects S+oo to SIFF in the corresponding rows, respectively.

On the other hand, the objects to be measured S L00 to SIFF in the same column constitute one group, and the output data from the objects to be measured S too to SIPF included in each of these groups is transmitted to the data output lines D+oo to DIFF. The signals are respectively input to external NOR (hereinafter referred to as EX-NOR) gates Blo to BIF via the respective EX-NOR gates. The output signals of these EX-NOR gates Boo to B1p are input to comparators J100 to JIOF via EX-NOR output signal lines E1o to Etp. Also, among the input signals from EX-NOR game Boo to BIF, the data output line D is the representative value.
The data on IOF to DIF+- is sent to converter J.
110 to J IIF.

Next, the operation of the array tester configured as described above will be explained.

First, prior to i'jlll determination, all measurement objects BIao
The same data is written in S and 22. C.A.S.
The switching circuit 1 is set to the second mode and synchronized with the RAS signal to send the CAS signal to all objects to be measured S100 to SIF.
When data is supplied to F all at once, data is read out from these measurement objects S100 to SIFF all at once.

If all the read data is the same data, E
The outputs of the X-NOR gates B10 to BIF become high level. Also, EX-NOR gate BIO to BIF
If there is a low level output of
Measurement objects S txo to S, outputting data to the X-NOR gate Box. It can be seen that at least one of the following is abnormal. Converter J 100 to J xo
v determines the presence or absence of such an abnormality.

On the other hand, when the outputs of the EX-NOR game Bto to BIF are all at high level, the data output signal line 7D
The level of IOF to D +pp is converted to converter J1.
By making the judgments from 10 to J IIF, it is possible to judge whether all the measurement objects SIOO to SIPF are good or bad.

In addition, when determining the quality of only a specific object to be processed, it is sufficient to set the CAS switching circuit 1 to the first mode and supply the CAS signal to the CAS signal line of the specific row to be measured, as in the conventional case. .

According to this embodiment, the converters Jsoo to JII
The number of F is twice that of the conventional one, but the test time is 1/1 of the conventional one.
Since it can be shortened to l6, it is effective enough to compensate for the disadvantage of increasing the scale of the determination circuit.

FIG. 2 is a diagram showing an array tester according to a second embodiment of the present invention.

RAS signal line R2, CAS signal lines C20 to C
2F1CAS switching circuit 2 and measurement object S 200
S2PIJ to RAS signal line R.S2PIJ in FIG. , CAS signal line CI. ~CIF1CA
S switching circuit l and measurement object Slo. ~SIFF
corresponds to

In this example, the measurement target S 200 to 8 2FF
The power of each group is input to exclusive OR (hereinafter referred to as EX-OR) games B20 to B82F. The outputs of these EX-OR gates B20 to B2F are EX-OR gates B20 to B2F.
On/off of the switching circuits W20 to W2F is controlled via OR output signal lines E20 to E2F.

One end of the switching circuits W20 to W2F is connected to the data output signal lines D200 to D2FO, and the other end is connected to the input ends of the comparators J20 to J2F.

In this example, the measuring object S 200 to s
After writing the same data to 2pp, all measurement objects S
200 to 8 When reading data from 2FF, if all output data is the same, EX-OR game -}B2
The outputs of O to 82F become low level, the switching circuits Wsio to W2F are turned on, and the data on the data output signal lines D200 to D2FO are input to the comparators J2o to J2F. This results in
It is possible to determine the quality of the measurement objects S200 to S222.

Moreover, the measurement object S2. . ~8 If even one of the output data of 2FF is different from the others, EX-OR game }
B2. Any one of 82F to 82F becomes high level. This turns the corresponding switching circuit off, and the input of the converter connected thereto becomes high impedance. This indicates that at least one measurement target included in the group is abnormal.

According to this embodiment, exactly the same number of converters as the conventional one,
That is, the same effects as the first embodiment can be achieved without substantially increasing the scale of the determination circuit.

Note that the present invention is not limited to the embodiments described above. For example, in the circuit of Fig. 1, an EX-OR gate may be used instead of the EX-NOR gate, and in the circuit of Fig. 2, an EX-NOR gate may be used instead of the EX-OR gate. Needless to say.

[Effects of the Invention] As described above, according to the present invention, a large number of measurement objects are classified into several groups, and a determination circuit determines the identity of output data from each group and its representative value. Therefore, without increasing the scale of the judgment circuit,
A large number of measurement objects can be tested in a short time.

This improves the efficiency of testing work and makes it possible to test multiple objects under the same conditions.
This has the excellent effect of improving measurement reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an array tester according to a first embodiment of the present invention, FIG. 2 is a block diagram of an array tester according to a second embodiment of the present invention, and FIG. 3 is a block diagram of a conventional array tester. . 1.2,3; CAS switching circuit, S100 to S+
pp + 8200 to S2FF + S300 to S
3wmn: Measurement object, Boo to Btp; EX N
OR gate, B20 to B2F; EX-OR gate, J
100 to JIFF+J20 to JQp*J30 to J0; combiner, W20 to W2F; switching circuit, R1, R2, Ra; RAS signal line,
Cxo~CIF#C20~C 2F+ C 30
to C3n; CAS signal line, D1oo to D IF
F I D200 to D2FF + D30 to D3 data output signal line, E1o to ELF; EX-NO
R output signal line, E20 to E2,; EX-OR output signal line

Claims (1)

[Claims] (1) A means for simultaneously reading data from a plurality of grouped measurement objects, and a means provided corresponding to each group of these plurality of measurement objects, and data read from all measurement objects included in the group. a plurality of exclusive logic gates that respectively check the identity of each object, and output data of each measurement object from the output values of these exclusive logic gates and data read from one measurement object in each group. An array tester comprising: a determination circuit for making a determination.