JPH03269610A - Lsi circuit for interface - Google Patents

Abstract

PURPOSE:To easily form plural compact interfaces with high performance by setting a delay line into an interface LSI circuit for production of plural skew compensated strobe signals and providing the selection circuits. CONSTITUTION:Two types of interfaces are prepared and the interface type selection signals 16 and 17 are supplied from outside. The signal 16 is set at logic 1 in a type 1 and a strobe signal 11 is received by a receiver circuit 1. The output 12 of the circuit 1 is delayed via a delay line 2. The output 13 that secured the skew compensating time needed for the interface of type 1 is outputted to the output 15 by a selection circuit 3, the data bus signal received by a receiver circuit 4 is fetched by a data register 5. At the same time, the signal 17 is set at logic 1 with use of the interface of type 2 and the output 14 of the line 2 that secured the skew compensating time needed for the interface of type 2 is outputted to the output 15 by the circuit 3. Thus a sampling signal of the register 5 is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer interface for an information processing device, and more particularly to an interface LSI circuit using a sampling method for receiving data on the interface.

[Conventional technology]

Conventionally, this type of interface receiving circuit has been configured such that only a plurality of receiver circuits are configured as LSIs, or even when a data register is included, the data is synchronized with an external clock.

[Problem to be solved by the invention]

Conventional LSI circuits for interfaces synchronize with an external clock when they have a built-in data register as described above, so data capture performance is limited by the operating frequency of the LSI, so they are not used for high-speed performance interfaces. I couldn't. In addition, when a data register is not built-in, a delay line must be provided outside the LSI to accommodate higher performance, which increases the number of parts and makes it difficult to downsize.

[Means to solve the problem]

The interface LSI circuit of the present invention includes a data bus signal receiver circuit, a data register ε for holding the output of the receiver circuit, a strobe signal register circuit for sampling data, and an output of the receiver circuit. and a selection circuit that selects the plurality of delay outputs for each type of interface (2. The output of the selection circuit is configured to be supplied as a sampling signal ε to the data register. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 11 is a block diagram inside an LSI according to an embodiment of the present invention. In the figure, 1 is a receiver circuit that receives a strobe signal 11, its output 12 is connected to delay line 2, and outputs 13 and 14 of day l/1 line 2 are inter selectors.
The SFF 411 selection signal 16 and the INTER selection-META 412 selection signal] and 7 are both input to the selection circuit 3. 4 is a receiver circuit for receiving the data bus signal 18, and its output is inputted to the data register 5. Further, the output 5 of the selection circuit 3 is supplied to the data register 5 as a sampling signal ε.

Next, the operation will be explained. In this embodiment, there are two types of interfaces, and the selection signals 16 and 17 for each interface are supplied from the outside.
In the case of
, the output 12 is delayed through the delay line 2, and the output 13 which has undergone the skew compensation time ε required for the type 1 interface is outputted to 15 by the selection circuit 3, and the data bus signal received by the receiver circuit 4 is is taken into the data register 5.

Similarly, when using the type 2 interface, the interface selection-meta 412 selection signal J7 becomes logic "1" and the output 14 of the delay line 2 with the skew compensation time required for the 5 type 2 interface is selected by the circuit 3. 15 and is used as a sampling signal for the data register 5.

〔Effect of the invention〕

As explained above, the present invention brings a delay line into an interface LSI circuit, creates a plurality of bias compensation strobe signals, and provides a selection circuit for each, thereby easily constructing a plurality of interfaces with high efficiency and high performance. be able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 1.4...Receiver circuit, 2...Delay line,
3...Selection circuit, 5...Data register. "Kuma (nichi \-(・pa)

Claims (1)

[Claims] A data bus signal receiver circuit, a data register that holds the output of the receiver circuit, a strobe signal receiver circuit for sampling data, a delay line that delays the output of the receiver circuit, and a plurality of delay outputs thereof. an LSI circuit for an interface, comprising a selection circuit for selecting each type of interface, and an output of the selection circuit is supplied as a sampling signal to the data register.