JPH03268011A - Clock signal supply device - Google Patents

Abstract

PURPOSE:To make a clock skew small in a system of a slave clock supply device independently from a clock skew of the whole device by dividing the clock supply into a master clock supply device and a slave clock supply device, and generating a reference signal by the slave clock supply device. CONSTITUTION:In a master clock supply device 151, only a clock signal and a synchronizing signal are generated. In a slave clock supply device 152, the clock signal and the synchronizing signal from the master clock supply device 151 are received, and in a frequency-dividing circuit 106 in the slave clock supply device 152, the clock signal is frequency-divided, and a reference signal is formed. In such a way, since the reference signal is generated by the slave clock supply device 152, a clock skew can be made small in a system 11 of the slave clock supply device 152, and the device is not influenced by the clock skew of the whole device.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a clock signal supply device, and is particularly used in large-scale computers that process arithmetic operations at high speed. The present invention relates to a lock signal supply device suitable for supplying a signal.

[Conventional technology]

In the conventional device, as described in Japanese Unexamined Patent Publication No. 63-231516, a clock signal and a reference signal are supplied from one clock supply source to a clock phase adjustment device having a clock phase adjustment function.

Also, in Japanese Patent Application No. 199361/1983 filed by the applicant of the present invention, the clock signal, reference signal and synchronization signal are supplied from one source.

[Problem to be solved by the invention]

However, in recent years, in large-scale computers, there has been a tendency to share a plurality of processors into a single device, and the number of processors has also increased, leading to larger scale devices. When a conventional clock supply device is applied to such a large computer, it is necessary to synchronize and supply clocks to each physically large device, even if it is equipped with a phase adjustment function. Therefore, the dispersion in the transmission time of the reference signal increases, and the clock skew of the entire device also increases.

When a processor is used as a system, it is necessary to minimize the signal transmission time within the system. Therefore, it is desirable to minimize clock skew within the system. On the other hand, the signal transmission time between each system does not need to be as small as the signal transmission time within the system, and a method is generally used in which the transmission takes several machine cycles. Therefore, there is no need to reduce the clock skew between systems so much.

However, when the lock signal oscillator in the prior art described above is applied to a large-scale computer such as the one described above, the clock signal is generated from one source.

In order to supply signals such as reference signals and synchronization signals to a plurality of systems, there is a problem in that the clock skew within the system, which should be minimized as much as possible, becomes large due to the influence of the clock skew between the systems.

An object of the present invention is to provide a lock supply device in which clock skew within a system is not affected by clock skew between systems and is minimized as much as possible within the system.

[Means to solve the problem]

In order to achieve the above purpose, each system that distributes clock signals receives a clock signal and a first synchronization signal supplied from one group clock supply device, and creates a reference signal and a second synchronization signal. Equipped with a child clock supply device to
Create a phase comparison signal from the second synchronization signal and the clock signal, compare the phases of the reference signal and the phase comparison signal, and send the phase comparison result to the variable delay circuit that adjusts the phase to adjust the phase of the clock signal. This is how it was done.

[Effect]

A family clock supply device generates only a clock signal and a synchronization signal. The child clock supply device receives the clock signal and synchronization signal from the above-mentioned family clock supply device, divides the frequency of the clock signal by a frequency dividing circuit in the child clock supply device,
Form a reference signal.

When the frequency is divided by the frequency dividing circuit in the child clock supply device, synchronization between the child clock supply devices is performed using a synchronization signal from the family clock supply device. The reference signal and synchronization signal from the child clock supply device and the clock signal from the family clock supply device are sent to the clock signal phase adjustment device. The clock phase adjustment device divides the frequency of the clock signal, performs synchronization using a synchronization signal, and creates a phase-compared signal. The phases of this phase-compared signal and the reference signal are compared, and the phase comparison result is sent to a variable delay circuit that adjusts the phase, thereby adjusting the phase of the clock signal. In this way, since the reference signal is generated by the child clock skew supply device, the clock skew can be reduced within the system of the child clock supply device, and is not affected by the clock skew of the entire device.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

In the device shown in FIG.
1 and the child clock supply system 11, and the family clock supply device 151 and the child clock supply system 12 are connected by signal lines, respectively. and family clock supply device 151
Since the signal lines connecting the child clock supply systems 11 and 12 are long and have different lengths, the phases in the child clock supply systems 11 and 12 are not aligned.

In FIG. 1, the family clock supply device 151 is provided with a clock signal oscillator 104 and a frequency dividing circuit 105. A clock signal oscillator 104 provides a clock signal. The frequency dividing circuit 105 is a clock signal oscillator 104
A synchronization signal is created by receiving the clock signal supplied by the device.

Child clock supply systems 11 and 12 each include a child clock supply device 152 and a plurality of phase adjustment devices 153.

The slave clock supply device 152 includes a reference signal frequency dividing circuit 106.
A synchronizing signal frequency dividing circuit 107 is provided. Reference signal dividing port #! r106 is a reference circuit which divides the frequency of the clock signal supplied from the clock oscillator 104 and a synchronization signal created by dividing the clock signal from the clock oscillator 104 by the frequency dividing circuit 105, and supplies the divided signal to the phase adjustment device 153. Create a signal. The synchronization signal frequency dividing circuit 107 divides the frequency of the clock signal supplied from the clock oscillator 104 and the synchronization signal created by dividing the clock signal from the clock oscillator 104 by the frequency division circuit 105, and divides the frequency of the clock signal from the clock signal from the clock oscillator 104 into a phase adjustment device. 153 is created.

The phase adjustment device 153 is provided with a variable delay circuit 101, a phase comparison circuit 102, and a frequency division circuit 103. The variable delay port 1% 101 controls the delay time of the clock signal supplied from the clock oscillator 104. Phase comparison circuit 1
02 compares the reference signal supplied from the reference signal frequency dividing circuit 106 and the phase comparison signal supplied from the frequency dividing circuit 103. The frequency dividing circuit 103 divides the frequency of the clock signal from the variable delay circuit 101 and the synchronization signal supplied from the synchronization signal frequency division circuit 107 to create a phase comparison signal to be supplied to the phase comparison circuit 102. The operation of the circuit shown in FIG. 1 will be explained. The clock signal generated by the clock oscillator 104 is supplied to a frequency divider circuit 105 for generating a synchronization signal, and is also distributed to child clock supply devices 152 in the system 11.12. It is not necessary for this clock signal to accurately match the signal propagation time to each distribution destination. The frequency dividing circuit 105 divides the frequency of the clock signal supplied from the clock oscillator 104 to create a synchronizing signal, and
It is distributed to child clock supply devices 152 within 1 and 12.

This synchronization signal needs to have the same signal transmission time to the child clock supply devices in the systems 11 and 12, but since it has a longer period than the clock signal supplied from the clock oscillator 104, attenuation is unlikely to occur.

Next, in the child clock supply device 152, the clock oscillator 1
The clock signal supplied from 04 is input to the reference signal frequency dividing circuit 106 for creating a reference signal and the synchronous signal frequency dividing circuit 107 for creating a synchronizing signal, and is distributed to each phase adjustment device [153]. . This clock signal also does not need to have exactly the same signal transmission time to each phase adjustment device 153.

The reference signal is generated by the reference signal frequency dividing circuit 106 by dividing the clock signal from the clock oscillator 104 and the synchronization signal from the family clock supply device 151, and distributed to each phase adjustment device W153.

This reference signal serves as a reference for phase matching, and it is necessary to accurately align signal transmission times from the reference signal frequency dividing circuit 106 to each phase adjustment device 153.

Similarly, in the synchronization signal valve rotation 1107, a synchronization signal for synchronizing with the reference signal is created, and each phase adjustment device 153
distribute to. This synchronization signal is also applied to the synchronization signal frequency dividing circuit 107.
A clock signal from each phase adjustment device 153 is input to the variable delay circuit 101, and its phase is adjusted by a predetermined phase amount, which will be described later. The variable delay circuit 101 is input to the frequency divider circuit 103, and is input to the child clock supply device 15.
The frequency is divided in synchronization with the synchronization signal created by the synchronization signal frequency division circuit 107 in the second circuit. This frequency-divided signal is a phase comparison signal, and is input to the phase comparison circuit 102 for phase comparison with the reference signal created by the reference signal frequency division circuit 106 in the child clock supply device 152. The phase comparison circuit 102 compares the phases of the phase comparison signal and the reference signal, and calculates only the amount of phase necessary to match the phases of the two signals.
A control signal for delaying the phase of the clock signal is fed back to the variable delay circuit 101. The phase-adjusted signal (output signal of the variable delay circuit 101) is transmitted to each logic LS.
It is distributed and used by I.

Phase adjustment is performed as described above,
The clock skew within the system 11 of the child clock supply device is
Since it is determined by the dispersion of the transmission time of the reference signal from the reference signal frequency dividing circuit 106 to each phase adjustment device 153, the difference between the parent clock supply device w151 and the child clock supply device 1
It has nothing to do with variations in transmission time of synchronization signals up to 52.

The clock skew between the systems 11 and 12 in FIG.
This is the sum of the variation in the transmission time of the synchronization signal between the two, and the variation in the transmission time of the reference signal between the child clock supply device 152 and the phase adjustment device 153, which is not as bad as in the system, but
As mentioned above, it is common that a large amount of clock skew is not required between systems.

FIG. 2 shows another embodiment of the invention. FIG. 2 shows an example of application of the present invention to a device in which a system 11 whose clock skew must be reduced and a system 31 whose clock skew does not need to be so small coexist. System 31, in which the clock skew does not need to be very small, is
For example, devices such as a main storage device, a service processor, etc. that require a slow machine cycle. For these devices, for synchronization purposes, it is common to use a machine cycle that is one times the cycle of the processor's machine cycle.

In FIG. 2, the same symbols as in FIG. 1 indicate the same devices or circuits. The frequency divider circuit 301 receives a clock signal supplied from the clock oscillator 104 and creates a timing signal used in the system 31 whose machine cycle is slow. The amplifier circuit 302 amplifies the timing signal used in the system 31 whose machine cycle is slow.

As mentioned before, the system 31 with a slow machine cycle does not need the phase adjustment device 153 because the clock skew does not need to be very small. The timing signal used in the system 31 is generated by the parent clock supply device 151, but the reference signal for the system 11 is generated by the child clock supply device 152. Therefore, the clock skew within the system 11 is equal to the clock skew of the entire device. can be made smaller independently.

Although the clock skew between the system 31 and the system 11 is large, as described above, a significant clock skew is not required between the systems.

〔Effect of the invention〕

As described above, according to the present invention, clock supply is divided into a parent clock supply device and a child clock supply device, and a reference signal is generated by the child clock supply device, so that the clock skew is generated within the system of the child clock supply device. This has the effect of being able to reduce the clock skew of the entire device independently.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a clock supply device according to one embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of a clock supply device according to another embodiment of the present invention. 101...Variable delay circuit, 1o2...Phase comparison circuit. 103... Frequency dividing circuit. 104... Clock oscillator, 105... Branch circuit. 106...Reference signal frequency dividing circuit. 107... Synchronous signal frequency dividing circuit. 151... Parent clock supply device. 152... Child clock supply device. 153...Phase adjustment device. 11.12... Child clock supply system.

Claims (1)

[Scope of Claims] 1. In an electronic computer comprising a first clock signal supply means and a plurality of systems to which a first clock signal from the first clock signal supply means is distributed, the first The clock signal supply means includes a clock oscillator that oscillates the first clock signal, and a first synchronization signal forming means that divides the frequency of the first clock signal to form a first synchronization signal, Each of the systems receives the first clock signal and the first synchronization signal, divides the frequency of the first clock signal, and generates a reference signal for adjusting the phase of the first clock signal. a reference signal forming means for forming a reference signal; and a second synchronizing signal forming means for receiving the first clock signal and the first synchronizing signal, dividing the frequency of the first clock signal and forming a second synchronizing signal. further comprising a variable delay means for outputting a second clock signal obtained by delaying the first clock signal by a time specified by a control signal; a phase comparison signal forming means for dividing the frequency of the signal and the second synchronization signal to output a phase comparison signal; and a phase comparison signal forming means for outputting the control signal by comparing the phases of the phase comparison signal and the reference signal. 1. A clock signal supply device comprising a phase adjustment means comprising a comparison means. 2. In the clock signal supply device according to claim 1, the clock signal may be directly supplied from the first clock signal supply means to a signal transmission system that does not require high clock skew accuracy. A clock signal supply device characterized by: