JPH03267821A - Manchester code decoder circuit - Google Patents

Abstract

PURPOSE:To attain normal decoding even when the phase of a clock is shifted or a Manchester code rule is in error by selecting a clock unable to be subject to N-stage protection depending on the relation between a biphase clock and a change point of a Manchester code data. CONSTITUTION:A biphase clock generating circuit section 1, a change point detection pulse generating section 6, 1st, 2nd clock N-stage protection sections 2, 3, a clock selection section 4 and a latch circuit 5 are provided to the decoder circuit, a clock for Manchester code data is converted into two clocks, a pulse going to one logic level is generated at the back side of a change point by two clocks and the Manchester code data and a clock unable to be in N-stage latch protection is selected depending on the relation of the pulse and both the clocks. The Manchester code data is latched and decoded into the NRZ code. Thus, even when the phase of the clock is shifted and the Manchester code rule is in error, the change point is deviated and normal decoding is implemented.

Description

[Detailed Description of the Invention] [Summary] Regarding a Manchester code decoder circuit, in particular, for example, LA
Regarding the circuit that decodes Manchester code data used in N (Local Area Network) into NRZ code data, we provide a Manchester code decoder circuit that can perform normal decoding even if the phase of the clock RCLK is shifted or the Manchester code rule is wrong. A two-phase clock generation unit that generates first and second two-phase clocks that are distributed one clock each from clocks supplied from an external source for Manchester code data, and and the Manchester code data, and generates an output pulse that always becomes one logic level after the change point of the Manchester code data; A first and second clock N-stage protection unit which inputs first and second two-phase clocks, respectively, when the output pulse latched by each clock maintains the same logic level for N clock stages, The second clock or the first clock is selected depending on the one that generates the corresponding protection completion output and the output of the first or second clock N-stage protection unit that enters the N-stage protection state earlier. and a latch circuit that latches Manchester code data supplied from the outside and generates NRZ code data using the clock selected by the clock selector.

[Industrial application field]

The present invention relates to a Manchester code decoder circuit, and more particularly to a circuit for decoding Manchester code data used in, for example, a LAN (Local Area Network) into NRZ code data.

In recent years, a large number of workstations and personal computers have been introduced, and these are now being replaced by C3MA/CD.
(carrier 5ense multip
le access withollision
A device has been developed that connects with a LAN (detection) method and performs mutual data communication.

FIG. 6 is a diagram showing a frame format used in such a CSMA/CD type LAN.

In the figure, rPRJ is the preamble part, and is a 7-byte synchronization sequence pattern ("1") for synchronization.
and a repeating pattern of "0").

rSFD is a start frame delimiter section, which is composed of a 1-byte special data pattern indicating that a frame has started. "D^" is a destination address field, which is composed of a 6-byte destination address that specifies the station to which data is to be sent.

"S^" is the source address part, which is composed of a 6-byte source address indicating the source. rDAT^”
is the data portion, which is variable transmission data in the range of 48 to 1500 bytes. rFCS is a frame check sequence section, which is composed of a 4-byte error detection code (CRC code) for detecting errors. In such a C3MA/CD frame format, a Manchester code is used as a code on a transmission path. Manchester code refers to the change point of the rising edge (0, 1) or falling edge (1, O) of a signal as "1" or "0", respectively.
This is known as one of the binary signal methods that improves the bit error rate in response to

Therefore, it is necessary to take in the Manchester code on the transmission path and convert it to an NRZ code so that it can be processed by internal circuits. For this purpose, it is necessary to provide a Manchester code decoder circuit at each station connected to the LAN. It has become.

[Conventional technology]

FIG. 7 shows an example of such a conventional Manchester code decoder circuit. In the figure, a D-type flip-flop (hereinafter simply referred to as a flip-flop) 5
0 is for dividing the clock RCLK sent from the transmission line into half the frequency. The output 5CLK of the flip-flop 50 is supplied to the clock input terminal CK of the flip-flop 51. Manchester code data RDATA sent from the transmission line is input to the data input terminal of the flip-flop 51. Then, it is latched at the clock 5CLK, and the NRZ code data SD
Output as ^T^. Note that the signal XRST in the figure is a reset signal that sets the flip-flops 5o and 51 to the initial state.

FIG. 8 is an immersion chart for explaining the operation of the above circuit. Figure (a) shows, for example, a 20 MHz clock RCLK sent from the transmission line, and figure (b)
) is sent from the transmission path, for example, to Manchester code data RO in which rlJ and OJ alternate.The transmission clock RCLK is divided by the flip-flop 50 into the IOMH2 clock 5CLK shown in FIG. and is supplied as a latch pulse to the clock input terminal CK of the flip-flop 51.Then, this clock S
Manchester code data RDA at the rising edge of CL
Latch the latter half of T^ and turn it into NR as shown in the same figure (d).
Output as Z code data 5flAT^.

[Problem to be solved by the invention]

However, in the Manchester code decoder circuit having the above configuration, if the phase of the clock RCLK deviates due to the initial state or disturbance, or if the coding rule of the Manchester code data RDAT^ is incorrect due to some kind of failure, the Manchester code decoder circuit uses the deviated clock to generate the Manchester code. In the example shown in Fig. 7, N is used to alternating "1" and "0" in order to eliminate data or Manchester code data with an incorrect code rule.
This has the disadvantage that it does not become RZ code data 5DAT^ and cannot be decoded normally.

Therefore, the present invention has been made in order to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a Manchester code decoder circuit that can perform normal decoding even if the clock RCLK is out of phase or the Manchester code rule is incorrect. shall be.

[Means to solve the problem]

In order to achieve the above object, the Manchester code decoder circuit according to the present invention, as shown in principle in FIG. second 2
A two-phase clock generation unit 1 that generates a phase clock receives the two-phase clocks and the Manchester code data, and generates an output pulse that always becomes one logic level after the change point of the Manchester code data. A change point detection pulse generator 6, and first and second pulse generators that receive the output pulse of the pulse generator 6 and the first and second two-phase clocks, respectively.
N-stage clock protection units 2 and 3 which generate a corresponding protection completion output when the output pulse latched by each clock maintains the same logic level for the stages of the clock; a clock selection unit 4 that selects the second or first clock, respectively, according to the output of the first or second clock N-stage protection unit 2.3 that enters the N-stage protection state; and the clock selection unit 4, the latch circuit 5 latches Manchester code data supplied from the outside to generate NR2 code data.

[Operation] The operation of the invention shown in FIG. 1 will be explained below with reference to the timing chart shown in FIG. 2.

First, the clock RCLK shown in FIG. 2(a) is a clock for Manchester encoded data RDATA (FIG. 2(b)), and the first and second clocks are distributed one clock each by the two-phase clock generator 1. 2-phase clock PO3, P
These first and second two-phase clocks PO3 and PO4 are converted into O4 ((e) and (f) in the same figure). Manchester code data RD is input from these input signals.
An output pulse PO7 is generated which always becomes one logic level after a point of change that normally exists in one bit of ATA.

In the first clock N-stage protection unit 2, this output pulse PO
7 and, for example, a first clock PO3, the output pulse PO7 is latched by the clock PO3, and when the latch result holds the same logic level as the clock N, a protection completion output P14 is generated.

This is similarly performed between the output pulse PO7 and the clock PO4 in the second clock N-stage protection section 3, but in the illustrated example, the protection section 2 generates the protection completion output P14. That is, since the clocks PO3 and PO4 exist before or after the change point of the Manchester code data RDAT^, based on these clocks, N stages are always applied to the output pulse PO7 which always becomes one logic level after the change point. The clock PO3 that exists before the change point can be protected by a clock latch, and the clock PO4 that exists after the change point cannot be protected by N-stage clock latch protection.

However, in this case, it has become clear that output pulses PO7 and PO4 exist after the change point, so selecting clock PO4 will prevent data latch errors from occurring.

Therefore, the clock selection unit 4 receives the N-stage clock/latch protection output P14 and selects the clock P that does not correspond to the N-stage clock/latch protection output P14.
By selecting O4 and applying it to the latch circuit 5, NRZ
Code data 5DAT^ can be decoded without error.

〔Example〕

FIG. 3 shows an embodiment of the Manchester code decoding circuit according to the present invention shown in FIG. In addition,
In this embodiment, a case of two-stage protection is shown as the N-stage protection sections 2 and 3.

The two-phase clock generation section 1 is composed of an inverter 11, a flip-flop 12, and AND gates 13 and 14, and includes, for example, a 20 MH clock supplied from an external transmission line.
The clock RCLK of z is supplied to the clock input terminal of the flip-flop 12 via the inverter 11, and also to one input of each AND gate 13 and 14.

The inverted output signal PO2 of the flip-flop 12 is inputted to the data input terminal of the flip-flop 12, so that whenever the output of the inverter 11 changes in the rising edge, its frequency divided by two is output POI, PO2. is reversed (see (C) and (d) in Figures 4 and 5).
.

Then, the normal output signal PO of the flip-flop 12
I is supplied to the AND gate 13, the inverted output signal PO2 is supplied to the other input of the AND gate 14, and AN
The outputs of the D gates 13 and 14 are as shown in FIG. 4(e) and (
As shown in f), two-phase clocks PO3 and PO4 are obtained in which every other pulse corresponding to the clock RCLK appears in the state thereafter.

The change point detection pulse generator 6 includes a flip-flop 616.
2 and exclusive OR (hereinafter referred to as rEOR).

(abbreviated as ) gate 63, and both flip-flops 6
Manchester code data RDAT^ from outside is commonly input to the data input terminal of 1.62, but AN
The clock PO3 from the D gate 13 is given to the flip-flop 61, and the clock PO4 from the AND gate 14 is given to the flip-flop 62.
Output pulse PO7 is generated from R gate 63.

The clock N-stage protection unit 2 includes flip-flops 22 and 23.
, 24, an EOR gate 63, an AND gate) 26, 27, and an OR gate 28. Each clock input terminal of the flip-flops 22, 23, and 24 has an AN
The output PO3 of the D gate 13 is supplied.

Then, the output PO7 obtained by exclusive ORing in the FOR gate 63 is supplied to the data input terminal of the flip-flop 22, and the output PO8 of the flip-flop 22 is supplied to the data input terminal of the flip-flop 23 and one of the AND gates 26. is fed to the input of

The output P10 of the flip-flop 23 is supplied to the other input of the AND gate 26, and the ANDed output P12 is supplied to one input of the OR gate 28.

The output P14 of the flip-flop 24 is supplied to the other input of the OR gate 28, and the output is sent to the flip-flop 24 via the AND gate 27.
The flip-flop 24 maintains the once set state by being supplied to the data input terminal of the flip-flop 24.

Note that the other input of the AND gate 27 is supplied with the inverted output of a flip-flop 34 of the clock N-stage protection unit 3, which will be described later. When set, the other flip-flop is prevented from setting.

In the above configuration, the flip-flops 22 and 23 realize two-stage protection of the clock latch.

The clock N-stage protection unit 3 has substantially the same configuration as the clock N-stage protection unit 2 described above. That is, flip-flops 32, 33, 34, AND game) 35, 36, and OR
It consists of a gate 37 and a flip-flop 3.
The output PO4 of the AND gate 14 is supplied to each clock input terminal of 2.33.34.

The output PO7 of the EOR gate 63 is supplied to the data input terminal of the flip-flop 32, and the output PO9 of the flip-flop 32 is supplied to the flip-flop 33 and the AN
It is supplied to one input of the D gate 35.

The output pH of the flip-flop 33 is supplied to the other input of this AND gate 35, and the logical product output P
13 is supplied to one input of the OR gate 37.

The output P15 of the flip-flop 34 is supplied to the other input of the OR gate 37, and the output is sent to the flip-flop 34 via the AND gate 36.
, the flip-flop 34 maintains the once set state.

It should be noted that the other input of the AND gate 36 is supplied with the inverted output of the flip-flop 24 of the N-stage clock protection section 2 described above, so that the output of the flip-flop 24 or 34 as described above is supplied. If either flip-flop is set first, the other flip-flop is prevented from being set.

In the clock selection section 4, a selector is configured by AND gates 41, 42 and an OR gate 43.

The flip-flop 24 of the clock N-stage protection unit 2
When is set, the signal PO4 is selected, and when the flip-flop 34 of the clock N-stage protection section 3 is set, the signal PO3 is selected and output as the latch clock 5CLK of the flip-flop 5. Then, the flip 70 knob 5 hits the Manchester code data RDAT^ with this latch clock 5CLK and outputs the NRZ code data 5.
Output as DATA.

Next, the operation of the above configuration will be explained with reference to the timing charts of FIGS. 4 and 5.

FIG. 4 shows the operation timing under normal conditions, that is, when there is no phase shift or error in the Manchester code rule. That is, when the Manchester encoded data RDAT^ is hit by the flip-flop 61 and the flip-flop 162 using the two clocks PO3 and PO4 generated by the two-phase clock generator 1, the results are shown in FIGS. 4(g) and (h).
) signals PO5 and PO6 are obtained. This signal PO
When the EOR gate 63 performs an exclusive OR on 5 and PO8, the signal PO7 shown in FIG. 5(i) is obtained.

This signal PO7 has the following meaning. In Manchester code, there is always a changing point within one bit, so the exclusive logic of the value struck before the changing point and the value struck after the changing point. When the sum is taken, the value will always be at H level after the point of change in Manchester code data. Therefore, by reaching this H level, it can be known that there has been a change point.

In other words, the output signal PO7 of the EOR gate 63 is transferred to the clock N-stage protection unit 2 using the two-phase clocks PO3 and PO4.
The signals PO8 and PO9 shown in FIG.

At this time, the signal PO8 becomes H level, which means that
This means that there was a change point before the clock PO3, and the signal PO9 remains at the L6 level, meaning that the previous change point has reached the clock PO4.

The signals PO8 and PO9 are sent to the next stage flip-flop 72.
3 and 33, and as shown in <1> and (m) of the figure, the signals PIO and pH are output, and the flip-flops 22 and 32 latch the next data RDATA.

As a result, the AND gates 26 and 35 output the H-level signal P12, respectively, as shown in (n) and (o) of the figure.
and outputs an L level signal P13.

Here, outputting an H level signal means that two consecutive change points can be detected and two-stage protection is achieved.

Next, the signal P12 is the OR gate 28 and the AND gate 27.
is supplied to the data input terminal of the flip-flop 24 via the clock PO3, and the flip-flop 24 is set at the next clock PO3, and as shown in FIG.
14, and the signal P13 remains at the L level, so the flip-flop 3 is output as shown in the figure (q>).
4 is never set, and the signal P15 remains at the L level.

Thereafter, the set/reset states of the flip-flops 24 and 34 do not change because their inverted outputs are input to the AND gate 27.36. In this embodiment, the set/reset states of the flip-flops 24 and 34 do not change. As described above, it goes without saying that the flip-flop 34 may be set to the contrary depending on the states of the clock RCLK and the data RDAT^.

The clock PO3, which has been given two-stage protection in this way, is locked in the clock selection unit 4 by resetting the flip-flop 34, while the clock PO4 is changed to the clock SCL by setting the flip-flop 24. (see Figure 3 (r>)).

Here, the reason why the clock PO4 on the opposite side is used instead of the clock PO3 that has been protected in two stages is because the clock PO3
, PO4 of the EOR gate 63 can be latched at H level by the output pulse P.
O7 is the clock PO3 on the opposite side of the change point,
Therefore, in order to avoid latching near the change point, it is necessary to have the clock PO4 on the same side as the output pulse PO7.

A clock 5CLK having the same phase as the clock PO4 selected in this way is supplied to the flip-flop 5.
By latching Manchester code data RO^T^ with CLK, NRZ code data 5DAT^ can be obtained as shown in FIG. 4(s).

In the above embodiment, 3 bits of data are lost due to two-stage protection, but the data protection described above is based on C
Since this is performed using the synchronization sequence (7 bytes) of the preamble part of the SMA/CD frame format, significant data after the start frame delimiter (5FI) is not affected.

Section 5 shows the operation timing when there is an abnormality, that is, when invalid data occurs at the beginning of the preamble section (PR).The operation of each section is the same as described above, so a detailed explanation will be provided. Although omitted, in this case, the signals PO5 and PO6 change as shown in (g) of the same figure.
The signal PO7, which is the exclusive OR of these signals, is used as the clock F.
Clock P by hitting '03 and PO4 respectively.
Since there is a Manchester code change point before O4, signal PO8 maintains the H level, and this is maintained until signal PIO.
Since stage protection is provided, even if illegal data occurs, the illegal data part is excluded and two-stage protection is performed, so that Manchester code data can be normally decoded into NRZ code data.

Note that since the C3MA/CD method is a burst communication in the above-described operation, data protection is performed in the array part (Pl'l) every time a packet is sent.

Also, the above actual Il! In the example, we have explained the case where two-stage protection is performed, but the invention is not limited to this, and the configuration can be configured to perform arbitrary N stages of protection within the range of bits that can be dropped in the preamble section (7 bytes). Of course, it is okay to do so. In this case, an appropriate latch clock can be selected more reliably, and accurate decoding becomes possible.

〔Effect of the invention〕

As described above, according to the Manchester code decoder circuit of the present invention, the clock for Manchester code data is converted into two clocks distributed one by one, and these two clocks and the Manchester code data are always placed one after the change point. Generates a pulse with a logic level of
Since it is configured to decode into a code, even if the clock phase is shifted or the Manchester code rule is wrong, decoding can be performed normally by shifting from the change point.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining the principle of the Manchester code decoder circuit according to the present invention, FIG. 2 is a timing chart for explaining the operating principle of the present invention, and FIG. 3 is a detailed explanation of the present invention. FIG. 4 and FIG. 5 are timing charts for explaining the operation of the embodiment. FIG. 6 is a diagram showing a frame format used in a C8MA/CD type LAN. FIG. 7 is a diagram showing a conventional Manchester code. In the diagram showing an example of a decoder circuit, 1... 2-phase clock generation unit, 2. 3... N clock stage protection unit, 4... Clock selection unit, 5... Latch (flip-flop). Circuit 6... Changing point detection pulse generation section. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A two-phase clock generation unit (1) that generates first and second two-phase clocks that are distributed one clock each from clocks supplied from the outside for Manchester code data; a change point detection pulse generator (6) that inputs a clock and the Manchester code data and generates an output pulse that always becomes one logic level after the change point of the Manchester code data; and the pulse generator (6). ) and the first and second two-phase clocks are input to the first and second clock N-stage protection units (2) and (3), respectively, and the output pulses latched by each clock are One that generates a corresponding protection completion output when the same logic level is maintained for N clock stages, and one that generates the protection completion output corresponding to the same logic level for N clock stages.
Depending on the output of the device that has entered the stage protection state, the corresponding second
or a clock selection section (4) that selects the first clock, and the clock selected by the clock selection section (4),
A Manchester code decoder circuit comprising: a latch circuit (5) that latches Manchester code data supplied from the outside to generate NRZ code data.