JPH032676A - Full-wave rectifier circuit - Google Patents

Full-wave rectifier circuit

Info

Publication number
JPH032676A
JPH032676A JP13793289A JP13793289A JPH032676A JP H032676 A JPH032676 A JP H032676A JP 13793289 A JP13793289 A JP 13793289A JP 13793289 A JP13793289 A JP 13793289A JP H032676 A JPH032676 A JP H032676A
Authority
JP
Japan
Prior art keywords
full
output transistor
emitter
vbe
differential pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13793289A
Other languages
Japanese (ja)
Inventor
Ryuichi Sakano
坂野 竜一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13793289A priority Critical patent/JPH032676A/en
Publication of JPH032676A publication Critical patent/JPH032676A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a full-wave rectifier circuit with a high accuracy by including two differential couples for performing a half-wave rectification and an emitter coupling circuit for adding a half-wave rectification waveform thereof. CONSTITUTION:A signal is inputted at points (p) and (g) from a signal source Vin 1 through C1 and C2 of a capacitance element 3 and when voltages at the points (p) and (g) are set at Vp and a Vg, the Vp and Vg give waveforms of an opposite phase. Then, when signals at the points (r) and (s) are Vr>Vs (initial half cycle) with an emitter coupling circuit by Q5 and Q6 of an output transistor 11, the Q5 of the output transistor 11 is turned On and the Q6 thereof turned OFF. When VOUT = Vr-VBE = Vp->VBE, Vs>Vr (subsequent half cycle), the Q5 of the output transistor 11 is turned ON and the Q6 thereof is turned OFF and VOUT = Vs-VBE = Vg-<VBE to present a full-wave rectification waveform as indicated by VOUT is produced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明け、半導体集積回路に使用される全\ 、暇  波簀流回路に関するものである。[Detailed description of the invention] [Industrial application field] With this invention, all the materials used in semiconductor integrated circuits , concerning the leisure wave current circuit.

〆 〔従来の技術〕 第3図は従来の全波整流回路を示す回路図であり、図に
おいて田は信号源Vi n 、 121 I/′i直流
電圧源、131#’!信号源Vln Illの交流成分
を通す為の容量素子、(41はそれそのコレクタ、エミ
ッタが接続され、差動対をなす入力トランジスタ、・5
)に入力トランジスタ(41のQ7e Qaのベース端
子に直流電圧を供給する抵抗素子、(61は入力トラン
ジスタ(41による差動対のコレクタとこの回路の電圧
源人力Q51との間に接続された抵抗素子、+71#j
入カトランジスタ14)による差動対のエミッタと接地
の間に接続された抵抗素子、+81#−fベースが入力
トランジスタ14)による差動対のコレクタに接続され
た出力トランジスタ、+91H出力トランジスタ(8)
のエミッタに接続された定電流源スである。
[Prior Art] Fig. 3 is a circuit diagram showing a conventional full-wave rectifier circuit. A capacitive element for passing the alternating current component of the signal source Vln Ill (41 is an input transistor whose collector and emitter are connected to form a differential pair, 5
) is a resistance element that supplies DC voltage to the base terminal of the input transistor (41 Q7e Qa), (61 is a resistor connected between the collector of the differential pair by the input transistor (41 and the voltage source Q51 of this circuit) Element, +71#j
A resistor element connected between the emitter of the differential pair by the input transistor 14) and ground, an output transistor whose base is connected to the collector of the differential pair by the input transistor 14), a +91H output transistor (8 )
A constant current source connected to the emitter of

次に動作について説明する。第4図(&)〜(flは第
3図の全波整流回路における各点の波形を示す波形図で
ある。第3図に示すχ点及びy点には信号源Via I
llより、容量素子+31 as、a4に介して信号が
入り、χ点及びy点の電圧をそれぞれyz、v、とする
とき、vz 、 vyは第4図(a、+ 、 (blに
不すごとく逆相の波形となる。
Next, the operation will be explained. FIG. 4 (&) to (fl are waveform diagrams showing waveforms at each point in the full-wave rectifier circuit in FIG. 3. At points χ and y shown in FIG. 3, signal sources Via I
When a signal enters from ll through the capacitive elements +31 as and a4, and the voltages at the χ point and y point are yz and v, respectively, vz and vy are expressed as shown in Figure 4 (a, +, (bl)). The waveform is of opposite phase.

Vχ>Vy(最初の半周期)の場合、入力トランジスタ
)41のQlがON 、入力トランジスタ(4)のQa
がOFFとなり、抵抗素子161 Ra及び抵抗素子(
7)R7f流れる電流をそれぞれ工6.エフ、入力トラ
ンジスタ(41のベース、エミッタ間電圧iVmaとす
るとき 工6.エフは Vχ −VBI 工6 !エフ − 丘) また第8図に示す2点の電圧f?!:V*、電圧源人力
Q51に加わる電圧をVaa 、出力電圧をVOUTと
するとき Vz 、 vQσTは となる。
When Vχ>Vy (first half cycle), Ql of input transistor (41) is ON, Qa of input transistor (4)
is turned OFF, and the resistance element 161 Ra and the resistance element (
7) Adjust the current flowing through R7f, respectively.6. F, input transistor (41 base-emitter voltage iVma, then 6.F is Vχ -VBI 6!F-hill) Also, the voltage f at the two points shown in Fig. 8? ! :V*, when the voltage applied to the voltage source Q51 is Vaa, and the output voltage is VOUT, Vz and vQσT are as follows.

V、>Vχ (次の半周期)の場合入力トランジスタ1
4)のQaがON、入力トランジスタ(4)のQlがO
FFとなり Y−VBz 工6虐エフm11−−−−− Vz 、Vot+r は VzmVcc−工a F6− Vcc −−(Vr−V
BE )従ってVOI7Tは第4図(f+のように全波
整流された波形となる。またlI6.エフ%7zの波形
はそれぞれ第4図+cg 、 tol + telに示
すごとくである。
If V, > Vχ (next half cycle) then input transistor 1
Qa of 4) is ON, Ql of input transistor (4) is O
FF becomes Y-VBz Engineering 6 brutal F m11-----Vz, Vot+r is VzmVcc- Engineering a F6- Vcc --(Vr-V
BE) Therefore, VOI7T has a full-wave rectified waveform as shown in FIG. 4(f+).The waveforms of lI6.F%7z are as shown in FIG.

なお第4図に示す’17biaeは直流電圧源(2)の
電圧である。
Note that '17biae shown in FIG. 4 is the voltage of the DC voltage source (2).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の全波整流(ロ)路は以上のように構成されている
ので抵抗比のバラツキにより出力振幅が変化するなどの
問題点があった。
Since the conventional full-wave rectifier (b) path is constructed as described above, it has had problems such as variations in the output amplitude due to variations in the resistance ratio.

この発明は上記のような問題点を解消するためになされ
たもので、高精度の全波整流回路?得ることを目的とす
る。
This invention was made to solve the above problems, and is a high-precision full-wave rectifier circuit. The purpose is to obtain.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る全波整流回路は、半波整流を行なう2組
の差動対と、この半波整流波形を加算するエミッタ結合
回路を具備したものである。
A full-wave rectifier circuit according to the present invention includes two differential pairs that perform half-wave rectification and an emitter coupling circuit that adds the half-wave rectified waveforms.

〔作用〕[Effect]

この発明における全波!fi回路は、2組の差動対によ
りそれぞれ半波整流された半波整流波をエミッタ結合回
路により加算し全波整流波形として出力する。
Full wave in this invention! The fi circuit adds half-wave rectified waves that have been half-wave rectified by two differential pairs using an emitter coupling circuit, and outputs the sum as a full-wave rectified waveform.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図は全波整流回路の回路図である。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram of a full-wave rectifier circuit.

図において111〜(41は第8図の従来例に示したも
のと同等であるので説明を省略する。
In the figure, 111 to (41) are the same as those shown in the conventional example of FIG. 8, so their explanation will be omitted.

tlol i人力トランジスタ14)のQl、Q、2に
よる第1の差動対及び入力トランジスタ(41のQ、3
 、 Qaによる第2の差動対のトランジスタのベース
端子にそれぞれ直流電圧を供給する為の抵抗素子、αυ
は人力トランジスタ141のQl、Q2による第1の差
動対及び入力トランジスタ14)のQ3.Q4VCよる
@2の差動対のエミッタにそれぞれベースが接続され、
エミッタ結合された出力トランジスタ、 +121は入
力トランジスタ141のQl、Q2VCよる第1の差動
対のエミッタ端子に接続された定電流源n、031は入
力トランジスタ14)のQ3.QaVCよる第2の差動
対のエミッタ端子に接続された定電流源工2、a41r
a出力トランジスタα刀のQ5 、 Qaのエミッタに
接続された定電流源工3である。
tlol i The first differential pair with Ql, Q, 2 of the human-powered transistor 14) and the input transistor (Q, 3 of 41)
, a resistance element for supplying DC voltage to the base terminals of the transistors of the second differential pair by Qa, αυ
Q1, Q2 of the human-powered transistor 141 and the first differential pair Q3 of the input transistor 14). The base is connected to the emitter of @2 differential pair by Q4VC,
Emitter-coupled output transistors, +121 are constant current sources n connected to the emitter terminals of the first differential pair by Q1, Q2VC, and Q3. Constant current source 2 connected to the emitter terminal of the second differential pair by QaVC, a41r
This is a constant current source 3 connected to the emitters of Q5 and Qa of the output transistor α.

次に動作について説明する。第2図(8L1〜telは
第1図の全波整流回路における各点の波形?示す波形図
である。第1図に示すp点及びg点には信号源Vin 
Illより、容量素子(3)のOx、C!2を介して信
号が入り、p点及びg点の電圧をそれぞ;/’t Vp
 、vgとfるときVp 、 vgは第2図fat 、
 iJに示すととく逆相の波形となる。
Next, the operation will be explained. FIG. 2 (8L1 to tel is a waveform diagram showing the waveform at each point in the full-wave rectifier circuit in FIG. 1. At points p and g shown in FIG. 1, the signal source Vin
From Ill, Ox, C! of capacitive element (3)! A signal enters through 2, and the voltage at point p and point g respectively;/'t Vp
, when vg and f, Vp, vg is fat as shown in Figure 2,
In particular, the waveform shown in iJ is of reverse phase.

vp>vg(最初の半周期)の場合入力トランジスタ+
41のQl 、 Q3がON、入力トランジスタ+4の
Q2.Q、4がOFFとなり、第1図に示すr点、8点
の電圧をそれぞれVr、VeとするときVr −Vp 
−WEE V日=  Vbias  −VBE Vg ) Vp (次の半周期)の場合、入力トランジ
スタ14)のQ2.Cl3がON、入力トランジスタ(
4)のQl 、 Q3がOFF’となl)r点、8点で
はVr = Vbiaa −VBE V日 ■ v(−VBE となる。次にr点、S点の信号が出力トランジスタaυ
のQ5+ Q’ 、でよるエミッタ結合回路によりVr
)Ve(最初の半周期)の場合、出力トランジスタαυ
のQa 7j: ON 、 QaがOFFとなりVOI
7T  −Vr  −VBE  ”  vp −2VB
gV日>Vr(次の半周期)の場合、出力トランジスタ
111)のQ5がON、QaがOFFとなり、VOUT
 −vB −VBK −Vg−Z、 VBEとなり第2
図10jに示すvoaTのような全波整流波形となる。
If vp>vg (first half cycle), input transistor +
41 Ql, Q3 is ON, input transistor +4 Q2. When Q and 4 are OFF and the voltages at point r and point 8 shown in Fig. 1 are Vr and Ve, respectively, Vr - Vp
-WEE Vday = Vbias -VBE Vg ) Vp (next half cycle), then Q2. Cl3 is ON, input transistor (
When Ql and Q3 in 4) are OFF', at points r and 8, Vr = Vbiaa -VBE V day ■ v(-VBE.Next, the signals at points r and S are output to the output transistor aυ
Q5+Q', the emitter coupling circuit allows Vr
)Ve (first half period), the output transistor αυ
Qa 7j: ON, Qa turns OFF and VOI
7T −Vr −VBE” vp −2VB
When gV day > Vr (next half cycle), Q5 of the output transistor 111) turns ON, Qa turns OFF, and VOUT
-vB -VBK -Vg-Z, VBE becomes the second
A full-wave rectified waveform like voaT shown in FIG. 10j is obtained.

筐たVr、Veの波形はそれぞれ第2図10j 、 +
dlに示すごとくである。
The waveforms of Vr and Ve are shown in Fig. 2, 10j and +, respectively.
As shown in dl.

なお、上記実施列では差動対の入力トランジスタ14)
及びエミッタ結合された出力トランジスタGIJにNP
N)ランジスタを用いたものを示したが、PNP トラ
ンジスタであってもよい。
In addition, in the above implementation column, a differential pair of input transistors 14)
and emitter-coupled output transistor GIJ to NP
N) Although a transistor using a transistor is shown, a PNP transistor may be used.

〔発明の・切果〕[The fruit of invention]

以上のように、この発明によれば、2組の差動対七エミ
ッタ結合回路により構成されているので、出力振幅にバ
ラツキのない高精度の全波整流回路が得られる。
As described above, according to the present invention, a highly accurate full-wave rectifier circuit with no variation in output amplitude can be obtained because it is configured with two sets of differential pair seven-emitter coupling circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による全波整流回路を示す
回路図、第2図tal〜telは窮1図の回路の各点に
おける信号の波形を示すR形図、第3図は従来の全波整
流回路を示す回路図、第4図(8L1〜+f+は第3図
の回路の各点における信号を波形を示す波形図である。 図においてll+は信号源V1n s +21は直流電
圧源。 31は容量素子、(4)は入力トランジスタ、(1o)
は抵抗素子、 UUは出方トランジスタ、0力は定電流
源Iz、04は定電流源12 、α4は定電流源xs 
、 g〜は電圧源入力である。 なお1図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a circuit diagram showing a full-wave rectifier circuit according to an embodiment of the present invention, FIG. 2 tal to tel are R-shaped diagrams showing signal waveforms at each point of the circuit in FIG. FIG. 4 is a circuit diagram showing the full-wave rectifier circuit of FIG. 31 is a capacitive element, (4) is an input transistor, (1o)
is a resistance element, UU is an output transistor, 0 power is a constant current source Iz, 04 is a constant current source 12, α4 is a constant current source xs
, g~ is the voltage source input. In addition, in FIG. 1, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 1対の入力トランジスタのコレクタ端子とコレクタ端子
とが接続され、エミッタ端子とエミッタ端子とが接続さ
れた第1の差動対と、第1の差動対と同じ構成の第2の
差動対と、第1の差動対のエミッタ端子にベース端子が
接続された第1の出力トランジスタと、第2の差動対の
エミッタ端子にベース端子が接続された第2の出力トラ
ンジスタと、第1の出力トランジスタのエミッタ端子と
第2の出力トランジスタのエミッタ端子が接続され、エ
ミッタ結合回路を構成したことを特徴とする全波整流回
路。
a first differential pair in which the collector terminals of the pair of input transistors are connected and the emitter terminals are connected; and a second differential pair having the same configuration as the first differential pair. a first output transistor whose base terminal is connected to the emitter terminal of the first differential pair; a second output transistor whose base terminal is connected to the emitter terminal of the second differential pair; A full-wave rectifier circuit characterized in that an emitter terminal of an output transistor and an emitter terminal of a second output transistor are connected to form an emitter-coupled circuit.
JP13793289A 1989-05-31 1989-05-31 Full-wave rectifier circuit Pending JPH032676A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13793289A JPH032676A (en) 1989-05-31 1989-05-31 Full-wave rectifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13793289A JPH032676A (en) 1989-05-31 1989-05-31 Full-wave rectifier circuit

Publications (1)

Publication Number Publication Date
JPH032676A true JPH032676A (en) 1991-01-09

Family

ID=15210063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13793289A Pending JPH032676A (en) 1989-05-31 1989-05-31 Full-wave rectifier circuit

Country Status (1)

Country Link
JP (1) JPH032676A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05344735A (en) * 1992-06-15 1993-12-24 Mitsubishi Electric Corp Full-wave rectifying circuit
US5721507A (en) * 1995-05-22 1998-02-24 Nec Corporation Full-wave rectifying circuit having only one differential pair circuit with a function for combining a pair of half-wave rectified currents into a full-wave rectified current
JP2009271034A (en) * 2008-05-12 2009-11-19 Toyota Industries Corp Ac current detection circuit
WO2009147765A1 (en) 2008-06-04 2009-12-10 東洋インキ製造株式会社 Composition for battery
WO2013162025A1 (en) 2012-04-27 2013-10-31 東洋インキScホールディングス株式会社 Composition for forming electrode of lithium secondary battery, electrode, and lithium secondary battery

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61235759A (en) * 1985-04-11 1986-10-21 Pioneer Electronic Corp Alternating current level detecting circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61235759A (en) * 1985-04-11 1986-10-21 Pioneer Electronic Corp Alternating current level detecting circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05344735A (en) * 1992-06-15 1993-12-24 Mitsubishi Electric Corp Full-wave rectifying circuit
US5412559A (en) * 1992-06-15 1995-05-02 Mitsubishi Denki Kabushiki Kaisha Full wave rectifying circuit
US5721507A (en) * 1995-05-22 1998-02-24 Nec Corporation Full-wave rectifying circuit having only one differential pair circuit with a function for combining a pair of half-wave rectified currents into a full-wave rectified current
JP2009271034A (en) * 2008-05-12 2009-11-19 Toyota Industries Corp Ac current detection circuit
WO2009147765A1 (en) 2008-06-04 2009-12-10 東洋インキ製造株式会社 Composition for battery
WO2013162025A1 (en) 2012-04-27 2013-10-31 東洋インキScホールディングス株式会社 Composition for forming electrode of lithium secondary battery, electrode, and lithium secondary battery

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