JPH03266132A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the probability of a system shutdown by connecting an arithmetic processor, composed of plural microprocessor parts, plural cache parts with cache by-pass mode, a crossbar switch means, and a majority decision circuit, to a diagnostic processor through a bus. CONSTITUTION:The arithmetic processor 9 consists of the microprocessors (MPU) 1 - 4 including the stand-by MPU, the caches 21 - 24 including the stand-by cache, the crossbar switch 10 which combines those MPUs 1 - 4 and caches 21 - 24 selectively, and the majority decision circuit 30 which make a triple majority decision according to the fault state of the caches 21- 24 and selects the outputs of the caches 21-24 by comparative logic. Then this arithmetic processor 9 is connected to the diagnostic processor 40 which indicates diagnosing operation for a fault by procedures predetermined in the crossbar switch 10 and majority decision circuit 30 through the bus 80. Consequently, the MPUs 1-4 and caches 21-24 which are not faulty are used effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an information processing device having the function of an arithmetic processing device based on majority logic.

[Conventional technology]

Conventionally, this type of information processing device has a microprocessor unit (hereinafter referred to as MPU), as shown in the block diagram of FIG.
401 to 404 and cache units 421 to 424, respectively, are configured as a set of arithmetic processing units 491 to 493, a standby arithmetic processing unit 494, and a majority circuit 430. Furthermore, three of the arithmetic processing units are used in the triple majority decision operation mode, and the remaining one is used as a standby system. When one of the microprocessor section or the cache section of one arithmetic processing section used in the triple majority decision fails, the failed arithmetic processing section is separated and a standby arithmetic processing section is incorporated to perform the triple majority decision processing; When a failure occurs in two arithmetic processing units, the two failed arithmetic processing units are separated and the remaining two arithmetic processing units enter a comparative operation mode. Furthermore, when three arithmetic processing units failed, the arithmetic processing unit system went down. Note that an input/output processing device 450 and a main storage device 460 are provided externally, forming an information processing device.

[Problem to be solved by the invention]

In the conventional information processing device described above, the microprocessor section and the cache section constitute the arithmetic processing section, so even if either the microprocessor section or the cache section fails, the arithmetic processing section will fail. Therefore, there is a drawback that the microprocessor section or the cache section that is not faulty cannot be used effectively. Therefore, there is a limit to the demand for redundancy in information processing equipment that is operated for a long period of time.

[Means to solve the problem]

An information processing apparatus of the present invention includes an arithmetic processing unit each having at least four or more microprocessor units and a cache unit, a main storage device, and an input/output processing unit. a crossbar switch section that takes any combination of selection modes depending on a failure; a majority circuit that selects multiple cache section outputs based on triple majority voting and comparison logic according to a failure mode of the cache section; - It has a switch section and a diagnostic processor that collects faults in the majority circuit and selects and controls a fault mode.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a configuration diagram of an information processing device according to an embodiment of the present invention, in which the arithmetic processing device 9 has four MPUs including one spare MPU.
PUs 1 to 4, four caches 21 to 24 including one spare cache, these MPUs 1 to 4 and cache 2
a crossbar switch 10 that selects combinations of the caches 1 to 24 according to an operation procedure described later; a majority circuit 30 that selects the caches 21 to 24 according to a fault condition described later;
It is comprised of a crossbar switch 10 and a diagnostic processor 40 that instructs a fault diagnostic operation according to a predetermined procedure based on the majority vote [i[F2O].

Note that the input/output processing device 50 stores desired programs and data in the disk group connected thereunder to the main storage device 6.
0, and after checking the occupied time of the bus 80, the data is transferred to the cache 2 in bytes from the main storage device 60.
The crossbar switch 10, which sequentially calls ports 1 to 24 to process data, is an MPU selection circuit 2 shown in FIG.
01, is composed of a cache selection circuit 202, an MPU selection mode register 203, and a cache selection mode register 204, and the circuit diagram of FIG. 2 shows the flow of signals according to the control operation of this crossbar switch 10.
As shown in FIG. 1, the majority voting circuit 30 includes a cache selection circuit 301, a multiplex majority voting and comparison logic circuit 302, a cache ratio selection mode register 303, a comparison valid mode register 304, and caches 21 to 24 from the bus 80.
The circuit diagram of FIG. 3 shows the flow of signals according to the control operation of the majority voting circuit 30.

Next, the operation of this embodiment will be explained mainly with reference to FIG.

First, when starting up the system, the diagnostic processor 40 loads a diagnostic program into the main storage device 60 from a disk included under the input/output processing device 50 . Next, the diagnostic processor 40 connects the bus 80, the majority circuit 30, and the cache 2.
A command signal is sent to the MPU selection mode register 203 via 1 or 22 or 23 or 24. The MPUg selection mode register 203 inputs the output signals of MPUs 1 to 4 to the caches 21 to 4, respectively, based on the command signal that is connected during normal operation.
Similarly, the diagnostic processor 40 also sends a command signal to the cache selection mode register 204. The cache selection mode register 204 controls the cache selection circuit 202 to output the output signals of the caches 21 to 24 to the MPUs 1 to 4, respectively, to form a signal path using a command signal, which is also a normal connection.

The diagnostic processor 40 also sends a command signal to the cache output selection mode register 303. The cache output selection mode register 303 controls the cache selection circuit 301 by a command signal that is connected during normal operation, and selects the cache 2.
1 is set to output W, cache 22 is set to output X, and cache 23 is set to output Y. In addition, in the initial state, the outputs of the comparison valid mode register 304 are all at the "0" level, and the outputs W, X, Y of the cache output selection circuit 301 (350 to 35 in FIG.
The triple majority voting and comparison logic circuit 302 executes the triple majority voting in 2). In this way, the diagnostic processor 4
0 instructs the arithmetic processing unit 9 to execute a diagnostic program after setting the status in various mode registers,
Check the normality of. If the execution of the diagnostic program is completed normally, that is, the MPU 4 and cache 24
And the state is set in the MPU selection mode register 203, the cache selection mode register 204, and the cache output selection mode register 303 so as to select two of each of the MPUs and caches determined to be normal by the execution of the diagnostic program. settings and instructs the execution of the diagnostic program. If the execution of the diagnostic program is normal, the diagnostic processor 40 resets the operating configuration in each mode register, and then transfers the program for system startup to the main storage device 60 from the disk to the input/output processing device 5.
After loading via 0, the CPU 9 instructs the arithmetic processing unit 9 to execute a boot load operation and starts the operating system.

When a triple majority vote failure occurs under the control of such an operating system, the majority decision circuit 3° enters the comparison operation mode and continues processing. At the same time, the arithmetic processing unit W9 interrupts the diagnostic processor 4o. The diagnostic processor 40 collects status information of the processing unit 9 in parallel with the operating system. Thereafter, the diagnostic processor 4o is interrupted when the operation of the operating system ends. After returning the comparison operation mode of the majority decision circuit 3° to the majority decision operation mode, the diagnostic processor 4o starts a diagnostic program and performs a diagnostic operation. Next, set the cache bypass mode for all configured caches, run the diagnostic program again, and confirm that the failure is caused by the MPU.
Determine whether it is in the cache or in the cache. In this way, the failure location is determined and the failure is registered on the system configuration table managed by the diagnostic processor.
Reset the changed value to select PU as normal cache or MPtJ. Also, the cache bypass mode is canceled for the cache. Thereafter, when a triple majority vote failure occurs, the same operation will occur. In addition, when either two caches or MPUs fail, if the system emphasizes processing performance, it is possible to specify in the comparison valid mode register 304 which outputs of the cache output selection circuit 301 are to be compared. The corresponding bit W of the comparison valid mode register 304. , Xc, Yc
(See FIG. 3), two bits are set to "1" to instruct the triple majority decision and comparison logic circuit 302 to perform a comparison operation. In addition, if two caches fail and the system emphasizes data quality over high-speed processing performance, specify cache bypass mode for all caches, and set triple majority voting and comparison logic circuit 302 to comparison effective mode. Register 304 specifies triple majority voting operation.

〔Effect of the invention〕

As explained above, the present invention connects an arithmetic processing unit consisting of a plurality of microprocessor units, a plurality of cache units with cache bypass mode, a crossbar switch means, and a majority circuit to a diagnostic processor via a bus. By connecting them, it is possible to disconnect only the failed microprocessor or cache, which increases the redundancy of the system against failures and has the effect of constructing a system that reduces the probability of system failure.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram of an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams of essential parts of this embodiment, and FIG. 4 is a block diagram of a conventional information processing apparatus. 1.2.3.4...Microprocessor section, 21゜2
2.23.24... Cache section, 10... Crossbar switch, 30... Majority circuit, 9... Arithmetic processing unit, 40... Diagnostic processor, 50... Input/output processing device, 60... Main storage device, 80... Bus, 2
01... MPU selection circuit, 202... Cache selection circuit, 203... MPU selection mode register, 20
4... Cache selection circuit, 203... MPU! !
Selection mode register, 204... Cache selection mode register, 205.206, 311, 312... 3-state driver, 207, 208, 310, 313.
3-state receiver, 301 Cache output selection circuit, 302 Triple majority voting and comparison logic circuit, 303 Cache selection mode register, 304
... Comparison valid mode register.

Claims (1)

[Scope of Claims] 1. An information processing device having an arithmetic processing unit each having at least four or more microprocessor units and a cache unit, a main storage unit, and an input/output processing unit,
A crossbar switch unit in which the microprocessor unit and the cache unit take any combination of selection modes depending on a failure, and selects multiple cache unit outputs based on triple majority voting and comparison logic depending on the failure mode of the cache unit. An information processing device comprising: a majority decision circuit; and a diagnostic processor that collects faults in the crossbar switch unit and the majority decision circuit, selects and controls a fault mode. 2. The crossbar switch section has a microprocessor selection circuit and a cache selection circuit that select combinations between a plurality of microprocessors and a plurality of cache sections, and each of the two selection circuits receives a command from a diagnostic processor. 2. The information processing apparatus according to claim 1, wherein the information processing apparatus is controlled by a microprocessor selection mode register and a cache selection mode register. 3. The information processing apparatus according to claim 1, wherein the plurality of cache units bypass all cache units according to instructions from the diagnostic processor to determine whether the failure is in the microprocessor unit or the cache unit. .