JPH03265216A - Semiconductor element output circuit - Google Patents

Abstract

PURPOSE:To allow the circuit to cope with even a heavy load by interposing 1st and 2nd output buffers to an output line through which an output of a semiconductor element is fed to an output terminal in parallel and providing a delay means to an input of a 2nd buffer. CONSTITUTION:When a heavy load exists at an output terminal, an output control terminal 14 connects to the position of ground GND to turn on an NMOS transistor(TRs) N3 and a PMOS TR P3 thereby connecting an output line and an output buffer 12. Since the output buffers 11, 12 are connected in parallel, one large output buffer is provided. However, the TRs N3, P3 are interposed between the line 2 and the input of the buffer 12 the TRs N3, P3 act line a resistor and a capacitor at the time of rising and falling of a semiconductor element, then the data of the line 2 is reach the buffer 12 later than the buffer 11. Thus, since the circuit drives a comparatively small buffer 11 only just after the time of rising and falling of the semiconductor element, the circuit copes with a heavy load.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an output circuit of a semiconductor device, and in particular, to an output circuit of a semiconductor device.
OS (Metal Oxide Sem1condu
ctor) In memory and MOS logic devices,
This makes it possible to avoid ringing in the output waveform that occurs as circuit operation speeds up.

[Prior art] Conventional output circuits used in MOS memories, etc.
For example, there is one shown in FIG. 4(a) or (b).

Figure 4(a) shows the CM OS (Complement
ary MOS) output circuit, and the power supply V. , and PMO3 (P-channel MO3) l- to ground GNIlrjI
Transistor P10 and NMO3 (N-channel MO3)
An output buffer 1 consisting of a CMOS inverter with a transistor N1o arranged in parallel is interposed between an output line 2 of a semiconductor element (not shown) and an output terminal 3, and an inverter is connected to the input side of the output buffer 1. There are 4.

Therefore, when the output line 2 is at H level, the PMOS transistor P1° is turned on and the NMOS transistor NIO is turned off, and the output terminal 3 is connected to the voltage aVtlD, so that the output becomes H level. Conversely, if output line 2 is at L level, PMOS transistor Pl+
1 is turned off and the NMOS transistor N,. is turned on and the output terminal 3 is connected to the ground GND, so the output becomes L level.

FIG. 4(c) shows the NMO3 output circuit, in which the power supply VD
Two NMO3) transistors N between D and ground G, ID
, and N1□ in series, and the gate of the NMOS transistor N on the power supply Vllll side is connected to the output line 2 via one inverter 4a, and the NMOS transistor N1 on the ground GND side. The gate of transistor N1□ is connected to output line 2 via two inverters 4b and 4c.

Therefore, even if it is a 20NMO3 output circuit, if the output line 2 is at H level, the NMOS transistor N11
is turned on and the NMOS transistor N12 is turned off, so that the output terminal 3 becomes a voltage. Since it is connected to Since it is connected to G and ID, the output becomes L level.

[Problem to be solved by the invention]

In this way, the conventional output circuits shown in FIGS. 4(a) and 4(a) can provide the desired operation, but in reality they have the following problems.

That is, in either of the circuits shown in FIGS. 4(a) and 4(b), the size of each transistor constituting the output buffer 1 is set depending on the size of the load connected to the output terminal 3. Usually, the larger the load, the larger the transistor.

For example, as shown in FIG. 5, when the output waveforms of these output circuits fall from the H level to the L level (
The same applies when rising from L level to H level.

), it settles down to the ground voltage after a certain amount of settling time, but if the transistors that make up the output buffer 1 are large and the circuit operates at high speed (the fall speed of the output circuit is fast), The amplitude of undershoot and overshoot across the ground voltage increases.

For this reason, as shown in FIG. 5, the output waveform that has fallen below the -degree threshold voltage V5M and reached the L level at T has a large overshoot, so the output waveform reaches the threshold voltage V5M again.
So-called ringing, which exceeds H level and becomes H level, occurs, and as a result, the actual access time of the output circuit becomes T2, rather than T, which is possible due to its ability.

Furthermore, if the overshoot or undershoot is large, noise may be generated in the power supply line, etc., and the internal circuit may malfunction.

These problems can be solved by making the transistor of the output buffer 1 smaller or by slowing down the circuit operation, but the size of the transistor is approximately determined by the connected load, and by slowing down the circuit operation. Doing so is not a good idea as it will result in lowering the product value.

The present invention has been made by focusing on the unresolved problems of the conventional technology, and provides an output of a semiconductor device that can handle even a large connected load and can avoid ringing. The purpose is to provide circuits.

[Means for Solving the Problems] In order to achieve the above object, the semiconductor element output circuit of the present invention connects first and second output buffers in parallel to the output line that supplies the output of the semiconductor element to the output terminal. In addition, a delay means is provided on the input side of the sofa to the second output.

[Effect]

In the present invention, the output of the semiconductor element is supplied from the output line to the output terminal via the first and second output buffers in parallel.

However, since a delay means is provided on the input side of the second output buffer, the output of the semiconductor element is first supplied to the output terminal via only the first output buffer, and then, after a slight delay, the output of the semiconductor element is supplied to the output terminal via only the first output buffer. Since the output buffer is activated, the signal is supplied to the output terminal via the first and second output buffers.

Therefore, when the output of the semiconductor element is supplied to the output terminal via only the first output buffer, it is equivalent to an output circuit equipped with a small output buffer, so the overshoot and undershoot of the output waveform are small. Therefore, when the output of the semiconductor element is supplied to the output terminal via the first and second output buffers, the load connected to the output terminal is equivalent to an output circuit with a large output buffer. Even if the size is large, it can be handled satisfactorily.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention. Note that FIG. 4(a) and (
Components equivalent to those in b) are given the same reference numerals, and redundant explanation thereof will be omitted.

First, the configuration will be explained.

That is, the output line 2 that supplies the output of a semiconductor element (not shown) to the output terminal 3 has a CMOS transistor in which a 2MO3) transistor P and an NMOS transistor N1 are connected in series.
Output buffer 11 as a first output buffer consisting of an inverter and PMOSMOS transistor PNMO3
Output buffer 1 as a second output buffer consisting of a CMOS inverter connected in series with an I-transistor N2
2 are interposed in parallel.

An NMOS transistor N3 as a delay means is provided between the PMOS transistor P-to and the inverter 4, and a 2MOS transistor N3 as a delay means is provided between the gate of the NMOS transistor N2 and the inverter 4.
3l-transistor P.

is provided, the gate of NMO3) transistor N3 is connected to the output side of inverter 13, and the gate of PMOS transistor P is connected to inverter 1 via inverter 15.
Further, the input side of the inverter 13 is connected to the power supply V,. It is connected to the output control terminal 14 which is connected to either the ground GND or the ground GND.

In addition, the output of the inverter 13 is the power supply Vllll and 2MO
3) 2MO3 interposed between the gate of transistor P2
) is also connected to the gate of transistor P4, and the output of inverter 15 is also connected to the gate of NMOS transistor N4 interposed between the gate of NMOS transistor N2 and ground CrND.

Therefore, when the output control terminal 14 is connected to the power supply VDII side, the output of the inverter 13 becomes L level, so NM
O3) The transistor N is off, and the PMOS transistor P is connected to the gate of the pMOS transistor P2.
Since the PMOS transistor P is turned off and the output of the inverter 15 becomes H level, the PMOS transistor P is turned off and the NMOS transistor N4 is turned on, and the gate of the NMOS transistor N2 is connected to the ground GND, so that the NMOS transistor N2 is connected to the ground GND. Since the transistor N2 is turned off, the output huffer 12 is disconnected from the output line 2.

Conversely, if the output control terminal 14 is connected to the ground GHD side,
Since the output of the inverter 13 becomes H level, NMO3
) transistor N is on, P M OS transistor P
4 is turned off, the output of inverter 4 is supplied to the gate of transistor P2, and the output of inverter 15 becomes L level, so PMOSMO
Since the S transistor P and the NMO3) transistor N2 are turned off, and the output of the inverter 4 is supplied to the gate of the NMO3) transistor N2, the output vanofer 12 is connected to the output line 2 in parallel with the output vanofer 11. become in a state of being

FIGS. 2(a) and 2(b) are configuration examples of loads connected to the output terminal 3, with FIG. 2(a) being an example of a relatively large load, and FIG. 2(b) being an example of a relatively large load. ) is an example of a relatively small load.

Here, the size of each of the transistors P, , N, , Pt, and N2 constituting the output huffers 11 and 12 is 300 μm/I, respectively, expressed as a gate width/channel length ratio.
μm, 150μm/1μm7 Q Oam/l am,
450 ttm/1t1m.

In other words, in this embodiment, when the output huffer 11 is made smaller than the output huffer 12, and when both of the output huffers 11 and 12 are set to the driving state as described later, the result shown in FIG. 2(a) is as follows. Corresponds to relatively large loads shown,
When only the output huffer 11 is in the driving state, the second
The output circuit corresponds to a relatively small load as shown in Figure (b).

Next, the operation of this embodiment will be explained.

That is, when the load connected to the output terminal 3 is a relatively large load as shown in FIG. 2(b), by connecting the output side m terminal 14 to the ground GNIll side,
O3) transistor N3 and PMO5I-transistor P,
is turned on to connect the output line 2 and the output buffer 12.

Then, since the output buffers 11 and 12 are in a parallel relationship, this is equivalent to providing one large output buffer.

However, between the output line 2 and the input side of the output buffer 12, an NMOS transistor N3 and a PMO3 transistor P are interposed, and when the output of the semiconductor element rises and falls, the NMOS transistor N3 and the PMO5I- Since the transistor P acts as a resistor and a capacitor, the data on the output line 2 reaches the output buffer 12 later than the output buffer 11.

As a result, only the relatively small output buffer 11 is driven immediately after the rise and fall of the output of the semiconductor element, so overshoot and undershoot of the output waveform are reduced, and the output buffer 12 is in the driven state. After that, it is equivalent to driving one large output buffer, so it can sufficiently handle large loads.

In other words, as shown by A in Figure 3, the output waveform in this case changes more smoothly than C, which is the waveform when a large output sofa is driven from the beginning, but overshoot and undershoot are extremely large. Since it is small, there is almost no fear of ringing, and as a result, access time is shortened.

On the other hand, when the load connected to the output terminal 3 is a relatively small load as shown in FIG. 2(b), by connecting the output control terminal 14 to the power supply VDD side, the NMO3
) transistor N3 and PMOS transistor P3 are turned off, and PMO3) transistor P4 and NMO3) are turned off.
Turn on transistor N4 to disconnect both the input and output sides of output buffer 12 from output line 2.

Then, since only the relatively small output buffer 11 can be driven, the output waveform becomes C as shown by B in FIG.
It changes even more quickly than before, and there is less overshoot and undershoot, so the access time is shorter.

In this way, with the configuration of this embodiment, the output control terminal 1
4 can be used as an output circuit for large loads or small loads depending on the connection state of 4. For example, if the user connects the output control terminal 14 to either the power supply VDD or the ground GN11, the output circuit can be programmed. It becomes an output circuit.

Moreover, the output circuit has high performance whether it is for a large load or a small load.

In particular, when used as an output circuit for large loads, as mentioned above, ringing is avoided, speeding up the circuit operation, and the excellent effect of being able to sufficiently handle even large loads. do.

In the above embodiment, a case was explained in which CMOS inverters were used as the output buffers 11 and 12, but the invention is not limited to this. For example, an NMO3 output circuit as shown in FIG. 4(b) may be used. It can be applied even if

Further, in the above embodiment, a case has been described in which the NMOS transistor N3 and the PMO3I-transistor P3 are used as the delay means, but the present invention is not limited to this. In other words, if the output circuit is dedicated to a large load, elements that act as switches such as the NMOS transistor N3 and the PMO3I-transistor P3 are unnecessary. Any element that can receive the output will suffice.

Furthermore, the size of each transistor P, N, P2, and N2 constituting the output buffers 11 and 12 is not limited to the above-mentioned value, but can be set arbitrarily depending on the size of the connected load, etc. It is.

〔Effect of the invention〕

As explained above, according to the present invention, two output buffers are provided and one output buffer is driven with a delay from the other output buffer, so overshoot and undershoot of the output waveform are reduced. , ringing is avoided, speeding up the circuit operation is achieved, and even a large load can be satisfactorily handled.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, FIG. 2(a) is a circuit diagram showing an example of a large load, FIG. 2(a) is a circuit diagram showing an example of a small load, and FIG. The figure is an output waveform diagram explaining the operation of this embodiment, in which A is the terminal 1.
Output waveform when 4 is connected to ground GND, B is terminal 4
C is the output waveform when C is connected to the power supply vDD, and C is the output waveform of a conventional circuit as a comparative example. Figure 4(a) and (b)
) is a circuit diagram showing an example of a conventional output circuit, and FIG. 5 is an output waveform diagram when the conventional output circuit is used. 2... Output line, 3... Output terminal, 11.12.
...Output buffer, 14...Output control terminal, N3...
・NM○S transistor (delay means), P, ---PM
OS transistor (delay means) Fig. 2 (0) (b) Fig. ND Fig. (0) (b) ND

Claims (1)

[Claims] (1) First and second output buffers are interposed in parallel on the output line that supplies the output of the semiconductor element to the output terminal, and a delay means is provided on the input side of the second output buffer. A semiconductor element output circuit characterized by: