JPH03265003A - Numerical controller - Google Patents

Abstract

PURPOSE:To shorten working time by simultaneously executing repeat calculation dispersively at plural CPU. CONSTITUTION:The arithmetic routine of a common memory CM22 is trans ferred to a local memory LM28 of a sub CPU 27, and an entry address is stored in the memory area of the leading address in the offset routine of the LM28. Then, the transferred flag of the CM22 is turned on. The final shape data on the CM22 is transferred to the LM28 and the leading address is transferred to the final block of the LM28. A CPU 21 executes offset operation. When the arithmetic end flag on the CM is turned on, the result on the LM28 is outputted and afterwards, the offset operation result is outputted through a pulse distributor 108. When the operation start flag on the LM is turned on, the sub CPU 27 operates the prescribed offset shape to the final shape block and when the operation is finished, the operation end flag on the CM22 is turned on. Thus, since the plural CPU 21 and 27 almost simultaneously operating the offset shapes of various offset amounts, the operation time is shortened and the working time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a numerical control device in which when it is necessary to perform the same processing multiple times, the processing is shared among a plurality of central processing units.

[Prior Art] FIG. 14 is a configuration diagram of a conventional numerical control device (hereinafter referred to as an NC device) disclosed in, for example, Japanese Patent Laid-Open No. 80-85811. In the figure, (101) is the operation display panel, (1
02) is a central processing unit (hereinafter referred to as CPU), (103
) is the NC data reading device, (104) is the NC tape of the computer program, (105) is the non-volatile memory element (hereinafter referred to as ROM), and (10B) is the data input/output device that exchanges data between the NC and the machine. It is.

(107) is a machine tool, (10g) is a pulse distributor, (
109) is a servo circuit, (110) is a servo motor, (
111) is a volatile memory element (hereinafter referred to as RAM) whose contents disappear when the power is turned off. (112) is a working memory, and (113) is a common bus.

Next, the operation will be explained. (b) When the cycle start button on the operation panel (101) is pressed, the CPU (102
) uses the NC data reader (103) to read the NC tape (
104) to read one block of NC data.

Note that in addition to normal path data, G function command data, and M-S-T- function command data, the NC tape records area processing data, and at the end of the NC program there is an M mark indicating the program end. A code (MO2) is recorded. Also, at the beginning of the area processing data, an area processing command indicating that the subsequent data is data area processing data is recorded, and at the end of the area processing data, a code indicating the end of the area processing data is recorded. ing.

(b) The CPU (102) determines whether the read NC data is "MO2°" indicating the end of the program under the control of the control program stored in the ROM (105), and if it is "MO2", the NC data is Finish the process.

(c) On the other hand, if the read NC data is not "MO2°" indicating the end of the program, the CPU (102)
It is determined whether the NC data is an area processing command.

(d) If the NC data is not an area processing command, the CPU (
102) executes normal NC processing. For example, if the NC data is an M-S-T-function command, these are output to the machine tool (107) via the data input/output device (10B) that functions as an interface circuit between the NC device and the machine. The NC data reading device (107) receives a completion signal indicating the completion of M-S-T-function command processing from the
3) to read the next NC data. Further, if the NC data is passage data, the following passage control processing is executed.

That is, the incremental value X1SYi of each axis.

Find Zi and find its incremental value and command feed rate F
and the velocity components in each axis direction, Fx, Fy.

Fz is calculated from the following formula % formula % ] (1), and then the predetermined time of 61 seconds (-
The amount of movement ΔX1 that should be moved in each axis direction during 8 msec)
ΔY1ΔZ is obtained from the following formula 6, %(2) (2) (2), and these ΔX1ΔY1ΔZ are output to the pulse distributor (10111) at every time ΔT. Pulse distributor (1
0g) performs simultaneous three-axis pulse distribution calculation based on input data (ΔX1ΔY1Δ2) to generate distributed pulses Xp, Y
p, Zp, and input the distributed pulses to the servo circuits (109X), (109Y), (109Z) of each axis, and drive the servo motors (uoX) (IIOY), (
Rotate IIOZ). As a result, the tool moves toward the target position relative to the workpiece.

In addition, the CPU (102) updates the current position Xa in each axis direction stored in the working memory (112) every 61 seconds.
%YaSZa is calculated as Xa±ΔX→Xa (3a
) Ya±ΔY −Y a −−−−・−
(3b) Za±ΔZ −Z a −−(
3c) Update (sign depends on direction of movement). Furthermore,
The CPU (102) similarly stores the remaining movement amount Xr1Yr in the working memory (112) every 61 seconds.

Zr (the initial values of Xr, Yr, and Zr are incremental values Xi, Yi, and Zi) is calculated as Xr−Δx by the following formula.
−x r −−(4a)Yr−ΔY −
Y r −−−−−−(4b) Zr−Δ
Z → Zr ...... (4C) Update. And CPU (102) is Xr-Yr-Z
r-0-=15), the next NC is read by the NC data reader (103).
Read the data.

(e) On the other hand, if the NC data is a region processing command in the determination process of step (c), the NC data reading device (1
03) to read the area processing data, and
(111).

Here, a case will be considered in which, for example, pocket processing as shown in FIG. 15 is performed as area processing. Figure 16 is a top view of the processed part in Figure 15, and in the figure (120)
is the final processed shape. When this pocket machining is performed, for example, from the outside with an end mill tool, first apply an offset calculation to the final machining shape (120) with an offset amount corresponding to the radius of the end mill tool, and the offset shape (
121).

Next, offset calculation is applied to the final machined shape (120) using the offset quantum predetermined depth of cut as the offset amount. Thereafter, in the same manner, offset calculations with different offset amounts are applied to the final machined shape (120) to sequentially obtain offset shapes (122), (123), and (124). Then, the obtained offset shape is output as a machining path according to the procedure described above.

[Problems to be Solved by the Invention] Since the conventional NC device is configured as described above, when the same calculation program is repeated many times as in the case of pocket machining, it is difficult to perform the same operation until one calculation is completed. Unable to start next operation. For example, in the example shown in Figure 16, the calculation of the next offset shape (122) cannot be performed until the calculation of the offset shape (121) is completed, and especially for complex shapes, calculation time is required, resulting in machining time. There was a problem that it was long.

Furthermore, in pocket machining, for example, the next offset shape is calculated during the machining process, which causes problems such as the machining temporarily stopping and creating grooves in the workpiece.

By the way, Japanese Patent Application Laid-Open No. 60-611402 discloses a technique in which a master central processing unit and a slave central processing unit are provided in this type of NC device, and each performs arithmetic processing. The device is installed on the machine side to reduce the number of signal lines connected to the NC device main body side, and is not intended to shorten the calculation time in repeated processing of the same calculation program.

This invention was made in order to solve the above-mentioned problems, and is applicable when the same calculation program is repeatedly executed based on different calculation data, such as offset shape calculation processing. In addition, by dividing the calculation processing among multiple CPUs and shortening the calculation time, an NC that prevents the processing from stopping in the middle of processing.
The purpose is to obtain equipment.

[Means for Solving the Problems] An NC device according to the present invention is a computer-controlled NC device having a function of repeatedly executing arithmetic processing of a predetermined arithmetic program based on different arithmetic data. It has a plurality of CPUs that are assigned to each CPU and execute its calculation programs.

Further, the NC device according to the invention is a computer-controlled NC device having a function of repeating arithmetic processing of a predetermined arithmetic program based on different arithmetic data, in which different arithmetic data are respectively assigned, and the above-mentioned It has a plurality of sub-CPUs that execute arithmetic programs and one main central processing unit that controls the distribution of arithmetic data of the plurality of sub-CPUs and the execution of the arithmetic processing.

[Operations] In this invention, a plurality of CPUs are assigned different calculation data and each executes the same calculation program.

Further, in the present invention, the main CPU allocates calculation data to the sub-CPU data, and further controls execution of the calculation processing. The sub CPUs each execute the same calculation program based on the calculation data assigned under the control of the main CPU.

[Embodiment] FIG. 1 is a block diagram of an NC device according to an embodiment of the present invention, and in this embodiment, a case will be explained in which there are two CPUs. In the figure, (21) is the main CPU that controls all CPUs, (22) is the common memory that includes the control program, offset shape calculation routine, shape data such as the final shape, work area, etc.
) saves the contents of the common memory (22) to the main CPU (21).
A direct memory access controller (hereinafter referred to as DMAC) for transfer without using
A bus arbiter (26) arbitrates so that only one of the common bus (23) and the common memory (22) can access the common bus (24).
Only one of A C (23) etc. is common memory (22
) is a memory arbiter that arbitrates for access. (27) is the secondary CPU, (28) is the secondary CPU (
27) Dedicated local memory; (29) is a bus arbiter that mediates between the two.

: (D actual m example Teha M CPU (27) no N minute (3
0)>(1m has been explained, but this sub CPU (
There may be a plurality of portions (30) of 27).

2 to 4 are flowcharts showing the operation of this embodiment, and FIGS. 5 and 6 are diagrams showing the data structures of the common memory (22) and local memory (28). The operation of the embodiment shown in FIG. 1 will be described below with reference to these figures.

FIG. 2 is a flowchart showing the initial processing that is performed only once when the main CPU (21) is powered on or when a predetermined offset calculation appears.
22) The offset shape calculation routine itself is transferred to the local memory (28) for the sub CPU (27) (Sll). Next, the storage area (fifth address) of the start address of the offset routine on the local memory (28) is
The entry address of the routine transferred in step (Sll) is stored in (b) of the figure (812). After that, the transferred flag on the common memory (22) (Fig. 5(a)
) is turned on (813).

The third WJ is a flowchart showing the process of calculating the offset shape of the main CPU (21). First, sub-C
An offset amount for offset calculation of P U (27) is calculated (814). Next, this value is stored in the offset amount storage area (Fig. 5(C)) on the local memory (28).
) (315).

Next, the final shape data on the common memory (22) is transferred to the local memory (28) (S18). and,
The start address is transferred to the final shape block on the local memory (28) (317). At this time, in the figure. Although not shown, the output address of the result of the offset calculation may also be transferred. When the output address is not transferred, the result is created at a certain fixed address, so the raw C
P U (21) knows this. Then, the calculation start flag on the local memory (28) (Fig. 5(e))
is turned on to clear the computation end flag on the common memory (22) (81g).

Thereafter, the main CPU (21) calculates the offset amount for the next offset calculation and performs its own offset calculation (819). And common memory (22)
Wait until the above computation end flag (FIG. 5(a)) is turned on (S20). When this is turned on, the result on the local memory (28) is output (821), and then the result of its own offset calculation is output (922).

This output takes place via a pulse distributor (10g).

FIG. 4 is a flowchart showing the processing of the sub CPU (27). Although the program itself for this process in the sub CPU (27) is not shown in the figure, it may be transferred before the transfer of the offset routine itself in FIG. 27) Local R for
I have it in OM. The sub CPU (27) waits for the computation start flag (Fig. 5(e)) on the local memory to turn on (323), and when it turns on, it starts a predetermined final shape block (Fig. 5(d)). )), a predetermined offset shape is calculated (FIG. 5(b)) (S24). When the calculation is completed, the calculation completion flag (FIG. 5(a)) on the common memo IJ (22) is turned on (825).

As described above, since the plurality of CPUs (21) and (27) calculate offset shapes with different offset amounts almost simultaneously, the calculation time for all offset shapes is shortened.

By the way, in the embodiment shown in FIG. 1, the CPU (27) is 1
However, if there are multiple sub CPUs (27), the initial processing in FIG. 2, the processing in steps (S15) to (S21) in FIG. 3, and the processing in FIG. It is sufficient to repeat this process as many times as there are sub-CPUs. In that case,
Flags, storage areas, etc. shown in FIG. 5 are prepared for the number of sub-cPUs.

FIG. 6 is a block diagram of an NC device according to another embodiment of the present invention. In the figure, (31) is the main CPU.

(32) is a secondary CPU, and (33) is a local RAM dedicated to the secondary CPU (2). (34) is the secondary CPU
(2) This is a non-volatile storage device (hereinafter referred to as local ROM) containing a control program for controlling. Secondary CPU (32), local RAM (3
3) and the local ROM (34) may be in the same class as one set, but a case of three sets will be described below.

7 to 9 are flowcharts showing the operation of the main CPU (11), FIG. 10 is a flowchart showing the operation of the sub CPU (82), and FIG. 11 is a flowchart showing the operation of the main CPU (31).
) in the working memory (112) of each sub-CPU.
The correspondence management table, FIG. 12 is a function management table similarly provided in the working memory (112), and FIG. 13 is a management table provided in the local RAM (33) for the sub CPU (32).

Here, in the function management table in Figure 12, the sub CPIJ
There are as many areas as (32), and the pointer points to one of them. This pointer has a ring buffer structure in which it can be advanced by that number, and if it is advanced beyond the last area, it will point to the beginning.

Next, the operation will be explained.

Normal operation is performed by a conventional CPU ((102 in Figure 14)
) of this embodiment was performed by the main CPU (3
1) is the same as the conventional method, so it will be omitted.

In the flowcharts of the main CPU (31) shown in FIGS. 7 to 9, first, when it is necessary to perform a certain calculation, it is determined whether or not it is a repetitive process (330). For example, the first
The processing shown in FIGS. 5 and 16 is determined to be repeated processing because offset calculations are performed using different offset amounts for the same final shape. If it is determined that it is not a repeated operation, the same processing as before is performed (S
31). When repeating processing, first perform initialization processing (
832). As this initialization process, the CP shown in FIG.
The U management table is cleared to O, the function management table shown in FIG. 12 is cleared to zero, etc.

Next, it is checked whether the following processes have been repeated for all sub-CPUs (32) (S33). This is because the number of secondary CP IJ (32) is known in advance (
In this example, the determination is made based on whether or not it has been repeated that number of times (three in this example). If the processing has not been repeated as many times as there are sub-CPUs, it is first determined whether the corresponding calculation program (in this example, the offset calculation program) has already been transferred to the sub-CPU (S34).

This determination is made depending on whether the function ID field of the corresponding sub-CPU in the CPU management table of FIG. 11 is 0 or something else. When it is 0, it means that it has not been transferred yet. Note that when a processing program is transferred, a function ID that specifies the program is set in this function ID field.

When not being transferred, the main CPU (31) ROM (
105) is stored in the local RAM (3
3) (S35). Then, the start address of the calculation routine is set in the calculation start address of FIG. At that time, a different function ID is set for each processing program in the function ID field of the corresponding sub-CPU in the CPU management table shown in FIG.

At that time, the sub CPU number to which the transfer has just been made is assigned to the area pointed to by the pointer in the function management table of FIG. 12, and the pointer is advanced by one. Next, it is checked whether the data (final shape data in this example) that is the basis of the calculation has already been transferred (93B). This is the corresponding sub-CP
The determination is made based on whether the input data address and the number of input data blocks on the local RAM (33) of the IJ (32) are not 0. If at least one of these two data is 0, it is determined that the original data has not been transferred. At that time, the data in RAM (111) is transferred to the local RAM (33), and the input data start address,
The number of input data blocks is set (S37).

Next, the data for calculation (in this example, the offset amount) is stored in the sub-CP shown in FIG. 13 on the local RAM (33).
Transfer to function argument area of U management table (838)
. Then, turn on the calculation start flag in the calculation start flag field of the same secondary CPU management table. , Nishiku 539)
, Furthermore, the operation flag in the operation flag field in FIG. 11 is turned on. The above steps (834) to (S4
0) is repeated for the number of sub-CPUs (32). When the repetition for all sub-CPUs is completed, the pointer of the function management table in FIG. 12 will point to the first area.

Next, it is checked whether the sub CPU (32) with the sub CPU number indicated by the pointer has completed its calculation (S41). This is the operation end flag (13th) in the operation end flag field on the local RAM (33).
(see figure) is turned on. If it is not yet turned on and the calculations have not been completed, it is determined whether all the current calculations have been allocated (S41). This is the case, for example, when there are only three sub-CPUs (2) and the offset calculation is performed five times.

In such a case, the sub CPU (
32) is checked by the same method as in step (S41). If the secondary CPU finishes the calculation first,
(32), the next operation is assigned to that sub CPU (32) (S44), (845).

At this time, since the calculation routine and the original data to be calculated have already been transferred, only the argument of the calculation routine (in this case, the offset amount) needs to be transferred again. Also, at this time, the output data is saved by means not shown in the figure.

When checking in step (S41), the secondary CPU (32)
If the calculation has been completed, the output data of the sub CPU (32) is transferred from the local RAM (33) to the RAM
<111) (846). Then R.A.
M (111) Turns off the calculation flag in the calculation flag field of the CPU management table shown in FIG. 11 above (847), and selects the secondary CP indicated by the pointer shown in
Clear the U number area to 0 and advance the pointer by one (
S4111). The same processing as in the conventional example is performed on the calculated data to control the machine tool (S49).

Then, it is checked whether all the calculations have been completed by checking whether the function relation table shown in FIG. Repeat from

The N10 diagram shows the sub CPU in the local ROM (34).
- It is a flowchart which shows the control program of (32). The secondary CPU (32) has a local RAM (33
) Wait without doing anything until the calculation start flag (see Figure 13) on the management table of the secondary CPU turns on (
Sho). When turned on, the calculation end flag is cleared and the calculation is performed on the input data from the given function start address in FIG. 13, and the calculation result is output to the output data area (Sol). Then, the calculation start flag is cleared and the calculation end flag is turned on (S82).

The process shown in the flowchart of FIG. 10 above is repeated in the same way in all the sub CPUs (32).

In this embodiment, the secondary CPUs (32) all had local ROMs (34) storing their own control programs, but of course each side CPU (32) only had a local RAM (33). Main CP first
You may decide to transfer it from U (31) to the secondary CPU (32).

Further, in the above-mentioned embodiments (FIGS. 1 and 6), examples of offset calculation have been described, but other calculations are of course possible. Conversely, if the entry is limited to offset calculations, there is no need to transfer the entry for the offset calculation routine on the sub-CPU if it is fixed. Furthermore, if the local ROM for the sub-CPU is sufficiently large and the offset calculation routine itself is stored in the ROM, there is no need to transfer the offset calculation routine itself.

[Effects of the Invention] As described above, according to the present invention, iterative calculations are distributed to multiple CPUs so that they can be executed simultaneously, so it is possible to perform the iterative calculations quickly, and as a result, the machining time is shortened. This has the effect of providing an NC device.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an NC device according to an embodiment of the present invention;
Figure 2 is a flowchart showing the initial processing of the main CPU, Figure 3 is a flowchart showing the offset calculation processing of the main CPU, Figure 4 is a flowchart showing the offset calculation processing of the main CPU, and Figure N5 is a flowchart showing the offset calculation processing of the main CPU. A diagram showing the data structure, FIG. 6 is a configuration diagram of an NC device according to another embodiment of the present invention, and FIGS. 7 to 9 are diagrams showing the main CP.
A flowchart explaining the operation of U, FIG. 10 is a sub-CP
Flowchart showing the operation of U, FIG. 11 is an explanatory diagram of the main CPU's sub-CPU correspondence management table, FIG. 12 is an explanatory diagram of the function management table, FIG. 13 is an explanatory diagram of the management table for the sub-CPU, and FIG. This figure is a block diagram of a conventional NC device, and FIGS. 15 and 16 are explanatory diagrams of pocket machining that requires repeated calculations in the NC device. In the figure, (21) is the main CPU, (22) is the common memory, (23) is the DMAC, (25) is the bus arbiter, (26) is the memory arbiter, (27) is the sub-CPU,
(28) is local RAM, (29) is bus arbiter, (31) is main CPU, (32) is sub-CPU, (33)
is a local RAM, and (34) is a local ROM. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a computer-controlled numerical control device that has a function of repeatedly executing arithmetic processing of a predetermined arithmetic program based on different arithmetic data, a plurality of centers are assigned different arithmetic data and execute the arithmetic program. A numerical control device characterized by having a processing device. (2) In a computer-controlled numerical control device that has a function of repeatedly executing arithmetic processing of a predetermined arithmetic program based on different arithmetic data, a plurality of sub-controllers are assigned different arithmetic data and execute the arithmetic program. A numerical control device comprising: a central processing unit; and one main central processing unit that controls distribution of calculation data and execution of calculation processing by the plurality of sub-central processing units.