JPH03263179A - Circuit diagram editing device - Google Patents

Abstract

PURPOSE:To eliminate the need to pay attention to hierarchic symbols in the designing of a logic circuit consisting of a large-scale hierarchic circuit by providing a symbol generation rule part and a hierarchic symbol generation part and generating the hierarchic symbols automatically according to a rule which is registered in advance. CONSTITUTION:A designer registers the rule in the symbol generation rule part 2 so as to obtain hierarchic symbols in desired shapes. A circuit diagram file 7, on the other hand, is stored with circuit information on a hierarchic circuit as an object of hierarchic symbol generation. The hierarchic symbol generation part 6 inputs the rule from the symbol generation rule part 2 and then input/output information from an input/output information acquisition part 3 next, and the input/output information acquisition part 3 inputs the input/ output information from the circuit diagram information in the circuit diagram file 7 in advance. The hierarchic symbol generation part 6 generates the hierarchic symbol automatically from the input/output information according to the rule. Consequently, the designer only registers the rule in advance to obtain the hierarchic symbols in the desired shape.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a circuit diagram editor for logic circuit design that generates hierarchical symbols for hierarchical circuits such as logic circuit devices.

The purpose is to automatically generate hierarchical symbols according to predetermined rules.

From a symbol creation rule section in which rules for creating a hierarchical symbol representing a logic circuit as a symbol are registered as external parameters, and a circuit diagram file that stores circuit diagram information regarding the logic circuit.

an input/output information acquisition unit that extracts input/output information about the logic circuit; and at least from the input/output information extracted by the input/output information acquisition unit according to the rules registered in the symbol creation rule unit.

and a hierarchical symbol creation section that creates the hierarchical symbol for the logic circuit.

[Industrial application field]

The present invention relates to a circuit diagram editor, and more particularly to a circuit diagram editor for designing a logic circuit that generates hierarchical symbols of a hierarchical circuit such as a logic circuit device.

When designing circuits such as logic circuit devices, CA using large computers, workstations, personal computers, etc.
D system is used, but in designing LSI circuits etc.
The mainstream is to design a circuit in which the entire circuit is divided into a plurality of functional blocks, that is, a hierarchical circuit.

[Conventional technology]

With conventional circuit design CAD systems, when designing a two-layer circuit, it is difficult to design a single-layer circuit.

It is necessary to create a two-layer symbol in order to reference that circuit in an upper layer circuit. Here, the upper layer circuit is a layer circuit that inputs the output of the layer circuit or includes the layer circuit.

When creating this hierarchical symbol, the designer artificially creates the above quotation according to the input/output information of the first layer circuit.
Input and output pins must be defined. Furthermore, when updating a two-layer circuit, the designer needs to visually check the difference between the new and old input/output information. This update of the hierarchical circuit is caused by changing the lower hierarchical circuit (or logic circuit).

[Problem to be solved by the invention]

With the recent increase in the scale of logic circuits, even one hierarchical circuit may have more than 100 inputs and outputs. This causes a first-order problem.

In other words, the definition of the hierarchical symbols of a two-layer circuit occupies much of the work process for one circuit designer, and since this work is done manually, the output information of the two people does not match the bins of the hierarchical symbols, resulting in inconsistencies. may occur. Additionally, if a hierarchical circuit is updated after creating a -degree hierarchical symbol, the symbol shape may be changed, but this may spread to the upper hierarchical circuit as the circuit is re-created, which can be a major problem. It had become. Furthermore, it was necessary to consider that the method of bin arrangement of first-level symbols must be changed depending on the type of design target.

An object of the present invention is to provide a circuit diagram editor that can automatically generate eight-layer symbols according to predetermined rules.

[Means to solve the problem]

FIG. 1 is a diagram illustrating the principle of the present invention and shows a circuit diagram editor according to the present invention.

In FIG. 1, 1 is a circuit diagram editor, 2 is a symbol creation rule section, 3 is an input/output information acquisition section, 4 is an existing symbol information acquisition section, 5 is an input/output information comparison section, 6 is a hierarchical symbol creation section, and 7 is an input/output information acquisition section. Circuit diagram files 8 and 9 are symbol files.

The symbol creation rule section 2 registers rules for creating first-level symbols as external parameters. This rule is 1, for example, the origin position I of the 0th layer symbol, the bin (
input/output terminal) length, etc.

The input/output information acquisition unit 3 is from the 2-circuit diagram file 7.

The input/output information regarding the logic circuit stored in the circuit diagram file 7 is extracted.

The hierarchical symbol creation section 6 creates a hierarchical symbol for the logic circuit from at least the input/output information taken out by the input/output information acquisition section 3. This creation is performed in accordance with the rules registered in the symbol creation rule section 2.

[For production]

In order to obtain a hierarchical symbol of the desired shape, the designer must:
The rules are registered in the symbol creation rule section 2 in advance.

On the other hand, the 1-circuit diagram file 7 stores circuit information regarding a hierarchical circuit for which a 1-level symbol is to be created.

The hierarchical symbol creation section 6 takes in rules from the symbol creation rule section 2, and then takes in input/output information from the input/output information acquisition section 3. Prior to this.

The input/output information acquisition unit 3 takes in the input/output information from the circuit diagram information of the two circuit diagram files 7.

The hierarchical symbol creation unit 6 uses the input/output information.

Automatically generates 9-layer symbols according to rules.

That is, the origin position and bin length of the 5th layer symbol are as follows.

The position and length are determined in advance by the rules.

This allows designers to simply register rules in advance.
A hierarchical symbol of a desired shape can be obtained. Also,
Since this hierarchical symbol is created by the second-level symbol generator 6, there will be no contradiction.

〔Example〕

FIG. 1 will be further explained.

The existing symbol information acquisition unit 4 stores the following information in the symbol file 8.
If there is an already created hierarchical symbol, its graphic information, pin information, etc. are extracted and sent to the input/output information comparison section 5. This ready-made hierarchical symbol needs to be a hierarchical symbol (before modification) for the hierarchical circuit stored in the two-circuit diagram file 7. For this purpose, for example, the input/output information of the hierarchical circuit before modification is sent from the input/output information acquisition section 3 to the already-symbol information acquisition section 4. The existing symbol information acquisition unit 4
The symbol file 8 is searched using the input/output information, and if there is a hierarchical symbol corresponding to the input/output information, this is acquired as an already created hierarchical symbol. At this time, in order to effectively utilize the hierarchical symbol, its graphic information, pin information (corresponding to input/output information), etc. are all extracted.

The input/output information comparison unit 5 takes in and compares the input/output information acquired and sent out by the input/output information acquisition unit 3 and the pin information acquired and sent out by the existing symbol information acquisition unit 4, and recognizes the changed part. , and sends this to the hierarchical symbol creation section 6. When pin information does not exist, that is, when no existing hierarchical symbol exists and a new hierarchical symbol is to be created, input/output information is sent to the hierarchical symbol creation section 6. This changed portion is recognized by comparing input/output information and pin information for each pin. Therefore, it is possible to recognize deleted pins, added pins, etc. due to changes.

The hierarchical symbol creation unit 6 creates or modifies a first-level symbol based on the comparison result in the input/output information comparison unit 5. That is, when creating a new hierarchical symbol, the hierarchical symbol is generated based on rules from the input/output information. On the other hand, when modifying a two-layer symbol, the graphic information and pin information are modified based on the rules using the input/output information. That is, pins that should be deleted are deleted, pins that should be added are added, and if necessary, graphic information is also modified.

The hierarchical symbols created by the hierarchical symbol creation section 6 are stored in the symbol file 9. This symbol file 9
is 2. When modifying the hierarchical symbol, it is used as the symbol file 8 that stores the already created hierarchical symbol.

FIG. 2 is an explanatory diagram of the embodiment.

FIG. 2(A) shows the symbol creation rule section 2 in a state in which rules have been registered from the outside.

A hierarchical symbol is a symbolic representation of a logic circuit, that is, a hierarchical circuit, and its shape is usually rectangular. Then, pins (input/output terminals) are added to this rectangle, and pin names, hierarchical symbol names, etc. are also displayed.

The rules are: 1 item, 1 origin position, 111 name display position standard (for hierarchical symbols), 111 symbol width J...etc.
Information is set so that each shape becomes a desired shape.

For example, if the "origin position" is set to "upper left J," the upper left corner of the rectangle of the symbol is set as the origin.Then, from this origin, the "convergence of the symbol rectangle" is determined by the "symbol convergence." .

On the other hand, the length (height) of the symbol rectangle is variable depending on the number of pins. In other words, [Upper/lower side-pin distance J determines the distance from the highest and lowest pins to the upper and lower sides of the symbol rectangle, and furthermore, the "pin spacing" determines the distance between adjacent pins arranged side by side. .

"Occupied area length" indicates the distance of the range to be occupied from the upper and lower sides of the symbol rectangle. on the other hand.

Regarding the occupied area width, does it occupy the length of the pin from the left and right sides of the symbol rectangle? , the width should be one area.

Here, the occupied area is an area in which description (existence) of hierarchical symbols for other hierarchical circuits constituting the same logic circuit is not permitted, and only the hierarchical symbol exists within the area.

The length of the pin is determined by "pin length.""Pin arrangement method" indicates a sorting method of arranging input pins according to pin salt, such as on which side of a rectangle of a hierarchical symbol, for example, input pins are arranged.

Note that this rule is commonly applied to the creation of a plurality of hierarchical symbols that constitute the same logic circuit.

FIG. 2(B) shows the input/output information acquisition section 3.

“The input/output information acquisition unit 3 extracts input/output information from the circuit diagram file 7 among the circuit information regarding the logic circuit for which the first-level symbol is to be created.

The input/output information consists of an "input/output column name", that is, a pin salt, and its "input/output type".The input/output column names are 9, for example, Di, D2, etc., set in advance by the circuit designer.

An appropriate name will be given. The input/output type indicates whether the pin is an input pin, an output pin, or an input/output pin.

FIG. 2(C) shows the already-symbol information acquisition section 4. As shown in FIG.

The existing symbol information acquisition unit 4 obtains, from the symbol file 8,
Extract pin information and graphic information about existing hierarchical symbols.

Bin information consists of a "pin salt" and its "coordinates" and corresponds to input/output information. In other words, it is possible to associate the input/output column name with the pin salt.

The coordinates indicate the positional coordinates of the pin from the origin in the hierarchical symbol.

The graphic information consists of "item" and "display coordinate j, and includes information when viewing a two-layer symbol as a graphic. For example,
It includes the display coordinates of the origin position (each side of the occupied area), each side of the symbol rectangle, each pin itself, the display position of each pin name, etc. Most of this information is used as is since five existing hierarchical symbols are used.

FIG. 2(D) shows the input/output information comparison section 5.

The input/output information comparison unit 5 compares the "pin salt" and the "input/output column name" and recognizes the added pin salt and the deleted pin salt. In other words, those in the "input/output column name" that are not in the "pin salt" are set as additional pin salts, and the reverse is set as deletion pin salts. This information is then sent to the first layer symbol creation section 6 along with the "graphic information".

Note that 1. If there is no information to be extracted from the symbol file 8, only "input/output information" is sent to the V# layer symbol creation 6.

FIG. 3 is a flowchart of hierarchical symbol creation processing.

■The symbol creation rule section 2 reads the rules.

(2) The input/output information acquisition unit 3 reads the input/output information of the circuit diagram for which hierarchical symbols are to be created from the 5-circuit diagram file 7.

(2) The existing symbol information acquisition unit 4 searches the symbol file 8 to check whether or not an existing hierarchical symbol exists, and if it exists, reads information on the existing symbol.

(2) The input/output information comparison section 5 compares the (new) input/output information with the existing symbol information (input/output information), and sends the result to the hierarchical symbol creation section 6.

(2) The hierarchical symbol creation unit 6 uses the pin farthest from the "origin" as a reference.

In addition, if there is no ready-made hierarchical symbol.

A part of process (■), processes (2) and (2) are omitted.

■The hierarchical symbol creation unit 6 sorts the additional pins.

Additional pins are placed in order from the reference point in the direction away from the origin.

Next, delete the delete pin from the existing hierarchical symbol.

(2) After the pin placement is completed in process (2), the three-level symbol creation unit 6 determines the area occupied by the symbol rectangle 5 according to the rules.

(2) Data regarding the hierarchical symbol created by the hierarchical symbol creation section 6 is saved in the symbol file 9.

FIGS. 4 and 5 are diagrams showing an example of hierarchical symbol creation.

FIG. 4 shows a case where a new hierarchical symbol is created.

First, circuit information about a (hierarchical) circuit as shown in FIG. 1 is saved in a circuit diagram file 7. and.

The circuit shown in the figure, in which only the input/output information is read, is the input/output information from the input/output pins and the input/output information. D2. D3. R3 and EN
Ql, Q2 . Equipped with QA and QN.

From this input/output information, hierarchical symbols as shown in Figure 1 are generated according to set rules.

That is, first, the "origin" is determined, and the "symbol width" is determined based on this. Also, depending on the "pin arrangement method", for example, input pins and output pins.

It is determined that they are placed on the left and right sides of the symbol rectangle, respectively.

Therefore, as a first step, each pin is sequentially arranged. First, place the first pins DI and Ql according to the "top side - pin distance", and then "
Arrange each pin according to pin spacing J. For each pin, each pin salt is displayed according to the "name display position".

After placing the last pin R3, F lower side - pin distance IL,
Define the bottom edge of the symbol rectangle. That is, the length of the symbol rectangle is determined. Note that the length of the pin is determined by "pin length."

Next, determine the occupied area. What is the width of the occupied area?

It is determined as the sum of the "symbol width" and the left and right "pin lengths." The length of the occupied area is determined by the sum of the length of the symbol rectangle and the upper and lower "occupied area lengths." Set the total occupied area length to "0"
Then, it is determined as shown in the figure.

As described above, a hierarchical symbol desired by the designer is uniquely generated according to predetermined rules, and the symbol file 9
will be saved.

FIG. 5 shows a case where a hierarchical symbol is modified by changing the circuit shown in FIG.

First, the circuit diagram file 7 from 2 is loaded into the editor and 1
After the circuit diagram has been modified as shown, it is saved again in two circuit diagram files 7. This change adds rcPJ as a new input, adds IQAI as a new output, and deletes rQ41 from the output. Then, new input/output information is read from the circuit diagram file 7, and the first-level symbols are read from the symbol file 8 (9).

This hierarchical symbol is modified with new input/output information.

That is, first, the additional pins CP and QA and the deleted pin Q4 are recognized.

Next, pins R3 (input pin side) and QN (output pin side) farthest from the "origin" are determined as reference points. and,
From this reference point, additional bins CP are sorted and arranged on the input bin side and additional pins QA are sorted on the output pin side according to the "pin spacing". At this time, the length of the pin is determined by "pin length", and the side to which pins CP and QA are added is determined by "pin arrangement method j". Also, deletion bin Q4 is deleted. Therefore.

Existing pin positions are not changed. Furthermore, the pin spacing, pin length, symbol width, etc. remain unchanged.

Next, modify the symbol rectangle according to the addition or deletion of hints. In other words, the lower side of the symbol rectangle is determined by the "lower edge - pin distance", and the lower edge of the occupied area is determined by the "occupied area length" (in this case, the occupied area length is -0). Therefore, the distance from the origin is equal to the pin distance. C) The symbol rectangle and occupied area length are extended in the direction.

Note that the widths of the symbol rectangle and occupied area are not changed.

Through the above steps, a modified hierarchical symbol is generated and saved in the symbol file 9.

In this way, the first layer symbol utilizes the existing layer symbol, pins that have not been changed are not moved, and additional bins are placed in new positions where there is no problem. Therefore, even if the lower hierarchical circuit is modified at the time of designing the upper hierarchical circuit, the influence on the upper hierarchical circuit can be reduced. Further, the amount of correction can be reduced.

〔Effect of the invention〕

As explained above, according to the present invention, by providing a symbol creation rule section and a hierarchical symbol creation section in a circuit diagram editor, hierarchical symbols can be automatically generated according to pre-registered rules. In designing a logic circuit consisting of a large-scale hierarchical circuit, it is possible to eliminate the need to be aware of hierarchical symbols, and to eliminate errors in the generation of two or two hierarchical symbols.

Furthermore, by providing an existing symbol information acquisition unit and an input/output information comparison unit, it is possible to create a new hierarchical symbol with minimal changes to the existing hierarchical symbol when input/output information is changed. can.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention. FIG. 2 is an explanatory diagram of the embodiment. FIG. 3 is a hierarchical symbol creation process flow. FIGS. 4 and 5 are diagrams showing an example of hierarchical symbol creation. 1 is a circuit diagram editor, 2 is a symbol creation rule section, 3 is a human output information acquisition section, 4 is an existing symbol information acquisition section, 5 is an input/output information comparison section 26 is a hierarchical symbol creation section, 7 is a circuit diagram file, 8 and 9 are symbol files.

Claims (1)

[Scope of Claims] A symbol creation rule section (2) in which rules for creating hierarchical symbols representing logic circuits as symbols are registered as external parameters; and a circuit diagram storing circuit diagram information regarding the logic circuits. an input/output information acquisition section (3) that retrieves input/output information about the logic circuit from a file (7); and at least the input/output information acquisition section (3) according to the rules registered in the symbol creation rule section (2). a hierarchical symbol creation unit (6) that creates the hierarchical symbol for the logic circuit from the input/output information extracted in 3);
A circuit diagram editor characterized by being equipped with.