JPH03262206A - Memory device and digital signal processing device - Google Patents

Abstract

PURPOSE:To reduce power consumption required for write by providing two each of address counters and memories, allowing one address counter to sample data, decrementing the count of the other address counter by a prescribed value when carry takes place so as to write the data. CONSTITUTION:An i-th output Xk-i in a k-th sampling period outputted from a memory device 100 and a filter coefficient hi of a ROM 200 are given to a multiplier 200, where they are multiplied. The result of multiplication is given to one terminal of an adder ALU 203 and added to the result of sum up to an (i-1)th period of a k-th sampling period given to the other terminal and stored in an accumulator ACC 204. The result of sum to be stored is given to other terminal of the adder ALU 203. ln a DSP constituted in this way, the sampling data Xk-i and the filter coefficient hi are read, multiplied, added and stored and they are repeated twice, and a new data is written therein when one sampling period is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing device used in a digital filter and a memory device built therein, and particularly relates to a digital signal processing device used in a digital filter and a memory device built therein.
The present invention relates to a memory device that stores numerical values for product-sum calculations of filters, and a digital signal processing device that performs the calculations.

[Conventional technology]

For example, when implementing an FIR filter as a digital filter, sampling data
(The sum-of-products operation shown in equation (1) below must be performed using k-+1 and the filter coefficient.

Q+= =Σ h, ・Xfk-il ・・
・(]) However: Number of samplings n: Number of taps of the digital filter (natural number) Figure 14 is a processing flow diagram of the filter calculation shown in equation (1) using the FIR filter. Coefficient. This is multiplied by the result of multiplying the previous sampling data Xh-+ by the filter coefficient h1, and this is repeated in order to perform the product-sum calculation shown in equation (1).

Figure 9 shows a conventional digital signal processing device (hereinafter referred to as Digital Sign
1 is a block diagram showing the configuration of a main part of an alProcessor DSP. In the figure, 200 is a RAM for storing sampling data X(k-i).
−++ is applied to the multiplier 202 together with a filter coefficient stored in the ROM 201 in advance. Multiplier 202
Then, multiply them and send the multiplication result to the adder (^LU)
203 at one end. The other end of the adder 203 is provided with previous addition results held in an accumulator (ACC) 204, which will be described later, and these additions are performed. The addition result is held in the accumulator 204,
The signal is applied to the other end of the adder 203 at the next timing.

In ll5P configured in this way, IIAM 200
sampling data Xfk-+1 stored in
The filter coefficients stored in ll0M 201 are read every cycle and input to multiplier 202. The multiplication result is input to one end of the adder 203, and added to the value held in the accumulator 204, that is, the previous addition result, input to the other end. In this way, the sum-of-products operation of equation (1) shown in the processing flow of FIG. 14 can be executed at high speed.

Next, at this time 1IAI'l 200 and ROM 20
The data arrangement in 1 will be explained. FIG. 11 is a diagram showing the arrangement order of filter coefficients written in the ROM 201, where the coefficient h0 for the latest sampling data Xk is at address O, and the coefficient h0 for the oldest sampling data Xk-□-0 is Filter coefficient hN-1 is written at address N-1. These filter coefficients are predetermined and stored in ROM, so this arrangement cannot be changed during calculation. 12th
The figure shows sampling data X written to RAM 200.
FIG. 3 is a diagram showing the arrangement order of Lk-=), in which the latest sampling data is always written to address O, and the oldest sampling data is always written to address N-1. For example, by changing the arrangement order shown in FIG. 12(a) at sampling time tk to the state shown in FIG. 12(a) at sampling time t, 1+1, one sampling cycle later, The output of the FIR filter according to the processing flow shown in FIG. 14 can be easily obtained. In other words, Fit? In the filter, high-speed calculation processing is possible by delaying sampling data by one period for calculation in the next period for each sampling period.

Japanese Patent Application Laid-open No. 63-2 has proposed a technique for easily realizing a one-cycle delay of sampling data written to the RAM 200.
There is one disclosed in Japanese Patent No. 66576. FIG. 10 is a block diagram showing the configuration of a RAM 200 of the DSP disclosed in the publication. The RAM 200 receives a basic clock signal φ supplied from a control circuit (not shown) in the DSP.

The memory cycle operates according to the basic clock signal φ. defined by. Again? The AM 200 is brought into a selected state using the memory cycle as a unit period according to the memory enable signal ME supplied as a control signal from the control circuit. At this time, the operating mode of the RAM 200 is determined according to the address shift mode signal SM and the read/write signal R/W supplied from the control circuit. That is, each of the above-mentioned signals is applied to the timing generation circuit 5, which generates control signals to be described later for each section.

Further, within the RAM 200, there is a RAM cell section as a storage element, which is composed of a decoder 12 for decoding input address signals, a memory array 13 consisting of word lines and data lines, and a sense amplifier 11 to which the data lines are connected. 10 is provided, and input/output of sampling data is performed via a data buffer 3 which latches sampling data thereto and latches sampling data read therefrom. The address given to the RAM cell section 10 is specified by the address pointer 7, and the output thereof is a +1 bit address signal A0 to Ak and an address signal obtained by adding 1 to the +1 bit address signal by the plus 1 circuit 8, which is given to the selector 9. The selector 9 is given the timing signal φ8s from the timing generation circuit 5, and its "L", '
"H" degree selects the address signal of the address pointer 7 to 0 to 0 or the output of the plus 1 circuit 8, and outputs it to the decoder 12 as complementary internal address signals 11 to LL.

The decoder 12 receives a timing signal φi from the timing generation circuit 5. is given, and when it is "H", the complementary internal address signal amount ~l is decoded. Furthermore, the sense amplifier 11 is given a timing signal φsll, and its H
'' data on the data line of the memory array 13 is read. Further, the data buffer 3 is given a write signal φ and a read signal φ from the timing generation circuit 5,
Writing and reading of sampling data is performed by these 'H' levels.

Next, the operation of the conventional RAM 200 configured as described above will be explained. FIG. 13 is a timing chart showing the access operation of the RAM 200. 124M 2
In 00, the normal read mode shown by a solid line or the normal write mode shown by a broken line is performed in the first half of the memory cycle, and the address shift mode is performed in the second half of the memory cycle. The address shift mode is a mode executed when the address shift mode signal needle is "H". In this mode, the RAM 200 reads sampling data in the first half of the memory cycle, and transfers the sampling data read in the second half to the next one. Write to the address corresponding to the sampling period. As a result, reading and shifting of sampling data for product-sum calculations related to filter calculations can be performed simultaneously, and high-speed processing becomes possible.

A plus 1 circuit 8 and a selector 9 for selecting two address signals are provided to obtain an address signal corresponding to the next sampling period based on the applied address signal.

The address shift mode shown in the latter half of FIG. 13 is based on the basic clock signal φ. It is started by the RAM 200 when the memory enable signal ME is set to "H" at the rising edge of , and at the same time, the address shift mode signal level is set to H.

Address signals A0 to A are supplied to the RAM 200 along with a memory enable signal ME, and the read/write signal R/W is set to "H".Address signals A0 to A11
is the address where the desired sampling data is stored “
i'' is specified.

In the RAM 200, the basic clock signal φ. Since the memory enable signal amount is "H" at the rising edge of , the timing signal φ is "H" for one memory cycle period.
, and the timing signals φS and φ are gradually delayed.
1 becomes "H" in turn. As a result, a continuous read operation similar to that in the read mode is performed, and the data stored in the memory cell at address "i" is stored in the data buffer 3.

However, the basic clock signal φ. At the falling edge when the signal becomes “I7”, the address shift mode signal needle goes to “H”.
Therefore, in the RAM 200, the timing signal φ□ is set to "H"'. As a result, the selector 9 receives the output signal of the plus 1 circuit 8, that is, the address signal "i+".
1" is selected and supplied to the decoder 12 as the complementary internal address signal LL""1. At this time, before the timing signals φ, 1, . . . are set to "H", the timing signal φ□ is temporarily set to “I,” and then becomes “H” again when the decoding operation by the decoder 12 is completed.
It is said that

In other words, during a period in which the address signal transitions and the decoding operation by the decoder 12 is in a transient state, the decoder 1
The second word line selection operation is prohibited, and all word lines become unselected.

By setting the timing signal φ to "H" again, the word line corresponding to the address "i÷1" is placed in the selected state. At this time, each data line and sense amplifier 11 are assigned the address "i" read in the first half of this memory cycle.
The continuous signal of °゛ remains established. Therefore, the read sampling data at address "i" is written into the word line selected in the second half of the memory cycle, that is, the memory cell at address "i+1".In other words, the sampling data successively read from address "i" is , is outputted via the bus, and written as is to the address "i+1" corresponding to the next sampling period, essentially realizing a shifting process of the sampling data.

[Problem to be solved by the invention]

In a conventional RAM configured as described above, in address shift mode in which sampling data is read for a product-sum operation related to a filter operation, data is always written to an address that is the read address plus 1 when reading data. Therefore, there is a problem in that more transistors have to be operated than when reading, which increases power consumption.

This invention was made in view of such circumstances, and
? A memory device that can access data at high speed and reduce power consumption by changing the address specified by an address pointer using a counter instead of changing the entire data arrangement between machine cycles in AM, and a memory device using the same. The purpose is to obtain a digital signal processing device.

[Means to solve the problem]

The memory device according to the present invention includes first and second address counters that count clocks, and changes the contents of the second address counter by +2 or 2 in response to an overflow signal of the most significant bit of the first address counter. provide means,
accessing a first memory with a first address counter;
accessing a second memory with a second address counter;
When the first address counter overflows, the contents of the second address counter are changed by +2 or -2, and the address of the second memory is changed by 1 each time the first address counter overflows. Further, the digital signal processing device according to the present invention is configured to perform a product-sum operation on the outputs of the first memory and the second memory.

[Effect]

In the memory device of the present invention, when the first address counter counts 2'1 times, data is sampled and an overflow signal is output, and when this is detected, the count value of the second address counter increases by +2. Or -2 changes, the second memory becomes rewritable, and the sampled data is written to the address of the changed value. Therefore, instead of changing the arrangement of data in the second memory at each count, by changing the address by one at each sampling, writing is performed only once per sampling period for every 2' access operations. Not done. Further, in the digital signal processing device of the present invention, the above memory device is used, and the number of writes is performed every sampling period, that is, every time each memory is accessed, the data is read, and the product-sum operation is performed 2'' times. Therefore, the power consumption required for writing is reduced.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings showing one embodiment thereof. FIG. 1 is a block diagram showing the configuration of a memory device according to the present invention. In the figure, 100 is a memory device, and R of 2'I words stores sampling data.
It has an AM 200 and a 2" word ROM 201 that stores filter coefficients. 1 is an n-bit counter, which is incremented by a clock φ1 supplied from a control circuit (not shown). is counted, and the n-bit counting result is supplied to the I?OM 201.The ROM 201 uses the n-bit counting result to specify an address when filter coefficients are successively added.

Counter 1 outputs its most significant bit carry signal CA to control circuit 5 and address counter 2, which will be described later, in synchronization with clock φ. Address counter 2 is n
It is a bit counter, and its count value is used for addressing the RAM 200 when reading and writing sampling data. The upper n-1 bits of the address counter 2 are incremented in synchronization with the clock φ, and count the clock φ1, and the least significant bit counts the control signal CT in synchronization with the control signal CT from the control circuit 5.

The control circuit 5 controls the clock input to the least significant bit of the address counter 2, and normally synchronizes with the clock φ1, and outputs a control signal CT which becomes "0" when the carry signal CA-"B" is input. address counter 2
Output to. This control signal CT is applied to the least significant bit of address counter 2. When address counter 2 receives carry signal CA from counter 1, it increases the count value by 2.
It has the function of

The carry signal is also given to the RAM 200, and the RA
M200 becomes writable when the carry signal CA-“1”.

RAM 200 addressed by address counter 2
sampling data or sampling data X k −i input via the data bus 6 is supplied to the data register A3 from a control circuit (not shown), and the clock φ
The filter coefficients of the ROM 201, which are latched by the clock φ0 that does not overlap with 1, and which are addressed by the n bits of the counter 1, are simultaneously latched into the data register B4.

Figure 2 is a circuit diagram showing the configuration of address counter 2. In the figure, 20 uses its own output as one input, adds the carry from the lower bit as the other input, and outputs the addition result and carry signal. This is a 1-bit adder.

21 is a 1-bit adder that inputs its own output, outputs its inverted signal as the addition result, and makes the carry signal "1" when the input is "1", corresponding to the least significant bit of address counter 2. It is.

22 is a 1-bit adder which takes its own output as one input, adds the carry signal from the lower bit as the other input, and outputs the addition result, which corresponds to the most significant bit of the address counter 2. In the address counter 2, the least significant bit (0th bit) is the adder 21, and the 1st bit to n-
The second bit is constituted by an adder 20, and the most significant bit (n-1th bit) is constituted by an adder 22, respectively. Adders 20, 20, 22 from the 1st bit to the n-1th bit
Addition is performed in synchronization with the clock signal CT, and addition is performed in synchronization with the control signal CT for the least significant bit (0th bit). Also, selector 2 surrounded by a broken line is on the carry propagation line from the least significant bit (0th bit) to the 1st bit.
3 is provided. When the selector 23 receives a carry signal CA, which is a carry of the most significant bit of the counter 1, it supplies it to the gate of the N-channel transistor 232 and the inverter 231. The output of inverter 231 is applied to the gate of N-channel transistor 233. A power supply voltage is applied to one end of the N-channel transistor 232, and a carry signal from the adder 21 is applied to one end of the N-channel transistor 233. N-channel transistors 232 and 233
The other end of the adder 2 is connected to the 1st bit adder 2.
0 to the carry input terminal of either transistor 232.
233 outputs are given. Therefore, during the period when the carry signal CA is "0", the N-channel transistor 232 is turned off and the N-channel transistor 233 is turned on.
The bit is input to the adder 20. On the other hand, the carry signal -
During the period when is "1", the N-channel transistor 232 is on and the N-channel transistor 233 is off, so that "1" is forcibly input to the adder 20 for the first bit. This allows address counter 2 to be incremented by +2. In the address counter 2 configured in this way, the carry signal last is “
During the period 0'', the selector 23 selects to use the carry signal from the least significant bit (0th bit) as the 1st bit carry signal, and the control signal CT is controlled by the clock φ,
Since it is output at the same timing as the clock φ1, +1 is added as a normal color 6 vine in synchronization with the clock φ1. When the carry signal - becomes "1", the control signal CT becomes "0", so the least significant bit does not change, and the selector 23 switches to input the power supply voltage as the carry signal input for the 1st bit. The carry signal input to the th bit is forcibly set to "1", and the address counter 2 indicates a value obtained by adding two to the value l clock cycle ago. After that, with the next clock φ, the carry signal becomes "0" again, so the selector 23 selects the carry signal from the adder 21 for the least significant bit (0th bit) as the carry signal input for the 1st bit. Switching occurs again, and the address counter 2 returns to normal count-up operation.

The general operation of the memory device configured in this way will be described. Address counter 2 and counter 1 are both n-bit counters, and basically both complete one cycle in 211 cycles. During the period when the carry signal CA is "0", the increment operation is executed by the clock φ, and the carry signal CA is "1", that is, the value of counter 1 is all "1".
All become “0”, and the most significant bit carry is “1”.
'', the value of the address counter 2 shows the value added by 2 to the value one clock cycle ago, and the sampling data Xk-1 on the data bus is written to this address in the RAM 200. Carry signal
is turned on, so the increment operation based on the clock φ is returned to.

Next, the operation of the memory device Y100 configured as described above will be described in detail.

FIG. 3 is a timing chart explaining the addressing operation of the memory device, and FIGS. 4 and 5 are 1? AM and R
FIG. 3 is a diagram showing a data arrangement in OM.

As shown in FIG. 5, in the ROM 201, the filter coefficient h0 corresponding to the latest sampling data is stored at address O, and the filter coefficient h2'-1 corresponding to the oldest sampling data is stored sequentially from address 1 to address 2n1.
New filter coefficients h2''...hl are stored in order.

Furthermore, as shown in Fig. 4, the sampling data is sent to the data bus 6 every sampling period, and one piece of data is sent as the latest data.
74M Rewrite the oldest data in 200.

In addition, in order to execute the calculation of the digital filter during the sampling period T, Δt=T/2' (2) However, the ROM 201 and IIAM are It is only necessary to read data from φ0. One clock period of φ1 is assumed.

A state in which sampling data Xk-+ is written to address i-1 of RAM 200 at sampling time tk-1 is defined as an initial state of RAM 200. The arrangement of sampling data in the RAM 200 at this time is as shown in FIG.
Newer sampling data are stored in order up to -1. Then, sampling data Xk-r + Xk-++-+1 . . . Xk-2 are stored in order from address 0.

At sampling time tk after 2"-1 clock cycles, the n bits of counter 1 change from all 9 "1" to all "O#", so the carry signal C
^ becomes "1", the selector 23 selects the 1" input, and the address counter 2 is incremented by +2 from t2 to become i. The sampling data X11 is written to the data register A3 via the data bus 6. At the same time, the value i of the address counter 2 is written to the RAM 200 as an address, and the RAM 200 enters the state shown in FIG. 4(b). In FIG. The latest data Xk of , is at address i+1
The oldest data Xk-+2-11 is written in the location indicated by. In other words, the latest data at the sampling time tk was written at the position of the oldest data in the data arrangement in FIG. 3(a), and the arrangement shown in FIG. 3(b) was obtained.

Since the ROM 201 is accessed by counter 1, the coefficient stored at address 0 is used. is being published one after another.

The counter 1 is incremented by the next clock φ1, and when the value of the counter 1 becomes "1", the carry signal CA becomes "0", so the selector 23 selects the carry from the 0th least significant bit (0th bit) to the 1st bit. Therefore, the address counter 2 performs the normal increment operation and outputs ++1, and the RA
The oldest data Xk-+2-+) stored at address i+1 is read from M200, and the coefficient h2'' stored at address 1 is read from ROM201.
The signals are input to data register A3 and data register B4, respectively. Furthermore, address counter 2 and counter 1 are incremented by the next clock φ, and RAM 20
From 0, data Xk-+2-I+1, which is one newer than the oldest data stored at address i+2, is also stored in the ROM.
From 201, the coefficient h z stored in counter 1
'-z are respectively read out and input to data register 83 and data register B4, respectively. This operation is repeated 2I'-1 times until the carry signal CA becomes "B", the address counter 2 reaches i-1, and the counter l reaches 2"-1.
(all n bits are "1").

As a result, from the RAM 200, the latest data Xk, the oldest data X, l-+z"-++ + Xw-+2-21
The sampling data is sequentially read out to the data register A3 in the order of ``'
read out.

At sampling time L1+1, all n bits of counter 1 change from “1” to all “0” and carry signal C
When A becomes 1", the selector 23 switches again to the "1" input. Then, the address counter 2 is incremented by +2 from i-1 to become i+1, and the sampling data X
? I is written to the location pointed to by address i+1 of RAM 200, resulting in the state shown in FIG. 4(C). At the same time, Xk+ is written to the data register 83. Further, since the value of the counter 1 is "0", the coefficient h0 pointed to by the address O of the ROM 201 is read into the data register B4. When the counter l is incremented by the next clock φ, the carry signal CA becomes “0” again, and the selector 23
switches to input the carry from the least significant bit (0th bit) to the 1st bit. Then, the address counter 2 performs a normal increment operation and outputs i+2. Thereafter, the address counter 2 is incremented to i during 2''l cycles, and the data is sequentially read out to the data register A3 in the order of latest data L++s oldest data X to (241s Xk-+2-31...X).

Further, the ROM 201 uses the counter 1 as the address and the address 0. Address 1. Address 2...Address 2''
Coefficient ho + hz'-+... stored in 1
is read into data register B4.

Thus, the sampling time t. Counter 1 again at 2
When the n bits of all go from all “1” to all “0”,
The carry signal becomes “BI” and the selector 23 becomes “1” again.
Switches to input, address counter 2 changes from 逼 to +
2 is added and becomes i+2.

Then, the sampling data 3. Repeat the write, read, and coefficient read operations.

As a result, it is only necessary to write the sampling data once in the sampling period, and there is no need to write it every time it is read as in the conventional case, and the number of write operations is reduced to 1/27th of the conventional number of times.

Next, other embodiments of the invention will be described.

In the above embodiment, the counter 1 and the address counter 2 were configured with n-bit counters that incremented, but these may also be n-bit counters that decremented the count value from 2"-1 to O. In that case, the configuration is as follows. 6 and 7 are diagrams showing data arrays in the RAM 200 and ROM 201 in this case.

As mentioned above, in this embodiment, unlike the previous embodiment, counter 1 and address counter 2 are decremented by n.
It consists of a bit counter and therefore RAM 2
The sampling data stored in 00 is symmetrical to that shown in FIG. 4 about address i, and 170M 2
The filter coefficients stored in 01 are arranged in the reverse order with respect to the addresses of those shown in FIG. i.e. RAM 20
0, sampling data L+-,
+,.

However, the same Xk-4 is also at address 2"-1, and address l
The oldest sampling data Xk-2' is stored in respectively. Also, in ROM 201, address 2°
-1 is the filter coefficient h0 corresponding to the latest sampling data xh-+, and address 2"2 is the filter coefficient h2"-1 corresponding to the oldest sampling data xk-2".
are stored respectively.

Next, a digital signal processing device (DSP) according to the present invention
I will explain about it. FIG. 8 is a block diagram showing the configuration of the main parts of the DSP of the present invention for realizing an FTP filter. In the figure, 100 is a memory device of the present invention, and the i-th output X, -4 of the RAM 200 in the sampling period and the filter coefficient of the ROM 200 are given to a multiplier 202, where they are multiplied. be done. The multiplication result is applied to one end of the adder (ALU) 203, added to the addition result added up to the i-1st sampling period, which is applied to the other end, and is held in the accumulator (ACC) 204. Ru. The retained addition result is provided to the other end of adder 203.

In the DSP configured in this way, the sampling data X, -1 and the filter coefficients are clock φ. It is read out at the timing of , and multiplication, addition, and retention are performed.

This is repeated 2″ times, and when one sampling period ends, new sampling data is stored in RAM 200.
It is written to the incremented address and performs the same operation.

〔Effect of the invention〕

As explained above, according to the present invention, the first and second
The two address counters in the first memory and the second
Since it is only necessary to specify the address of the second memory, change the address to be accessed without changing the data arrangement in the second memory, and perform the write operation once every sampling period, the power consumption of the memory can be reduced. , high-speed access is possible, and when used in a DSP, excellent effects such as high-speed access, reduced power consumption, and suppressed heat generation are achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a memory device according to the present invention, FIG. 2 is a circuit diagram showing the configuration of an address counter,
FIG. 3 is a timing chart explaining the addressing operation of the memory device, FIG. 45 is a diagram showing the data arrangement of RAM and ROM, and FIGS.
8 is a block diagram showing the configuration of the main part of the digital signal processing device according to the present invention; FIG. 9 is a block diagram showing the structure of the main part of the conventional digital signal processing device; Is Figure 10 a conventional RA? Figures 11 and 12 are diagrams showing the data arrangement of conventional ROM and RAM, and Figure 13 is a block diagram showing the configuration of conventional RA.
FIG. 14 is a timing chart showing the access operation of M, and is a processing flow diagram of the product-sum operation in the FIR filter. 1...Counter 2...Address counter 5...
・Control circuit 100...Memory device 200
. . . RAM 201 . . ROM 202 . . . Multiplier 203 . . . Adder (ALU) 204 . 8

Claims (2)

[Claims] (1) n-bit first and second address counters that count clocks, and the contents of the second address counter are +2 or -2 depending on the overflow signal of the most significant bit of the first address counter. A memory device comprising: means for changing; a first memory accessed by a first address counter; and a second memory accessed by a second address counter. (2) the memory device according to claim 1; Read the values stored in the first and second memories. a multiplication means for multiplying and multiplying; Find the difference of the products obtained by the multiplication means addition means and A digital signal characterized by comprising: Processing equipment.