JPH03261992A - Image composition system - Google Patents

Abstract

PURPOSE:To compose data of two image data by a line memory and a frame memory and to reduce the memory capacity by writing image data corresponding to the same line and reading data out of the frame memory corresponding to the line. CONSTITUTION:First image data is written in the line memory 111 in synchronism with a 1st horizontal synchronizing signal H1 and 2nd image data is written in the frame memory 121 in synchronism with 2nd horizontal and vertical synchronizing signals H2 and V2. Further, the 1st image data is read out of the line memory 111 in synchronism with the 1st horizontal synchronizing signal H1 and the 2nd image data is read out of the frame memory 121 in synchronism with the 1st horizontal and vertical synchronizing signals H1 and V1 corresponding to the 1st image data. Therefore, the image data are both read out in synchronism with the 1st horizontal and vertical synchronizing signals H1 and V1 and the two synchronizing image data are obtained to compose the image by a composing means 131. Consequently, the memory capacity is reducible.

Description

[Detailed Description of the Invention] [Summary] Regarding an image synthesis method in which two input video signals are synthesized, the purpose of reducing memory capacity is to synchronize with the first horizontal and vertical synchronization signals H1 and V1. One line of this image data is stored in synchronization with the first horizontal synchronization signal H1, and the stored image data is synchronized with the first horizontal synchronization signal H1. The line memory to be output and second image data synchronized with the second horizontal and vertical synchronizing signals H2 and V2 are input,
This image data for one screen is stored in synchronization with the second horizontal and vertical synchronization signals H2 and V2, and the stored image data is output in synchronization with the first horizontal and vertical synchronization signals H1゜vl. The image forming apparatus is configured to include a frame memory and a synthesizing means to which the first and second image data outputted from the line memory and the frame memory are input and which synthesizes the image data.

[Industrial application field]

The present invention relates to an image composition method that combines two input video signals.

[Conventional technology]

In recent years, with the diversification of uses for personal computers (hereinafter referred to as "personal computers"), information systems such as data created on computers are being superimposed on images of video tape recorders (VTRs), laser disc devices, etc. as in-store terminals. Techniques for displaying them together are widely used.

FIG. 6 shows an outline of the case where images from other devices are synthesized and displayed on the screen of a personal computer. FIG. 6 (a) shows the system configuration. For example, as shown in FIG. 6(b), a display image of a zero composite image that imports a moving image or a still image from the laser disk device 631 and synthesizes it with the personal computer 611's own characters, graphics, etc. and displays it is as shown in FIG. In some cases, images input from the VTR 621 and the laser disc device 631 are displayed in different areas of the display screen, and data from the personal computer 611 is also added, and as shown in FIG. It is conceivable that one of the images of 631 is displayed with the other image superimposed, and data from the personal computer 611 is also added.

By the way, the conventional method of combining and displaying an image input to a computer or the like with data created inside the computer is to temporarily store the input image in a frame memory and combine this stored data with the data created internally. A method that synchronizes and synthesizes is widely used.

FIG. 7 shows a detailed configuration of the personal computer 611 when such a conventional method is applied to the system of FIG. 6(a).

The video signal a is input from the VTR 621, and the video signal a is input from the laser disc device 631.

As shown in FIG. 7, separation circuits 711 . It has a PLL 721 and three frame memories 731, 733, 735 corresponding to each color of RGB, and a separation circuit 751.735 corresponding to the video signal. PLL7
61 and three frame memories 771, 773, and 775 corresponding to each color of RGB. Note that the synchronization signal generation circuit (SYNCGEN) 791 generates a synchronization signal for matching the read timings of the frame memories 731 to 735 and 771 to 775.

In this way, by storing the video signals a and b in their corresponding frame memories and then reading them out in synchronization, data such as characters generated inside the personal computer 611 can be synchronized with these read RGB data. This makes it possible to superimpose the images.

[Problem to be solved by the invention]

By the way, in the conventional method described above, the input 2
The problem was that it required a large memory capacity since it was equipped with a frame memory corresponding to each of the two video signals.

For example, the display screen of PC 611 is 400 pixels vertically and 6 pixels horizontally.
If it is composed of 40 pixels and each pixel is represented by 8 points each for RGB, each frame memory will have 256 bytes, or 1
A memory capacity of 256K x 3 bytes is required to accommodate one video signal, and the circuit scale increases to accommodate the large memory capacity, resulting in an increase in device cost. Furthermore, in recent years, the resolution of display screens has tended to increase, and as the resolution increases, it is necessary to increase the memory capacity.

The present invention was created in view of these points, and an object of the present invention is to provide an image composition method that can reduce memory capacity.

[Means to solve the problem]

FIG. 1 is a principle block diagram of the image synthesis method of the present invention.

In the figure, the line memory 111 receives first image data synchronized with first horizontal and vertical synchronization signals H1 and V1, and synchronizes one line of this image data with the first horizontal synchronization signal H1. At the same time, the stored image data is output in synchronization with the first horizontal synchronization signal H1.

The frame memory 121 receives a second horizontal and vertical synchronizing signal H.
2, the second image data synchronized with V2 is input, 1iii planes of this image data are stored in synchronization with the second horizontal and vertical synchronizing signals H2, V2, and this stored image data is inputted into the first image data. horizontal.

Output in synchronization with vertical synchronization signals H1 and V1.

The synthesizing means 131 receives the first and second image data outputted from the line memory 111 and the frame memory 121, and synthesizes the image data.

Therefore, the overall configuration is such that data is read from the frame memory 121 in accordance with the read/write timing of the line memory 111.

[For production]

Writing of the first image data to the line memory 111 is performed in synchronization with the first horizontal synchronization signal H1, while the second
Writing of the image data into the frame memory 121 is performed in synchronization with the second horizontal and vertical synchronizing signals H2 and V2.

Further, reading of the first image data from the line memory 111 is performed in synchronization with the first horizontal synchronizing signal H1, while reading of the second image data from the frame memory 121 is performed based on the first image data. This is performed in synchronization with the first horizontal and vertical synchronizing signals H1 and V1 corresponding to the first horizontal and vertical synchronizing signals H1 and V1.

Therefore, line memory 111 and frame memory 121
The reading of image data from is performed in synchronization with the first horizontal and vertical synchronizing signals H1 and V1, and these read image data are combined by a combining means 131.

In the present invention, the line memory 111 writes and reads image data corresponding to the same line, and the frame memory 121 corresponding to this line writes and reads the image data corresponding to the same line.
By reading the stored data of the two
This makes it possible to obtain two image data and perform synthesis by the synthesis means 131.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment to which the image synthesis method of the present invention is applied.

In the figure, 211 is a synthesis control section, 221 and 261 are
is a separation circuit, 231 and 271 are phase-locked loops (P
LL), 241, 243 and 245 are line memories, 281, 283 and 285 are frame memories, 29
1 indicates a synthesis section.

Separation circuit 221. The PLL 231 and the three line memories 241 to 245 are for once capturing the video signal a and then outputting it at a predetermined timing.

The separation circuit 221 generates and separates R, G, and B color data (8 bits each) from the input NTSC composite video signal a, and extracts horizontal and vertical synchronizing signals H and V. It is. The generated RGB data is supplied to three line memories 241 to 245, and the synchronization signals H and V are supplied to the PLL 231.

The PLL 231 adjusts the phases of the input synchronization signals H and V, and produces adjusted horizontal and vertical synchronization signals H+.

■ Output ゛. This horizontal synchronizing signal H' is supplied to each of the line memories 241-245 as a write signal and a read signal.

The line memory 241 is for storing one line of 8-bit data corresponding to the OR of RGB data, and is configured with a first-in first-out memory (FIFO) having a capacity of 1024 bytes, for example.
41 takes in the R data separated by the separation circuit 221 in synchronization with the write signal, and outputs this stored data in synchronization with the read signal.

Similarly, the line memory 243 is configured with a FIFO, and stores one line of G data in synchronization with the write signal, and outputs it in synchronization with the read signal. The line memory 245 is composed of a FIFO, and stores one line of b data in synchronization with the write signal, and outputs it in synchronization with the read signal.

Also, the separation circuit 261. The PLL 271 and three frame memories 281 to 285 are used to once capture a video signal and then output it at a predetermined timing.

The separation circuit 261 performs the same operation as the separation circuit 221, and generates and separates R, G, and B color data from the input NTSC composite video signal, and also generates horizontal and vertical synchronization signals H. , V. The generated RGB data is stored in three frame memories 28.
1 to 285, and synchronizing signals H and V are supplied to PLL271.
is supplied to

The PLL 271 performs the same operation as the PLL 231, and adjusts the phase of the input synchronization signals H and V.
Horizontal and vertical synchronization signal H” after adjustment.

■" is output. This horizontal and vertical synchronization signal H".

■'' is supplied to each of the frame memories 281-285.

The frame memory 281 is for storing one frame (screen) of 8-bit data corresponding to the OR of RGB data, and has a capacity of, for example, 256 bytes. The frame memory 281 horizontally stores the R data separated by the separation circuit 261.

In synchronization with the vertical synchronization signals H", ■", that is, take in the storage area corresponding to the display position of the pixel, and output this stored data in synchronization with the horizontal and vertical synchronization signals H"V l output from the PLL 231. do.

The combining unit 291 receives two RGB signals input from the line memories 241 to 245 and the frame memories 281 to 285.
It is used to synthesize data. line memory 24
Reading of RGB data from 1 to 245 and reading of RGB data from frame memories 281 to 285 are both performed using the horizontal and vertical sentence signals H output from the PLL 231.
', V', two RGB data corresponding to the same pixel are input to the synthesis unit 291 at the same timing, and the synthesis unit 291 can select either of these two RGB data. The images are synthesized by

FIGS. 3 and 4 show the timing of reading and writing RGB data in each line memory and each frame memory described above.

FIG. 3(a) shows the operation timing at which the first line of the video signal a is stored in the line memories 241 to 245.
Figure (b) shows video signal a in line memories 241 to 245.
This shows the operation timing at which the line is stored. Also, rw, p, in the figure.

indicates a write pointer, and rR, P, and J indicate read pointers, respectively. W, P indicate which line the input video signal corresponds to, and R
, P indicates which line the data to be read corresponds to.

Since video signal a and video signal S are generally asynchronous, when the Oth line of video signal a is being input, the video signal S line is being input. Therefore,
Frame memos I7281-285 are provided so that the video signals of this first line can be stored. Data is read from these frame memories at the same timing as the line memories 241 to 245. Therefore, when data is being written to the 0th line, data is read from the storage SIN corresponding to the 0th line. will be held.

Similarly, when the nth line of video signal a is being input, the (k+n)th line of video signal A is being input, and is stored in the corresponding areas of frame memories 281 to 285. At this time, data corresponding to the nth line is read from each of the line memories 241 to 245 and the frame memories 281 to 285.

In addition, FIG. 4(a) shows the timing of writing data to the line memories 241 to 245, and Φ) in the same figure shows the timing of writing data to the frame memories 281 to 285.
C) shows the read timing of data from the line memories 241 to 245, and FIG.
The read timings from 285 to 285 are shown respectively. Further, "m" and 'PJ' in the figure indicate the frame serial number of the video signal a or b.

As shown in FIG. 4, when the Oth line of the video signal a is written in the line memories 241 to 245, the Oth line of the video signal a is written in the frame memories 281 to 285, and at this time, Video signal a corresponding to the previous frame.

Each Oth line of b is read from each of the line memory and frame memory. Similarly, line memory 24
When the nth line of the video signal a is written in frames 1 to 245, the (n+k)th line of the video signal a is written in the frame memories 281 to 285. Each nth line of video signals a and b is read from each of the line memory and frame memory.

In this way, by matching the reading timing of the line memories 241 to 245 storing one video signal a with the reading timing of the frame memories 281 to 285 storing the other video signal a, the combining unit 29
It becomes possible to synthesize images according to 1. Therefore, it becomes possible to store one video signal a in the line memories 241 to 245, thereby reducing the overall memory capacity.

FIG. 5 shows a configuration when the embodiment shown in FIG. 2 is applied to a personal computer as shown in FIG.

In FIG. 5, 511 is a display control section, 513 is a character generation section, 515 is a graphic generation section, and 52
1 indicates a display section.

In FIG. 5, the same reference numbers as in FIG. 2 indicate the same components.

The display control section 511 controls the composition section 291. It includes a character generation section 513 and a graphic generation section 515, and controls the display on the display section 521.

Horizontal and vertical synchronization signals H''Vl output from the PLL 231 in the synthesis control section 211 are input to the display control section 511, and the character generation section 513 and the graphic generation section 515 use the horizontal and vertical synchronization signals H', The pattern data generation operation is performed in synchronization with V'. Therefore, the two RGB data output from the composition control section 211, the character generation section 513, and the graphic generation section 515
All data generated by horizontal and vertical synchronization signals H'■
”, the synthesis unit 291 synthesizes images based on these data, and the synthesis result is displayed on the display unit 52.
Displayed by 1. As a result, a composite screen as shown in FIG. 7 is displayed.

In addition, in the embodiment of the present invention described above, two video signals a
, b has been considered, but the present invention can also be applied to a case where three or more video signals are input. In this case, only one video signal may be stored in the line memory, and the other two or more video signals may be stored in the frame memory.

〔Effect of the invention〕

As described above, according to the present invention, by writing and reading image data corresponding to the same line using the line memory and reading data stored in the frame memory corresponding to this line, two pieces of image data can be read. This is extremely useful in practice, since it is possible to reduce memory capacity by realizing synthesis using line memory and frame memory.

[Brief explanation of drawings]

Figure 1 is a principle block diagram of the image synthesis method of the present invention, Figure 2
The figure is a block diagram of an embodiment of the present invention, Figures 3 and 4 are explanatory diagrams of the operation timing of the embodiment, Figure 5 is a block diagram of an application example of the embodiment, and Figure 6 is image synthesis. FIG. 7 is a configuration diagram of a conventional example. In the figure, 111 is a line memory, 121 is a frame memory, 131 is a combining means, 211 is a combining control unit, 221.261 is a separation circuit, 231.271 is a phase locked loop (PLL) 241.2
43.245 is line memory, 281.283,285
291 is a frame memory, 291 is a synthesis section, 511 is a display control section, 513 is a character generation section, 515 is a graphic generation section, and 521 is a display section. Δ≦/S Sun/Moon phrase Fabrication diagram Figure 1 Lie/End ν Kui 7 Memory frame No. 7 ν (a an (b)

Claims (1)

[Claims] (1) First image data synchronized with the first horizontal and vertical synchronization signals H1 and V1 is input, and one line of this image data is stored in synchronization with the first horizontal synchronization signal H1, A line memory (111) that outputs the stored image data in synchronization with the first horizontal synchronization signal H1, and second image data synchronized with the second horizontal and vertical synchronization signals H2 and V2 are input, This image data for one screen is stored in synchronization with the second horizontal and vertical synchronization signals H2 and V2, and the stored image data is also stored in synchronization with the first horizontal and vertical synchronization signals H1 and V1. A frame memory (121) to output, the line memory (111) and the frame memory (
The first and second image data outputted from 121) are input to a compositing means (131) for composing the image data.
), and an image composition method characterized by comprising: