JPH03261238A - Alarm detection circuit for bit error rate - Google Patents

Abstract

PURPOSE:To use only one counter circuit for counting bit errors by providing a circuit selecting a setting value of bit errors of plural stages depending on alarm detection result in a bit error rate. CONSTITUTION:The circuit is provided with a bit error count means 3 detecting a bit error of an input data signal, comparing it with a threshold level of any of plural stages of bit error rate threshold levels and outputting a propriety discrimination signal. Moreover, a switching means 6 receiving the discrimination signal, selecting plural stages of bit error threshold levels and switching them and an alarm display means 5 for a bit error rate corresponding to the threshold level selected at that point of time are provided. That is, the setting value of the plural stages of bit error threshold levels is decided and an alarm of a new bit error rate up-dated at all times is displayed and the relevant bit error is counted. Thus, the count for plural stages of bit errors is implemented by using only one counter circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bit error rate alarm detection circuit in a wireless transmitter/receiver system.

[Conventional technology]

Conventional bit error rate alarm detection circuits count the bit error rate of input data, compare it with a predetermined fixed bit error alarm setting value, and display an alarm if the bit error is worse than this setting value. do. Furthermore, when changing alarm settings for different bit errors, bit error alarm detection was performed by operating a switch or the like to switch to one of multiple bit error alarm detection circuits with different bit error setting values. .

[Problem to be solved by the invention]

The above-mentioned conventional bit error alarm detection circuit has a drawback in that a plurality of alarm detection circuits are prepared and one of them is selected by a switch, so that the alarm cannot be detected based on the selected setting value.

Therefore, a counting circuit having a plurality of bit error rate setting values is required, resulting in an increase in the number of circuits.

[Means to solve the problem]

The bit error rate alarm detection circuit of the present invention is a bit error rate alarm detection circuit for determining the quality of a data signal in a wireless transmitter/receiver system.
a bit error counting means for detecting a bit error in the input data signal, comparing it with a bit error rate threshold of one of a plurality of stages, and outputting a pass/fail judgment signal; a switching means for selecting and switching a plurality of bit error rate thresholds;
and alarm display means for the bit error rate corresponding to the threshold selected at that time.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The embodiment shown in FIG. 1 includes an input terminal 1 for inputting data, a bit error detection section 2 for input data, a bit error counting section 3 for inputting detected error pulses and counting the error pulses, and a bit error counting section 3 for inputting detected error pulses and counting the error pulses. If the counted error pulses have more errors than a predetermined set value, the counting unit 3 returns N.

Pulse 10. If it is less, YES pulse 11 is output. A bit error rate recognition unit 4 that recognizes the error rate by inputting this No pulse 10 or YES pulse 11, a set value switching unit 6 that changes the aforementioned set value, and an alarm display that displays an alarm when No pulse 10 has many bit errors. It consists of part 5.

Next, the operation of this embodiment will be explained. Bit error counter 3
does not detect any bit errors, so when the bit error rate recognition unit 4 receives the No pulse 10, it activates the alarm setting for the lowest bit error rate, and the alarm display unit 5 activates the alarm setting for the lowest bit error rate. Display alarms. On the other hand, the setting switching unit 6 increases the bit error alarm setting by one level, and the bit error counting unit 3
Now let's start counting for the new settings. After this, the bit error rate recognition unit 4 receives another N.

When pulse 10 is input, the second lowest bit error alarm setting is activated, and the alarm display section displays the alarm for the second lowest bit error rate. The setting switching section 6 raises the bit error alarm setting one step higher. At this stage, the bit error rate recognition unit 4
When the YES pulse 11 is input to , the previously activated bit error alarm is canceled and the alarm display section 5
Turns off the display of the next lower bit error alarm. Next, the setting switching section 6 lowers the bit error alarm setting by one level, and the bit error counting section 3 starts counting for the new setting. In this way, setting values for bit errors in multiple stages can be determined, and an alarm display of a new bit error rate that is constantly updated can be displayed, and the corresponding bit errors can be counted.

〔Effect of the invention〕

As explained above, the present invention provides a circuit that switches the bit error setting values of multiple stages according to the bit error rate alarm detection result, thereby displaying the bit error alarm at that point in time, and displaying the bit error alarm that is newly activated. This has the advantage that a single counting circuit can perform the bit error counting operation based on the bit error setting value.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 1... Input terminal, 2... Bit error detection section, 3.
. . . Bit error counter, 4. Bit error rate recognition section, 5. Alarm display section, 6. Setting value switching section.

Claims (1)

[Claims] 1. In a bit error rate alarm detection circuit for determining the quality of a data signal in a wireless transmitting/receiving device system, detecting a bit error in the input data signal and detecting a bit error in any one of a plurality of stages. a bit error counting means for outputting a pass/fail judgment signal by comparing it with a rate threshold; a switching means for receiving the judgment signal and selecting and switching the plurality of bit error rate thresholds; and a point in time. 1. A bit error rate alarm detection circuit, comprising a bit error rate alarm display means corresponding to a threshold value selected in . 2. The counting means stores a plurality of bit error rate thresholds, and performs a plurality of determination operations in which one of the stored thresholds is selected by a control signal of the switching means. 2. The bit error rate alarm detection circuit according to claim 1, wherein the bit error rate alarm detection circuit is incorporated into one circuit.