JPH0326121A - Modulation degree control circuit when frequency modulation panel is not mounted - Google Patents

Modulation degree control circuit when frequency modulation panel is not mounted

Info

Publication number
JPH0326121A
JPH0326121A JP16119689A JP16119689A JPH0326121A JP H0326121 A JPH0326121 A JP H0326121A JP 16119689 A JP16119689 A JP 16119689A JP 16119689 A JP16119689 A JP 16119689A JP H0326121 A JPH0326121 A JP H0326121A
Authority
JP
Japan
Prior art keywords
panel
sub
modulation
signal processing
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16119689A
Other languages
Japanese (ja)
Inventor
Yoshiaki Seki
良明 関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16119689A priority Critical patent/JPH0326121A/en
Publication of JPH0326121A publication Critical patent/JPH0326121A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To execute a control so that the characteristic deterioration of a main signal cannot be generated when a subsignal processing panel is inserted into a device by varying the resistance of a subsignal path through the use of a control circuit. CONSTITUTION:When a subsignal processing panel 5 is pulled out from a frequency modulation panel 1, a connection from the subsignal processing panel 5 to a modulation control part 4a is disconnected at a connecting point A and a connecting point B, the resistance value of a variable resistance 41a is made into an infinite open condition, and thus, an amplification degree A of an amplifier 42a is lowered. When the subsignal processing panel 5 is inserted, the connection to the modulation control part 4a is restored, a bias current flows from a d.c. voltage to a fixed resistor R4 and a fixed resistor R3, the variable resistance 41a is made into an ordinary resistance value by a d.c. bias from a control circuit 43a, the amplification degree A of the amplifier 42a is returned to a normal value, and a signal at a normal value is outputted from the modulation control part 4a. consequently, a normal modulated signal is outputted from a main signal phase modulator 2.

Description

【発明の詳細な説明】 〔{既  要〕 ディジタル多重無線装置の変調度制御回路、特に副信号
処理パネルの差し込み時における副信号のレベル制1卸
回路に関し、 副信号処理パネルが装置に差し込まれたとき、主信号の
特性劣化が発生しないような変調度制御回路を提供する
ことを目的とし、 外部からの音声等を増幅した副信号を出力する副信号処
理パネルと、外部からの主信号を前記副信号処理パネル
からの副信号と共に主信号位相変調器に加えることによ
り変調信号を送出する周波数変調パネルにおいて、前記
周波数変調パネルの副信号の接続点において、一端は直
流電圧を印加しかつ他端は前記接続.点を介して前記副
信号処理パネルの内部でアースを行い、前記副信号処理
パネルが周波数変調パネルに接続されているか否かの検
知を行ったバイ了ス電圧を出力すると共に、副信号処理
パネルを周波数変調パネルに接続した際に接続点に生じ
た急激な電位茅変化が吸収する制御を行うバイアス制御
手段と,前記バイアス制御手段からのバイアス電圧が加
えC“ノれることにより抵抗値の可変制御を行う抵抗可
変手段と、前記抵抗司変手段に接続されてお的、前記副
信号処理パネルが実装1へれていない場0・において前
記電圧制御水晶発振器に加わるj{τ.力電圧が小さく
なるように増幅する増幅度可変手段とを有した変調度制
御手段を設けた構或にする。
[Detailed Description of the Invention] [{Already required] Regarding a modulation degree control circuit of a digital multiplex radio device, particularly a level control circuit for a sub signal when a sub signal processing panel is inserted, the sub signal processing panel is inserted into the device. In order to provide a modulation degree control circuit that does not cause characteristic deterioration of the main signal when the main signal is In a frequency modulation panel that sends out a modulated signal by adding it to a main signal phase modulator along with a sub signal from the sub signal processing panel, one end applies a DC voltage and the other Connect the ends as described above. The sub-signal processing panel is grounded through a terminal, and the sub-signal processing panel outputs a bypass voltage that detects whether or not it is connected to the frequency modulation panel. a bias control means for controlling to absorb the sudden change in potential that occurs at the connection point when the is connected to a frequency modulation panel; and a bias voltage from the bias control means is applied and the resistance value is varied by A resistance variable means for performing control, and a target connected to the resistance variable means, when the sub signal processing panel is not connected to the mounting 1, the j{τ. The structure is provided with a modulation degree control means having amplification degree variable means for amplifying the signal so as to decrease the amplification degree.

(産業上の利用分野〕 本発明{・よ、ディジクル多重無線装置の変調度制御回
路、特に副信号処T1パネルの差し込み時における副信
号のレベル制御回路に関1る。
(Industrial Application Field) The present invention relates to a modulation degree control circuit for a digital multiplex radio device, and particularly to a sub signal level control circuit when a sub signal processing T1 panel is inserted.

?従来の技拝〕} 第4図は従来例(・)一実施例のllIj′l路構成を
′;jクす図である。図中、1は周波数変調・″ニネル
、2 f;l: ,:t. {’?.i号位相変#JR
器、3は電圧制御水晶発振器、まノ、;、5は副信号増
幅器51を有し,た剰信号処理パネルである。
? Conventional Techniques] Figure 4 is a diagram showing the path configuration of a conventional example (-). In the figure, 1 is frequency modulation/''9, 2 f;l: , :t.{'?.i phase change #JR
3 is a voltage controlled crystal oscillator; 5 is an additional signal processing panel having a sub-signal amplifier 51;

ディジタル無線装■においては、パルス変調された所謂
PCMデータの土信号と、音声信号等の増幅+−,た副
信萼を司汀[制御水晶発振器3に加えて得らねた被変調
周波数信号とを主信号位相変調器26こ加え、主信号を
副信号6、′よる位相変調を行,た変調信号を出力する
ようにしている。
In the digital radio system (2), the pulse-modulated so-called PCM data signal, the amplification of audio signals, etc., and the control of sub-signals (modulated frequency signals obtained in addition to the control crystal oscillator 3) are used. A main signal phase modulator 26 is added to perform phase modulation of the main signal by the sub signals 6 and ′, and a modulated signal is output.

このような場合、J′!′1波数変調パネル1が前記デ
ィジタル無線装置に差し込むとき、接続点八に電位差を
生じる。この接続yF.z、八の電位差があるため、電
圧制御水晶発振器3に加わる過度電圧となり、従って電
圧制御水晶発振器3の出力位相に急激なる変動を生し、
これにより主信号位相変調器2の出力の位相が瞬時にお
いて大きな変動を生じる原因になる。
In such a case, J′! '1 When the wave number modulation panel 1 is inserted into the digital radio device, a potential difference is generated at the connection point 8. This connection yF. Since there is a potential difference between z and 8, a transient voltage is applied to the voltage controlled crystal oscillator 3, which causes a sudden fluctuation in the output phase of the voltage controlled crystal oscillator 3.
This causes instantaneous large fluctuations in the phase of the output of the main signal phase modulator 2.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従って、変調信号に位相変動が生しるために受信系での
復調に影響を受け、受信するとき例えばビソトエラーが
発するという問題がある。
Therefore, since phase fluctuations occur in the modulated signal, it is affected by demodulation in the receiving system, and there is a problem that, for example, a bisoto error occurs during reception.

本発明は、周波数変調処理パネルが装置に差し込まれた
とき、主信号の特性劣化が発生しないような変調度制御
回路を提供することを目的とする[課題を解決するため
の手段] 本発明では第1図に示すように、外部からの音声等を増
幅した副信号を出力する副信号処理バネル5と、外部か
らの主信号を前記副信号処理パネル5からの副信号と共
に主信号位相変調器2に加えることにより変調信号を送
出する周波数変調バネルJにおいて、前記周波数変調パ
ネル玉の副信号の接続力におし・て、一端は直瀦電圧を
印加しかつ他端は前記接続点を介しでj111記副信号
処理バ不ル5の内部でアースろ“行い、前記副信号処理
ペイ5ル5が周波数変調バネノ)・1に接続されている
か否かの検知を行ったバイアス電圧を出力すると共に、
副信号処理バネル5をl,;J波数変調バネル1に接続
した際に接続点に生じた急激な電位差変化が吸収する制
御を行うバイアス制′4?jJI′f−段43と、前記
ハイアス制御手段43からI2)バイアス電圧が加えら
れることにより抵抗値の可変制御を行・う抵抗可変手段
41と、m記抵抗可変千段4Iに接続されており,,前
記副信号処理バネル5が実装されでし・ない場合Cこお
いて前記電圧制御水晶発j&器3に加わる出力電圧が小
さくなるように増幅する増幅度何変手段42と、を有し
7た変調度制御千段4を設4ノた横或乏するものである
An object of the present invention is to provide a modulation degree control circuit that does not cause characteristic deterioration of a main signal when a frequency modulation processing panel is inserted into a device. As shown in FIG. 1, there is a sub-signal processing panel 5 that outputs a sub-signal obtained by amplifying external audio, etc., and a main signal phase modulator that outputs the main signal from the outside together with the sub-signal from the sub-signal processing panel 5. In the frequency modulation panel J, which sends out a modulated signal by adding a signal to Grounding is performed inside the sub-signal processing panel 5, and the bias voltage detected as to whether or not the sub-signal processing panel 5 is connected to the frequency modulation spring 5 is output. With,
Bias control '4? which performs control to absorb the sudden potential difference change that occurs at the connection point when the sub signal processing panel 5 is connected to the L, J wave number modulation panel 1. jJI'f- stage 43, the high-ass control means 43 is connected to the resistance variable means 41 which performs variable control of the resistance value by applying a bias voltage, and the m number of resistance variable stages 4I. ,, if the sub-signal processing panel 5 is not mounted, it has an amplification degree varying means 42 for amplifying so that the output voltage applied to the voltage-controlled crystal oscillator 3 is reduced. 7 and 4 stages of modulation depth control are provided.

〔作 用〕[For production]

本発明では第1図に示す如く、、電圧制御水晶発振器3
の入力側に設けた変調度制御千段4において、バイアス
制御千段43の一端に直流電圧を印加しかつ他端を接続
点を介して副信号処理バネル5の内部においてアースを
し、またバイアス制御千段43により前記副信号処理パ
ネル5が周波数変調バネル1に接続されているか否かの
検知動作を行ったバイアス電圧を出力するとともに、副
信号処理バネル5を周波数変調パネル■に接続したとき
接続点に生じる急激な電位差の変化が吸収されるように
制御を行い、更にこのバイアス電圧を抵抗可変手段41
に加えて副信号路の抵抗を変化させて増幅可変千段42
に接続するようにしている。
In the present invention, as shown in FIG.
In the modulation level control stage 4 provided on the input side of When the control stage 43 outputs a bias voltage that detects whether or not the sub signal processing panel 5 is connected to the frequency modulation panel 1, and the sub signal processing panel 5 is connected to the frequency modulation panel ■. Control is performed so that a sudden change in potential difference occurring at the connection point is absorbed, and this bias voltage is further controlled by the resistance variable means 41.
In addition to that, by changing the resistance of the sub signal path, a variable amplification stage of 42
I am trying to connect to.

従って、この抵抗可変千段4lの抵抗の変化により増幅
度可変千段42の増幅度を可変できるため、副信号処理
バネル5が装置に差し込まれたときにおいて生じる急激
な位相変動を抑圧し、受信信号の特性劣化が発生しない
ような変調度制御回路の提供が可能となる。
Therefore, since the amplification degree of the variable amplification level 42 can be varied by changing the resistance of the variable resistance stage 4l, the sudden phase fluctuation that occurs when the sub signal processing panel 5 is inserted into the device is suppressed, and the reception It is possible to provide a modulation degree control circuit that does not cause signal characteristic deterioration.

〔実 施 例〕〔Example〕

第2図は本発明の一実施例の回路横或を示す図である。 FIG. 2 is a diagram showing the layout of a circuit according to an embodiment of the present invention.

図中、1は周波数変調パネルであり、従来例と同一の主
信号位相変調器2と電圧制御水晶発振器3及び変調制御
部4aからなる回路である。
In the figure, 1 is a frequency modulation panel, which is a circuit consisting of a main signal phase modulator 2, a voltage controlled crystal oscillator 3, and a modulation control section 4a, which are the same as in the conventional example.

なおこの変調制御部4aは本発明の変調度制御千段4に
対応しており、その回路構或は可変抵抗手段4lとして
の可変抵抗41a,固定抵抗器R1と、増幅度可変千段
42としての増幅器42a,固定抵抗器R2と、バイア
ス制御千段43としての固定抵抗器R3R,および静電
容量C,よりなる制御回路43aを有した回路である。
This modulation control section 4a corresponds to the 1,000-stage modulation degree control 4 of the present invention, and its circuit structure includes a variable resistor 41a as the variable resistance means 4l, a fixed resistor R1, and a 1,000-stage variable amplification level 42. This circuit has a control circuit 43a consisting of an amplifier 42a, a fixed resistor R2, a fixed resistor R3R as a bias control stage 43, and a capacitance C.

なお5は従来例と同一の副信号増幅器51を有した副信
号処理パネルである。更に接続点Aは音声等の入力側と
なる接続点、接続点Bは一端を制御回路43aに接続し
かつ他端をアースすることによりハイアス電圧を生戒ず
る接続点である。
Note that 5 is a sub-signal processing panel having the same sub-signal amplifier 51 as in the conventional example. Furthermore, the connection point A is a connection point that becomes the input side for audio, etc., and the connection point B is a connection point that connects one end to the control circuit 43a and earths the other end to prevent high-ass voltage.

副信号処理バネル5が周波数変調バネル1から抜かれて
いる場合、副信号処理バネル5から変調制御部4aへの
接続が接続点Aと接続点Bで断たれる。接続点l3が断
たれると、制御回路43aに加えられている直流電圧よ
り固定抵抗器R4と固定抵抗器R3を介して流れるバイ
アス電流が流れなくなって可変抵抗41aの抵抗値は無
限大のオゾン状態になり、これにより増幅器42aの増
幅度Aは低下するようなる。即ち、接続点Aを介して電
圧制御水晶発振器3に加わる人力のレベルを低下させて
接続点Aと接続点Bの断にする事によって生しる異常電
圧の発生を抑さえている。
When the sub-signal processing panel 5 is disconnected from the frequency modulation panel 1, the connection from the sub-signal processing panel 5 to the modulation control section 4a is cut off at connection point A and connection point B. When the connection point l3 is disconnected, the bias current flowing through the fixed resistor R4 and the fixed resistor R3 stops flowing due to the DC voltage applied to the control circuit 43a, and the resistance value of the variable resistor 41a becomes infinite ozone. This causes the amplification degree A of the amplifier 42a to decrease. That is, the level of human power applied to the voltage controlled crystal oscillator 3 via the connection point A is reduced, and the generation of abnormal voltage caused by disconnecting the connection points A and B is suppressed.

また一方、副信号処理バネル5が挿入されると変調制御
部4aへの接続が復旧し、直流電圧から固定抵抗器R4
と固定抵抗器R,にバイアス電流が流れ、可変抵抗41
aは制御回路43aからの直流ハイアスにより通常の抵
抗値となり、増幅器42aの増幅度Aは正常値に戻り変
調制御部4aからは正常な値の信号が出力される。従っ
て主信号位相変調器2からは正常な変調信号が出力され
る。
On the other hand, when the sub signal processing panel 5 is inserted, the connection to the modulation control section 4a is restored, and the fixed resistor R4 is connected to the DC voltage.
A bias current flows through the fixed resistor R, and the variable resistor 41
a becomes a normal resistance value due to the direct current high-ass from the control circuit 43a, the amplification degree A of the amplifier 42a returns to the normal value, and a signal with a normal value is output from the modulation control section 4a. Therefore, the main signal phase modulator 2 outputs a normal modulated signal.

この過程で制御回路43aは、固定抵抗器R,と固定抵
抗器R4と静電容量C1よりなる遅延要素を持っており
、非常に細いパルスを吸収するようにしてある。これに
より瞬時変動に対して追従しないようにして回路動作の
安定化を図っている。
In this process, the control circuit 43a has a delay element consisting of a fixed resistor R, a fixed resistor R4, and a capacitance C1, and is designed to absorb very thin pulses. This stabilizes the circuit operation by preventing it from following instantaneous fluctuations.

なお、第3図は本発明の一実施例回路のタイムチャート
を示す図である。図示するように、周波数変調パネル1
の抜き取り時の増幅度A1は、R. 一方周波数変調バネルlの挿入時の増幅度A2は、R,
     VR 即ち、Az>A+が得られる。
Incidentally, FIG. 3 is a diagram showing a time chart of a circuit according to an embodiment of the present invention. As shown, frequency modulation panel 1
The amplification degree A1 at the time of extraction of R. On the other hand, the amplification degree A2 when inserting the frequency modulation panel l is R,
VR, that is, Az>A+ is obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、副信号路の抵抗を
制j卸回路を用いて可変させることにより、副信号処理
パネルが装置に差し込まれたときの主信号の特性劣化の
発生しないように制御することが可能となり、安定な周
波数変調度制御回路が実現できる。
As explained above, according to the present invention, by varying the resistance of the sub-signal path using a control circuit, it is possible to prevent the characteristics of the main signal from deteriorating when the sub-signal processing panel is inserted into the device. Therefore, a stable frequency modulation degree control circuit can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理構威を示す回路図、第2図は本発
明の一実施例の回路構成を示す図、第3図は本発明の一
実施例回路のタイムチャートを示す図、 第4図は従来例の一実施例の回路構戒を示す図、ある。 図において、 ■は周波数変調パネル、 2は主信号位相変調器、 3は電圧制御水晶発振器、 4は変調度制御手段、 41は抵抗可変手段、 42は増幅度可変手段、 43はバイアス制御手段、 5は副信号処理パネル、 を示す。 本発明の一実施例のIl!lIl3構威を示す図第2図 時間t−p 本発明の一実施例回路のタイムチャートを示す図第 3
 図 本発明の原理構戊を示す図 従来例の一実施例の回路構威を示す図 第4図
FIG. 1 is a circuit diagram showing the principle structure of the present invention, FIG. 2 is a diagram showing a circuit configuration of an embodiment of the invention, and FIG. 3 is a diagram showing a time chart of the circuit of an embodiment of the invention. FIG. 4 is a diagram showing the circuit configuration of an embodiment of the conventional example. In the figure, ■ is a frequency modulation panel, 2 is a main signal phase modulator, 3 is a voltage controlled crystal oscillator, 4 is modulation degree control means, 41 is resistance variable means, 42 is amplification degree variable means, 43 is bias control means, 5 indicates a sub-signal processing panel. Il! of one embodiment of the present invention! Figure 2 shows the structure of the circuit. Time t-p. Figure 3 shows the time chart of the circuit according to an embodiment of the present invention.
Figure 4 shows the principle structure of the present invention Figure 4 shows the circuit structure of an embodiment of the conventional example

Claims (1)

【特許請求の範囲】 外部からの音声等を増幅した副信号を出力する副信号処
理パネル(5)と、外部からの主信号を前記副信号処理
パネル(5)からの副信号と共に主信号位相変調器(2
)に加えることにより変調信号を送出する周波数変調パ
ネル(1)において、前記周波数変調パネル(1)の副
信号の接続点において、一端は直流電圧を印加しかつ他
端は前記接続点を介して前記副信号処理パネル(5)の
内部でアースを行い、前記副信号処理パネル(5)が周
波数変調パネル(1)に接続されているか否かの検知を
行ったバイアス電圧を出力すると共に、副信号処理パネ
ル(5)を周波数変調パネル(1)に接続した際に接続
点に生じた急激な電位差変化が吸収する制御を行うバイ
アス制御手段(43)と、前記バイアス制御手段(43
)からのバイアス電圧が加えられることにより抵抗値の
可変制御を行う抵抗可変手段(41)と、 前記抵抗可変手段(41)に接続されており、前記副信
号処理パネル(5)が実装されていない場合において前
記電圧制御水晶発振器(3)に加わる出力電圧が小さく
なるように増幅する増幅度可変手段(42)と、 を有した変調度制御手段(4)を設けたことを特徴とす
る周波数変調パネルの非実装時の変調度制御回路。
[Claims] A sub-signal processing panel (5) that outputs a sub-signal obtained by amplifying external audio, etc.; Modulator (2
), at the connection point of the sub-signal of the frequency modulation panel (1), one end applies a DC voltage and the other end applies a DC voltage via the connection point. The sub signal processing panel (5) is grounded inside, and the sub signal processing panel (5) outputs the bias voltage used to detect whether or not it is connected to the frequency modulation panel (1). a bias control means (43) that performs control to absorb a sudden potential difference change that occurs at the connection point when the signal processing panel (5) is connected to the frequency modulation panel (1); and the bias control means (43).
) is connected to the resistance variable means (41) for variable control of the resistance value by applying a bias voltage from the auxiliary signal processing panel (5). amplification degree variable means (42) for amplifying so that the output voltage applied to the voltage-controlled crystal oscillator (3) becomes small when the voltage-controlled crystal oscillator (3) is not present; and a modulation degree control means (4) having the following: Modulation degree control circuit when a modulation panel is not installed.
JP16119689A 1989-06-23 1989-06-23 Modulation degree control circuit when frequency modulation panel is not mounted Pending JPH0326121A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16119689A JPH0326121A (en) 1989-06-23 1989-06-23 Modulation degree control circuit when frequency modulation panel is not mounted

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16119689A JPH0326121A (en) 1989-06-23 1989-06-23 Modulation degree control circuit when frequency modulation panel is not mounted

Publications (1)

Publication Number Publication Date
JPH0326121A true JPH0326121A (en) 1991-02-04

Family

ID=15730413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16119689A Pending JPH0326121A (en) 1989-06-23 1989-06-23 Modulation degree control circuit when frequency modulation panel is not mounted

Country Status (1)

Country Link
JP (1) JPH0326121A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5810526A (en) * 1995-07-18 1998-09-22 Dainippon Screen Mfg. Co., Ltd. Lubricant application apparatus in a gravure engraving machine
US6690032B1 (en) 1999-07-22 2004-02-10 Seiko Epson Corporation Electro-optical device and method of manufacture thereof, and electronic instrument
US6720944B1 (en) 1998-07-27 2004-04-13 Seiko Epson Corporation Electro-optical device, method of manufacturing same, projector and electronic apparatus
US6741315B1 (en) 1999-08-27 2004-05-25 Seiko Epson Corporation Liquid crystal device and electronic apparatus
US6894758B1 (en) 1999-03-08 2005-05-17 Seiko Epson Corporation Liquid crystal device and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5810526A (en) * 1995-07-18 1998-09-22 Dainippon Screen Mfg. Co., Ltd. Lubricant application apparatus in a gravure engraving machine
US6720944B1 (en) 1998-07-27 2004-04-13 Seiko Epson Corporation Electro-optical device, method of manufacturing same, projector and electronic apparatus
US6894758B1 (en) 1999-03-08 2005-05-17 Seiko Epson Corporation Liquid crystal device and manufacturing method thereof
US6690032B1 (en) 1999-07-22 2004-02-10 Seiko Epson Corporation Electro-optical device and method of manufacture thereof, and electronic instrument
US6741315B1 (en) 1999-08-27 2004-05-25 Seiko Epson Corporation Liquid crystal device and electronic apparatus

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