JPH03261179A - Insulated gate type bipolar transistor - Google Patents

Abstract

PURPOSE:To make a current of a bipolar transistor to be driven by many parallel-connection MOSFETs uniform in a semiconductor element surface by burying a slender low resistance region in an intermediate part of a thickness direction of a high resistance layer in contact with a base region to be equal potential. CONSTITUTION:A longer low resistance region 1 than a width is selectively formed at a deeper intermediate part than a plurality of first conductivity type first regions 5 in a thickness direction of a second conductivity type second layer 2. The layer 2 in contact with the base region of a bipolar transistor has a high resistance, but a slender low resistance region 11 exists therein, and the region 11 becomes the same potential at any part. Thus, an irregularity in the potential of the base region is eliminated to reduce irregular current of the transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate bipolar transistor (hereinafter abbreviated as ICRT) having multiple MO5 structures on one surface of one semiconductor body.

[Conventional technology]

The IGBT supplies the base current of a bipolar transistor from a MOSFET formed on its surface. FIG. 2 shows the structure of an n-channel type GBT, and the p-channel type has the same structure except that the conductivity types of each part are reversed. This structure is formed as follows. A p゛ epitaxial layer 2 is formed on the silicon plate 1, and an n-epitaxial layer 2 is formed on the silicon plate 1.
A gate electrode 4 is provided on the surface of the substrate with a gate insulating layer 3 interposed therebetween.

When a p- impurity diffusion region 5 is formed on the surface of the n-epitaxial layer 2 using this gate electrode 4 as a mask, the portion where this p- impurity diffusion region 5 contacts the gate insulating layer 3 becomes a channel region 6. - selectively forming n impurity diffusion regions 7 in impurity diffusion regions 5; After selectively masking the surface of gate electrode 4 with glabellar insulating layer 8, emitter electrode 9 is formed so as to be in contact with p- impurity diffusion region 5 and n° impurity diffusion region 7. On the other hand, a collector electrode 10 is formed on the surface of the p' type substrate l.

To drive such an IGBT, the emitter electrode 9
is grounded, a positive voltage is applied to the collector electrode 10, and a positive input signal is applied to the gate electrode 4. As a result, the channel portion 6 is inverted from p-type to n-type, the MOSFET operates, and the electron current 1e is transferred to the emitter electrode 9. n゛Impurity diffusion region 7
．． This n-epitaxial layer 2 flows into the n-epitaxial layer 2 through the channel part 6, and the n-epitaxial layer 2 flows between the p'substrate 1 and the p'
- This corresponds to the base region of the PNP type bipolar transistor consisting of the impurity diffusion region 5, and the potential of the base region falls to the potential of the emitter electrode 9 due to this electron current Ie, so that the PNP type bipolar transistor operates,
Hall current 1h is the collector electrode 10. p” substrate 1+n-
It flows through the epitaxial layer 2°p- impurity diffusion region 5 to the emitter electrode 9.

I In order to increase the current capacity of GBT, the electron current I
It is necessary to supply s over the entire surface of the semiconductor element, and for this purpose, a large number of MO3 structures are formed on one surface of one semiconductor element, and the MOS FET cells are connected in parallel.

[Problem to be solved by the invention]

The characteristics of a large number of MOSFET cells formed in one semiconductor body are determined by variations in the semiconductor crystal of the n- impurity diffusion layer 2, p- impurity diffusion region 5. If there are variations in the wafer process for the gate insulating layer, or variations in the structure or arrangement of individual cells due to design reasons, not only Ie but also Ih will become non-uniform within a single semiconductor element, causing both Variation in the overall current due to the sum of the currents is promoted.

Since the n-epitaxial layer 2 is made to have a high resistance in order to provide the withstand voltage of the element, it is difficult to alleviate variations in potential in the pronation of this layer.Such variations in current can be prevented by effectively using the area of the element body. Not only will this result in failure, but it may also cause deterioration or destruction of the device.

The object of the present invention is to eliminate the above-mentioned drawbacks and to solve the problem of parallel-connected MOS
An object of the present invention is to provide an IGBT in which the current in the plane of the base region of a bipolar transistor section has little variation even if the characteristics of FET cells vary.

[Means to solve the problem]

In order to achieve the above object, the present invention has a second layer of a second conductivity type adjacent to one side of the first layer of the first conductivity type, and a surface portion of the second layer on the side opposite to the second layer. A plurality of first regions of the first conductivity type are selectively formed, and a second region of the second conductivity type is selectively formed on the surface portion of the first region, and the exposed portion of the second layer is formed on the surface of the second layer. A gate electrode is provided on the first region sandwiched between the second regions via an insulating layer, an emitter electrode is in common contact with the first and second regions, and a collector electrode is in common contact with the second layer. In IC and BT where electrodes are connected in parallel,
It is assumed that a low resistance region having a longer length than width is selectively formed in an intermediate portion deeper than the -th region in the storage direction of the second layer.

[Effect]

The second layer, which corresponds to the base region of the bipolar transistor, has high resistance, but there is an elongated low resistance region within it.
Since all parts of that region have the same potential, variations in the potential of the base region are eliminated, and non-uniformity in the current of the bipolar transistor can be reduced. However, if this low-resistance region is formed as a low-resistance layer over the entire surface, the depletion layer will not grow at that position when voltage is applied between the emitter and collector electrodes, which may cause deterioration in breakdown voltage. If a low-resistance region is selectively formed, the depletion layer will spread easily in high-resistance areas where there is no low-resistance region, so it will extend further and eventually surround the low-resistance region, and no breakdown voltage deterioration will occur at that location. .

〔Example〕

FIG. 1 shows a cross-sectional structure of an IGBT according to an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. The difference with Fig. 2 is obvious; the n epitaxial layer 2
A strip-shaped low resistance region 11 is embedded at an intermediate position in the thickness direction. Fig. 3 fa) (bl, (C1 shows an example of the formation process of such a low resistance region 11 with a breakdown voltage of 1200V.
1. Grow an n-epitaxial silicon layer 21 of I. The resistivity of the n- layer 21 is 1000, and as shown in FIG. As impurity ions,
It is desirable to use arsenic to suppress spreading in the subsequent diffusion step.

Next, as shown in FIG. 3 (bl), an n- epitaxial layer 22 with the same impurity concentration is deposited on the n- layer 21, and the implanted impurity 13 is deposited to make the total thickness of the layer 2 100-.
will be slightly diffused in the subsequent impurity diffusion process for forming the p-Ml region 5 or n'' region 7, but if necessary, thermal diffusion or annealing may be performed at this point to form the third
As shown in FIG. 1, an n low resistance region 11 may be formed.

Since it is desirable that the entire surface of the semiconductor element be at the same potential, the low resistance region 11 is formed into a pattern as long as possible. For this purpose, a strip pattern is formed as shown by hunting in FIG. 4, or a grid pattern is formed by connecting strip patterns as shown in FIG. 5.

FIG. 6 shows another embodiment in an n-channel ICRT, in which the low resistance region 12 formed in the middle of the n-epitaxial layer 2 is a p° impurity diffusion region. However, the potential equalization effect was the same as in the case of FIG. As can be seen from this embodiment, the present invention is applicable to p-channel IGB
The same can be done with T.

〔Effect of the invention〕

The present invention provides a bipolar transistor driven by a large number of parallel-connected MO3FETs by embedding an elongated low-resistance region in the middle part of the high-resistance layer in the thickness direction, which corresponds to the base region of the bipolar transistor part of the IGBT, to achieve equal potential. The current can be made uniform within the plane of the semiconductor element, and the area of the element can be used effectively without reducing the withstand voltage. Furthermore, since concentration of current in one part is suppressed, it is effective in preventing deterioration and destruction of the element.

[Brief explanation of drawings]

FIG. 1 is a perspective sectional view of an IGBT according to an embodiment of the present invention;
FIG. 2 is a perspective sectional view of a conventional IGET, and FIG. 3 (a) shows a part of the manufacturing process of the IGBT shown in FIG. (Cross-sectional views shown in the order of bl and tel, Figures 4 and 5 are plan views showing two examples of patterns of low resistance regions according to the present invention, and Figure 6 is a perspective cross-section of semiconductor ICBTs of different embodiments of the present invention. 1: p-substrate 2: n-epitaxial layer; 3: gate insulating layer; 4: gate electrode; 5; p- impurity diffusion region; 7:
n゛impurity diffusion region, 9: emitter electrode, 10: collector electrode, 11, 12: low resistance region. IiJx人frJヱ 山 ロ Naoshige January lθ 2nd hanging 11 ↓ ... Ito/3 3rd solid Figure 4 Figure 5

Claims (1)

[Claims] 1) A second layer of a second conductivity type is adjacent to one side of the first layer of the first conductivity type, and a plurality of first regions of the first conductivity type are provided on the surface of the second layer on the side opposite to the first layer. is selectively formed, a second region of the second conductivity type is selectively formed on the surface of the first region, and a first region sandwiched between the exposed portion of the second layer and the second region is selectively formed. A gate is provided on the region via an insulating layer, an emitter electrode is in common contact with the first and second regions, a collector electrode is in contact with the first layer, and each emitter electrode is connected in parallel. An insulated gate bipolar transistor characterized in that a low resistance region that is longer than its width is selectively formed in an intermediate portion deeper than the first region in the thickness direction of the layer.