JPH0325972B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a wireless paging device, and more particularly to a paging receiver that also receives paging information at the time of paging.

〔overview〕

Conventionally, pagers and the like have had the problem of not being able to easily indicate who is calling. The present invention also takes in the call information that is input at the same time when a call number is received, determines what kind of call information it is from the call information, especially from the function data, and selects one of a plurality of musical melodies. Select to specify the alarm.
This allows the holder to recognize, for example, who is calling. [Prior Art] Conventionally, a self-paging device such as a pager operates a receiving device in a specific time unit. Then, when receiving it, it determines whether or not it has its own number,
It is determined whether there is a call from the base unit.
Generally, when making a call, for example, when a person dials the telephone number of the receiver to be called, that is, the calling number, the calling number is transmitted from the radio base station of the telephone station and detected by the calling device.

When a self-paging device such as a pager is called, the person holding the receiver, that is, the person holding the self-paging device, will be alerted by a buzzer, horn, etc. when the person is called. Recognize that. Since such pagers are called by a buzzer, horn, etc., as mentioned above, it is difficult to know what the current state of the call is, for example, is it a message to call point A or is it B? I couldn't tell whether it was a message telling me to call a certain number or whether it was some other requirement. In other words, they could only make telephone calls to fixed locations.

In recent years, as a solution to this problem, a paging receiver has been devised that is capable of transmitting and displaying not only a buzzer or horn but also a simple message at the same time. This paging receiver receives not only the above-mentioned buzzer notification but also the information following the calling number as information for the self-calling device and displays it. The display is simple, but compared to the conventional ones mentioned above, for example, compared to a pager, it not only recognizes whether a call has been made or not, but also recognizes where the call is coming from and by whom. can do.

[Problem that the invention seeks to solve]

In the above-mentioned paging receiver, a contact telephone number is also used as a message to be displayed. A person who has this self-paging device, that is, a person who has a paging receiver, recognizes the telephone number etc. that appears on the display and uses it to call the caller from the receiver. It's on. For such devices,
A display section is required, and even if the display is performed using, for example, an LCD, there is a problem in that the display is large. In particular, the more complex the information, the larger the display area, which is a major problem with devices such as pagers that must be carried at all times.

Also, in the case of LCDs, etc., if you are called at night, the display can only be read in a bright place.
Another problem is that when the recipient is in a dark place, it is impossible to determine what information is requested, that is, how the recipient should contact them.

In view of the above-mentioned conventional drawbacks, the present invention aims to provide a paging receiver that can recognize a caller's message, such as a call from Mr. A or a call from Mr. B, without looking at the display. .

[Means for solving problems]

The present invention provides, in a paging receiver having two self-calling numbers, means for selectively generating a plurality of types of melody sounds and a warning sound different from the melody sound as a means for generating a paging notification sound, and When the received called number matches the first self-called number, one of the plurality of types of melody tones is selected based on the function data added to the received called number, and the received called number is selected. When the calling number matches the second self-calling number, a selection control means is provided for selecting the warning sound regardless of the function data added to the received calling number, and the call notification is performed. This is what I did.

[Effect]

In a paging receiver having two self-calling numbers as in the present invention, one of the self-calling numbers is usually used for normal calls and the other for emergency calls, or one is used for individual calls and the other for group calls. In some cases, one is used for company use and the other for family use. Therefore, in either usage, most calls are made to one of the self-calling numbers, and calls to the other number are very rare. Moreover, most calls are made from one's own calling number, which is likely to be made by multiple people, making identification of the caller extremely important, whereas calling from another's number is Although the number of callers is limited and the identity of the caller is not very important, when this number is called, the contents of the business are relatively urgent.

The first self-calling number in the present invention is used as the self-calling number where most of the above-mentioned calls are made, and the second self-calling number is used as the other self-calling number. is as follows.

receiving a calling number, and determining whether the received calling number matches a preset first self-calling number, a second self-calling number, or any of the self-calling numbers; Determine if there is. When the received calling number matches the first self-calling number, the selection control means notifies one of the plurality of types of melody tones based on the function data added to the received calling number. Select as a sound and notify the call with the selected melody sound. Melody sounds are unpleasant to the ear, and the types of sounds (melody types) are easy to identify, so the caller can be easily identified by the melody sounds. On the other hand, when the received calling number matches the second self-calling number, the selection control means selects the warning sound as the notification sound regardless of the function data added to the received calling number. and alerts you to the call with a warning tone. Since the warning sound has excellent notification recognition, it is possible to quickly and reliably recognize that a call has been made using the second self-calling number.

〔Example〕

FIG. 1 is an external view of a paging receiver according to the present invention. FIG. 1a is a front view, FIG. 1b is a top view, and FIG. 1c is a side view. A display section 2 is provided on the front, and a display selection switch 3 and a scroll switch 4 are further provided on the right side thereof. The display section 2 has a two-tiered display, with the upper section displaying the time and the lower section displaying a message. In the embodiment of the present invention, as will be described later, messages for, for example, 30 calls can be stored, and the time at that time is also stored. In the display section 2, the content of the message is displayed at the bottom of the display section, and the time when the call request occurred is displayed at the top. Display selection switch 3
indicates which one to select from among the 30. For example, when the recipient presses this switch, a total of 30 items are displayed from the newest to the oldest. The display width of the display section 2 is very small, and messages may be larger than that. This is selected by scroll switch 4.
By pressing , you can scroll from the beginning of the message and display one line of call information if it is long.

There is a reset switch 5 and a sound emitting hole 6 on the side of the main body.
is provided. For example, a speaker or a piezoelectric element is provided inside the main unit of the sound emitting hole 6, and when the calling numbers match, an internal sound (buzzer sound) is outputted through the sound emitting hole 6. The reset switch 5 is for stopping the buzzer sound. When the switch is pressed for the first time, the sound alarm stops, and when the switch is pressed for the second time, the display on the display section 2 is cleared. A light switch 7 and a power switch 8 are provided at the top of the main body. Power switch 8
By turning on the main unit, the entire operation of the main unit starts. Further, by pressing down the light switch 7, the display lamp of the display section 2 is turned on. In a dark place, by pressing the light switch 7, the display section 2 is illuminated and the contents of the message can be read.

In the embodiment of the present invention, a speaker is provided inside the sound emitting hole 6. From this sound emitting hole 6, a melody changes according to information corresponding to the calling information, that is, according to function data, and is outputted to the outside.

FIG. 2 is a block diagram of an embodiment of the present invention.

Antenna 9 is an antenna that receives radio waves generated from the wireless base of a telephone station, for example, 280MHz.
Receive FM radio waves. This FM radio wave is modulated using the FSK signal (NRZ) method and contains information at a bit rate of 512 bits/sec. The signal received from this antenna 9 is transmitted to the radio receiving circuit 1
Add to 0. The radio receiving circuit 10 is based on the above-mentioned FSK.
This circuit demodulates the FM signal and converts it into "0" and "1" signals. This circuit naturally has a circuit that selects 280MHz, and also a demodulation circuit that demodulates the FSK signal, and this demodulated signal is transmitted to the communication control circuit 1.
Join 1. In the embodiment of the present invention, a POCSAG method is used, and the communication control circuit 11 analyzes the data of the signal applied from the radio receiving circuit 10 using this POCSAG method and determines whether it is its own calling number or is a circuit that outputs a reception signal for receiving the data to the CPU 12 when the call number is its own.
The CPU 12 detects and processes signals from the switch group 13. Also, receive data is stored in RAM (not shown).
At the same time, the data is sent to the display circuit 14 for display, and furthermore, the speaker 15 makes a sound that a call has been made.

FIGS. 3A to 3F are data configuration diagrams of the POXAG method.

Figure 3A shows the overall transmission signal format.
First, 576 bits of 101010 are sequentially followed by a preamble signal A, followed by a plurality of batch signals B, C...
...consists of more. The preamble signal is a signal for making the paging receiver recognize that data is about to be sent and for synchronization, and the communication control circuit 11 detects this preamble and recognizes that batch data will be sequentially added below.

FIG. 3B is a batch format of the above batch data. This batch has a synchronization code SC,
Next, each code consists of two words. Each code is made up of 2 words, but in the embodiment of the present invention, for example, 1 word = 32 bits, and 1 batch is made up of CD1 to CD8 blocks, making a total of 32 x 2 x 8 = 512 bytes. It's summery.

FIGS. 3C and 3D show the structure of each code that becomes the two code words mentioned above. FIG. 3C shows an address code word, which consists of a message flag at the beginning, an address code after the message flag, and further a function bit, BCH parity, and even parity. Further, FIG. 3D shows a message code word, which consists of a message flag followed by a message code, BCH parity, and even parity.

The message flag is a flag that identifies whether the next code is an address code or a message code, and when it is 0, it is an address code word,
When it is 1, it represents a message code word.
The 2nd to 19th bits after the message flag are an address code, which corresponds to the above-mentioned calling number. Furthermore, there are two function bits after this. This is a bit to indicate the display format and sound format, for example "00", "01",
There are four types of functions based on "10" and "11". In the POXAG method, an error may occur within one code, for example, an address code. In particular, if the reception condition is poor or unstable, the demodulation of the FSK signal will not be complete and errors will occur. To correct this, BCH parity is provided in bits 22 to 31. This 10
Corrects errors that occur due to bit data. This is called BCH parity. After that, an even parity bit is provided in bit 32. This even parity indicates whether the total number of bits from the beginning to the end represents the number of "1"s was an odd number or an even number. For example, if you mistake one bit for "0" and "1" By checking this even parity, it is possible to determine whether a bit has been lost or added.

In the case of the message code word shown in FIG. 3D, a message bit is added after the message flag. This includes a message from the caller, such as a telephone number and other information. Furthermore, within the same code word
BCH parity and even parity data are added to form the message code word.

In the POXAG method, the power to the wireless receiver circuit 10 is not always turned on, but only when necessary. Each paging receiver has one of blocks CD1 to CD8 in one batch.
A block is assigned, and the radio receiving circuit 10 is powered on at the time of this assigned 1 block.
shall be. A signal for detecting the position of one allocated block is a synchronization code word. The receiver turns on the power for the period of one block assigned by the synchronization code word. Note that the preamble signal is a signal for synchronizing the entire system, and if synchronization is not achieved, the power supply must be turned off to receive this signal as well.
Set to ON. FIG. 3E is a bit configuration diagram of a synchronization code word,
01111100110100100001010111011000 is its bit configuration. When the radio receiving circuit 10 receives a signal having this bit structure, it receives one block from among the subsequent blocks in the time allotted to each receiver. For example, the receiver is set to be in a receiving state at all times during the synchronization code time, and after detecting the synchronization code, the receiver repeats the code word of the block applied to its own frame, for example, during CD2 in FIG. Turn on the power and determine whether the received code word, for example, the address data shown in FIG. 3C, is your own data. If it is different, turn off the power.

On the other hand, if there is a match, the next message code word is also received and its data is taken in. The receiver turns on the power of the radio receiving circuit 10 when receiving this synchronization code and when receiving the code word of the block assigned to itself. That is, the receiver always turns on the power when the synchronization code and the block assigned to it are received in batch word units.
Note that when the power of the receiver is first turned on, the entire system is not synchronized, so the power of the radio receiving circuit 10 is periodically turned on to detect the preamble.
To summarize the above-mentioned POXAG method, when the receiver side detects a preamble, it turns on the power to the radio receiving circuit 10 when receiving the synchronization code and furthermore, when receiving the code word assigned to itself.
Set to ON.

The communication control circuit 11 performs these controls, and the radio reception circuit 10 performs a reception operation by ON/OFF control of the communication control circuit 11.

For example, if the preamble is detected and the entire system is synchronized, the synchronization code and the 8-block CD1
~Turn on the power to the radio receiving circuit 10 when the block assigned to you in CD8 is selected. In this way, the power consumption of the pager is reduced.

In the Pokusaku method, a word called an idle link codeword is provided in addition to the above-mentioned codeword. FIG. 3F is a bit configuration diagram of an idle link code word. This idle link codeword is a null code, and when this codeword is received, the page receiver is as if it did not receive any data. For example, if this idle link code word is located at the position of the synchronization code word and it is received, synchronization will be lost, and if it is present in the address code word or message code word, it will be the same as if nothing was received.

FIG. 4 shows the communication control circuit 11 in this embodiment.
FIG. 2 is a detailed circuit configuration diagram of FIG. A received signal coming in from the radio receiving circuit 10 is applied to an input synchronization circuit 21. The input synchronization circuit 21 is a circuit that corrects disturbances in the "0" and "1" signals upon demodulation of the FSK signal, and the input synchronization circuit 21 allows stable data to be taken in. The signal stabilized by the input synchronization circuit 21 is applied to a BCH error correction circuit 25, a preamble detection circuit 22, and a synchronization code detection circuit 24. Preamble detection circuit 22
is for detecting a preamble, and the detection result is added to the timing control circuit 23 by this detection. When the preamble is detected by the preamble detection circuit 22, the synchronization code detection circuit 24 operates to detect whether or not a synchronization code has been entered. The result is similarly output to the timing control circuit 23. For example, when detection is performed, a detection signal is applied to the timing control circuit 23.
The BCH error correction circuit 25 takes in all the data of the block assigned to itself in the batch format, determines whether or not there is a BCH error,
If there is any further error, it is a circuit that performs correction. When an address code is received by this circuit, the error-corrected code is first applied to the calling number detection circuit 26. The calling number detection circuit 26 includes an ID-ROM 127 that stores an ID number, and an ID-ROM 127 that stores an ID number.
A ROM 28 is connected, and the corrected code data is compared with the data from each IDROM to detect if they match. In an embodiment of the invention, each paging receiver stores a first address and a second address.
ID-ROM127 and ID-ROM28. The timing control circuit 23 has a clock that always detects the timing with respect to the synchronization code, and the transmitting side sequentially sends a preamble, batch format, and multiple batch data, so when the timing control circuit 23 detects the preamble, it detects the synchronization code. The power supply control circuit 29 is kept ON until the detection is detected. Furthermore, the power supply control circuit 29 is turned on using the code word of its own block. From the power supply control circuit 29
When the ON signal is applied, the synchronization code detection circuit 24 detects the synchronization code, and the BCH error correction circuit 25 corrects the received data.
Add to 6. The calling number detection circuit 26 identifies whether or not the caller is calling. For example, if it is not your calling number,
The process ends and the code word is detected again.

On the other hand, if it is your calling number, a reception interrupt signal is generated and the CPU in Figure 2
Add an interrupt to 12. The signal of the calling number detection circuit 26 is applied to the CPU control circuit 30,
The CPU control circuit 30 outputs a reception interrupt signal when a signal indicating that the calling numbers match is added.
Add to CPU12. As a result, the CPU 12 performs the processing described later.

Furthermore, in addition to this, data received subsequently or currently stored in the BCH error correction circuit 25 is passed through the calling number detection circuit 26.
It is added to the SP conversion circuit 31. SP conversion circuit 3
1 means 8 bits of data coming into the serial.
This is a circuit for delivering data to the CPU 12 in bit units. This circuit, which will be described later, is connected to the address/control bus and data bus of the CPU 12, and when an interrupt is generated from the CPU control circuit 30 in 8-bit units, the CPU 12 takes in 8-bit data.

In addition, the CPU control circuit 30 outputs an end interrupt signal when it has finished receiving all data. The received data is added in units of 8 bits, and in addition, 2 function bits included in the address code are also output to the buffer in the CPU 12. This is done under the control of the CPU control circuit 30. Furthermore, the message code is also sequentially distributed in 8-bit units as error-corrected message data and taken into the CPU 12 from the SP conversion circuit 31.

The communication control circuit 11 always operates,
The timing control circuit 23 turns the power on and off via the power supply control circuit 29 as described above, thereby preventing overall power consumption.

FIG. 6 is an operation flowchart of the communication control circuit 11 shown in FIG. When the power of the receiver is turned on, first, preamble search processing S1 is performed. This search request is sent to the timing control circuit 2.
This has been done since 3. The preamble is
Preamble detection circuit 2 consists of 576 bits.
If 2 is consecutively followed by 8 bits "10101010", it is added to the timing control circuit 23 as preamble detection. When this detection result is added, the timing control circuit 23 causes the synchronization code detection circuit 24 to start a synchronization code detection operation. The synchronization code appears immediately after the preamble, and if there are consecutive batches of data, it appears at the beginning of each batch of data. At this time, that is, after preamble detection, it is the first preamble detection, so immediately after this preamble detection signal is applied, the synchronization code detection circuit 24 is activated by the timing control circuit 24.
3 is operated. When a synchronization code is detected by the synchronization code detection circuit 24, that is, when a synchronization code is detected in step S2, the data of its own block is then taken into the BCH error correction circuit 25. Note that at this time, the power of the wireless receiving circuit 10 is on as described above. After importing, the calling number detection circuit 26 is operated to perform a process of detecting whether the contents of the IDROMI 27 and IDROM 28 match the received code, that is, a word search process S3.
Next, it is determined whether the synchronization code has been missed twice. Generally, a synchronization code may not be detected once due to noise or the like, so in the embodiment of the present invention, if synchronization loss occurs two times, it is determined that the synchronization code is out of synchronization. Then, the process S1 from the preamble search is executed again.

On the other hand, if it is missing only once or never (determination S4 NO), then in determination processing S5 it is determined whether the ID codes match. ID
If the code is not found, the word search (ID code search) process S3 is executed again.
In the POCSAG method,
The block given to self is a specific position,
There is no guarantee that the data in that block is your own data. That is, it is determined by the ID code, and if the ID code is different, it is something else. Therefore, it is quite possible that the ID code will be lost due to the occurrence of an error. This is determined in the aforementioned determination process S4.

On the other hand, if the ID codes match, then the message is retrieved (processing S6). This acquisition is carried out by the CPU 12, which will be described later, and the data serially output from the calling number detection circuit 26 is applied to the CPU 12 in 8-bit units and is acquired. When this capture is finished, that is, when processing S6 is finished, it is then determined whether the message is finished. That is, the message flag in the first bit of the message code word is checked, and when the message flag is "1", it is determined that the next message data will continue, and when the message flag is "0", it is determined that the message has ended. A judgment is made (processing S7).
If the answer to step S7 is NO, the message retrieval process is performed again, and the above operations are repeated in sequence. As mentioned above, this is done in units of 8 bits, for example, a total of 20 message bits 2 to 21.
During the bit period, it is determined whether all the data has been captured, that is, whether the message is at its end. S7
When it is determined that the message has ended, the next step is to perform the word search process again starting from S3.
For example, if the preamble is not detected or detected incorrectly when the power is turned on, for example,
Even if 8-bit data of 10101010 is actually repeated, it may still be data in some cases. In this case, the synchronization code is naturally lost twice because synchronization cannot be achieved. At this time,
The preamble search processing is performed again from S1. In this preamble search process, 62.5msec
During this time, the power of the wireless receiving circuit 10 is turned on, and it is determined whether or not it is a preamble. If it is not a preamble, the wireless receiving circuit 10 is powered on again after 1062.5 msec and the preamble search is performed again. By repeating the preamble search process S1 in sequence, the preamble sent before the batch data can be detected by performing the preamble search S1 several times.

As described above, the radio receiving circuit 10
By turning the power on, detecting the preamble during that time, and further synchronizing, the power is turned on only when the block is assigned to itself, and it is determined whether it is its own address or a different address. . This reduces power consumption.

As mentioned above, in the embodiment of the present invention, the first address and second address are
Stored in ROM127 and ID-ROM28. By providing these two addresses, it can be used for various calls such as a telephone request from point A, a telephone request from point B, and even an emergency call.

FIG. 5 is a detailed block diagram of the CPU 12.

CPU 12 has a data bus and an address/control bus, each of which connects microprocessor 4.
1, buffer 42, start flag register 43, oscillation circuit 44, ROM 45, RAM 46, display control section 47, switch control section 48, alarm control section 49,
A melody memory 50 is connected. The microprocessor 41 executes a program stored in the ROM 45 and controls what kind of processing is to be performed based on the data added from the communication control circuit 11 described above. Most of the capture processing is initiated by an interrupt. As described above, these interrupts include receive interrupt/, 8-bit interrupt, and end interrupt. Further, error bits and function bits (2 bits) are added to the buffer 42 from the CPU control circuit 30, and each process described later takes in the error bits and function bits (2 bits) via this buffer 42. The oscillation circuit 44 is a circuit that generates the clock required when the microprocessor 41 operates and accesses each circuit via the data bus and address/control bus. This clock is added to each circuit that requires it.

FIG. 7 is a detailed flowchart of the CPU 12 in an embodiment of the present invention. When a reception interrupt signal or signal is added, the message capture process shown in FIG. 7 is performed. First, a function bit, which is the first code, is taken in (processing T1).
The occurrence of an interrupt means that the ID number is detected in the communication control circuit 11 and is information that requests data reception.
Bit data is added. Therefore, after processing T1, there is a serial parallel interrupt, that is, 8
A process T2 is performed to determine whether or not a bit interrupt has been added. If there is no interrupt, this determination processing is performed sequentially, and the system enters a standby state during this determination processing.

On the other hand, when it is determined that a serial/parallel interrupt has occurred, the 8-bit serial data is
Since the data is converted into 8-bit parallel data by the SP conversion circuit 31 and output to the data bus, a process T3 is then performed in which the data is taken into a message buffer (described later). This is of course the microprocessor 41
The captured data is stored in RAM46.
is stored in the register area. Next, it is determined whether import into the message buffer has been completed (processing T4).

In the embodiment of the present invention, the message data is 20 bits, and since it is not possible to capture all the data in one capture of 8 bits, the message end determination process T
If the result of 4 is NO, it is determined whether the next 8 bits have been added, that is, the above-mentioned process T2 is performed, and the above-described operation is repeated again. When the process is completed in determination T4, the data is displayed next (processing T5).

In the message buffer import process T3, since there are two IDROMs in the embodiment of the present invention, two message buffers are also provided correspondingly.

FIG. 8 is a configuration diagram of the contents of each register in the embodiment of the present invention. Message Battle MB1
is a buffer corresponding to IDI (first address), and message buffer MB2 is a buffer corresponding to ID (second address). For example, if the address code word matches the IDI, the data is stored in the message buffer MB1.

In the embodiment of the present invention, data is sent multiple times to prevent one's own message from being lost due to noise or the like. When the reception condition is good, it is possible to receive all the data in one reception process, but when the reception condition is bad, it may not be possible to receive all the data in one reception process. After the display is finished, the reset flag is then determined (process T6). This is to determine whether previously received data has been cleared or not. If there is no reset flag, it is determined that this is the first reception, and then processing T7 is performed to sound an alarm melody. Then, the contents of the corresponding message buffer MB1 are stored in the message register. As shown in the register configuration diagram shown in Figure 8, the RAM 46 has a register that displays the current time.
TM and date register DT; furthermore, it has a 2-bit function area F for specifying four types of melodies when the ID code is , a flag indicating the ID code, a reset flag RS, a pointer P, etc.; Further below, there are areas TN ₁ to TN ₃₀ for storing telephone numbers and areas RT ₁ to RT ₃₀ for storing reception times.

In an embodiment of the present invention, a telephone number and the time of reception thereof are stored, and the telephone number is the content of the message bit sent in correspondence with the called number. The contents of the message bits are stored in telephone number register _TN1 in FIG. Then, the time at that time is stored in the reception time register _RT1 (processing T9). This reception time is the content stored in the current time register TM. The contents are CPU1 shown in Figure 5.
This is data of the timer included in the oscillation circuit 44 in the configuration diagram of FIG. This data is received in the reception time register.
Store it in the RT ₁ area and finish the message import process.

In the embodiment of the present invention, as described above, a total of 30 telephone numbers and reception times are stored. The storage from the message buffer to the message register TNn is configured to shift sequentially, for example,
If the reception status has been received twice before, the phone number
Store TN ₂ in phone number TN3, and store TN ₁ as TN ₂
Then, send the contents of message buffer MB1 to TN ₁ .
Store in. Further, the reception time is also the same; the contents of RT ₂ are stored in RT ₃ , the contents of RT ₁ are stored in RT ₂ , and the current received time is stored in RT ₁ .

Explaining with reference to FIG. 7, if the reception state was previously reset, the reset flag is set, and at determination T6, the reset flag is present and the contents of the current time are stored in the reception time register. Only process T9 is performed.

The reset flag mentioned above is set by the reset switch.
The flag is turned on or off depending on whether it is turned on or off, and this is done by each control program (stored in the ROM) of the CPU 12.

Returning to FIG. 5, the switch control section 4
Reference numeral 8 is for inputting the status of each switch shown in FIG.
It is joining 1. Based on this switch information, the microprocessor 41 performs processing to turn on the reset flag, for example, when the reset flag goes off. Then, as will be described later, the sound when the alarm is sounded is stopped. On the other hand, CPU1
2 also has a signal for activation when the power is turned on. This is microprocessor 4
1, for example, when the initial processing is completed and the state is ready for reception. First, in order to perform processing for searching for a preamble, a write is made to the activation flag register 43. This write signal becomes an activation signal and is applied to the CPU control circuit 30 in FIG. The CPU control circuit 30 applies a start signal to the timing control circuit 23. This signal starts the preamble search process shown in FIG.
Thereafter, the timing control circuit 23 sequentially detects preambles as shown in FIG. 6, and when detected, the synchronization code detection circuit 24 is operated to receive a synchronization signal.

When a synchronization signal is received, the power is turned on only for a specific time from the synchronization signal, that is, during the block assigned to the device, and the BCH signal applied from the radio reception circuit 10 is input via the input synchronization circuit 21. It is added to the BCH error correction circuit 25. This allows the device to correct errors and receive messages of its own data. This 8-bit data is always sent to the microprocessor 4.
1. That is, in response to an interrupt, the microprocessor 41 sequentially repeats the acquisition in 8-bit units to receive all messages.

In the embodiment of the present invention, the CPU 12 has circuits that generate four types of melodies and alarm sounds. For example, as shown in Figure 9a, the four types of melodies are ``10 Indians,'' ``Katsuko Waltz,'' ``Rocky Bye Baby,'' and ``London Bridge.'' is stored in the melody memory 50. Then, the microprocessor 41 sequentially reads out the melody and adds the scale corresponding to the content of the melody stored in the melody memory 50 to the tone control circuit 49. The alarm control circuit 49 generates corresponding data, that is, a musical scale. This generated scale is output to the speaker 15 in FIG. 2.

FIG. 9b is a flowchart for controlling the generation of each melody in response to this alarm. That is, this is a detailed flowchart of process T7 in FIG. First, the function area F is determined, and then the flag / is determined (processing T1
1, T12).

Identification and flag of function area F,
In this determination, if the flag indicates that the function area F is "00", the melody generation process T13 is performed to sound the melody 1, for example, "10 Indians". In addition, when the function area F is "01" in flag 1, processing T1 for sounding "Katsuko Waltz" of melody 2
Do step 4. Further, when the flag indicates that the function area F is "10", melody 3 "Rock-a-baby baby" is generated (process T15). Furthermore, when the flag shows Function Area F as "11", Melody 4's "London Bridge" is displayed.
is generated (process T16). Further, when the flag is set, that is, when the IDROM code is sent, a warning sound of melody 5 is generated (process T17). This warning sound is generated by, for example, adding a certain bit to the warning sound control circuit 49 in FIG. 5. Note that this tone control circuit 49 is configured to perform, for example, triple chords,
This is an IC for generating scales such as quintuple chords, and by adding timbre, scale, and other information such as attack, decay, and release information, it is possible to generate triple scales. Furthermore, the length is not shown in the diagram. The desired sound can be generated for a certain period of time by changing the timer in response to a timer interrupt applied from the oscillation circuit 44. Then, the scale corresponding to the target melody stored in the melody memory 50 is sequentially called up and the data is changed every time there is an interruption, thereby making it possible to output the scale.

In the embodiment of the present invention, the melody memory 5
0, but in addition to this, Melody IC
It is also possible to do this. For example, the alarm control circuit 4
By adding ``00'' to 9, the first melody also changes; by adding ``01'', the second melody also changes; by adding ``10'', the third melody also changes. It is also possible to create a fourth melody by adding "11" to the melody.

The embodiments of the present invention have been described in detail above, but in the embodiments of the present invention, for example,
When IDI is received, the content of the melody to be generated can be changed based on the corresponding 2-bit function data. Also, when the ID number matches the ID number stored in the IDROM, a warning sound is generated. Even if a melody or warning sound occurs, if you cannot respond immediately, you can search the display section 2 for the contents received so far, that is, press the display selection switch 3 in Fig. 1, and display them sequentially. You can check who is calling and what time. Further, if the contact can be made immediately, it becomes possible to identify it by the melody in the melody memory 50, for example, and it becomes possible to contact the contact without looking at the display. In particular, when illuminating the display section in a dark place, lighting with lamps consumes a very large amount of power, but the present invention can prevent this and create a paging receiver with low power consumption. It becomes possible to obtain.

〔Effect of the invention〕

As described above, the present invention selectively generates a plurality of types of melody sounds and a warning sound different from the melody sound as means for generating notification sounds in a paging receiver having two self-calling numbers. When the first self-dialing number is called, that is, when the self-dialing number is frequently used and is used by multiple people, the sound type can be easily identified as a notification sound. In addition, at the same time as selecting a harsh melody sound, a melody is selected based on function data added to the received calling number, and a call is notified with the melody sound of the selected melody, and on the other hand,
When called with a second self-calling number, i.e.
When called by a self-calling number that is used by a specific person and used infrequently but with a high degree of emergency, the notification tone is completely different in type from the melody sound and has a higher alertness (recognizability of the alert). ) is selected regardless of the function data added to the received called number, and the system is configured to notify the caller with this alert sound that has excellent alertness. This has the advantage of not only making it easy to identify the user's calling number, but also quickly and reliably recognizing which of the self-calling numbers the call was made to.

[Brief explanation of drawings]

Figure 1 is an external view of an embodiment of the present invention, in which figure a is a front view, figure b is a top view, figure c is a side view, and figure 2 is an overall configuration of an embodiment of the present invention. Figures 3A to 3F are data configuration diagrams of the POCSAG method, Figure 4 is a circuit configuration diagram of the communication control circuit 11, and Figure 5 is a diagram of the data configuration of the POCSAG method.
6 is a detailed block configuration diagram of the CPU 12, FIG. 6 is an operation flowchart and timing diagram of the communication control circuit 11, FIG. 7 is an operation flowchart of the CPU 12, FIG. 8 is a diagram showing a part of the configuration of the RAM 46, and FIG. Figure 9a shows the contents of the melody memory, Figure 9b shows the contents of the melody memory.
is a flow chart of melody generation control. 10... Radio reception circuit, 11... Communication control circuit, 12... CPU, 49... Alarm control circuit, 5
0...Melody memory.

Claims (1)

[Claims] 1 Compare the received calling number with the first and second self-calling numbers set in advance, and generate a notification sound when the received calling number matches either of the first and second self-calling numbers. In the paging receiver, the paging receiver is provided with a means for selectively generating a plurality of types of melody sounds and an alarm sound different from the melody sound as a means for generating the notification sound, and when the received calling number is the first self-calling number. When the number matches, one of the plurality of types of melody tones is selected based on the function data added to the received calling number, and the received calling number is set as the second self-calling number. 1. A paging receiver comprising a selection control means for selecting the warning sound when the number matches the number, regardless of the function data added to the received calling number.