JPH03259681A - Picture storage device - Google Patents

Abstract

PURPOSE:To improve the recording speed by providing plural memories supplying digital picture data in plural bits as to a prescribed picture element number to which supplied data in plural bits are to be written for each prescribed bit. CONSTITUTION:An object image by an image pickup lens 10 is converted into an electric signal by an image pickup element 12, processed by an analog picture processing circuit 14 and converted into a digital data in 8-bit by an A/D converter 16. Each bit of an output data of the A/D converter 16 is stored in memory packs 24a-24h of a memory cartridge 24. Since it is enough in one-bit write time to store each one picture element data in the memory cartridge 24, a time of 1/8 is enough to store one picture element data into one memory pack.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application 1] The present invention relates to an image storage device that uses a solid-state memory as a recording medium for image signals.

[Prior Art] A solid-state camera using a memory cartridge, for example, is already known as a device for recording image signals using a solid-state memory.

A configuration for improving the continuous shooting speed in such a solid-state camera is described in Japanese Patent Application Publication No. 126387 of 1981. FIG. 6 shows a block diagram of a device similar to the device shown in this publication.

In FIG. 3, 10 is a photographing lens, 12 is a solid-state image sensor, 14 is an analog image processing circuit, 16 is an A/D converter,
18 is a latch circuit, 20a, 2°b, 20c, 20d,
20e, 2Of, 20g.

20h is a parallel/serial (P/S) converter that converts an 8-bit parallel signal into a serial signal, and 22 is 8 memory packs 22a that use semiconductor memories as storage elements.
, 22b, 22c, 22d, 22e, 22f, 22g,
22h is a memory cartridge, and 23 is a clock circuit.

The image sensor 12 converts the subject image captured by the photographic lens 10 into an electrical signal, and the analog image processing circuit 14
The output of step 2 is subjected to known analog image processing. The A/D converter 16 converts one pixel signal output from the analog image processing circuit 14 into an 8-bit digital signal. This 8-bit data is latched by a latch circuit 18 and supplied to P/S converters 20a to 20h in sequence for each pixel.

In this case, the latch circuit 18 consists of 8 bits x 8 latch elements, and the first pixel data is sent to the P/S converter 20a, the second pixel data is sent to the P/S converter 20b, and so on. It is cyclically supplied to the P/S converters 20a to 20h each time.

P/S converters 208-20h convert 8-bit parallel signals into serial signals, and the serial outputs are stored in corresponding memory packs 22a-22h, respectively.

With this configuration, it is possible to record data in 1/8th of the time compared to storing all pixel data in one memory pack.
Recording time can be shortened. In other words, the continuous shooting speed can be increased. Generally, if N memory packs and N P/S converters are provided and the latch circuit 18 is configured with 8 bits x N latch elements, the recording time can be shortened to 17N.

[Problems to be Solved by the Invention] However, in the above conventional example, one image is stored in a distributed manner in the plurality of memory packs 228 to 22h of the memory cartridge 22, so that all the memory packs are not aligned. This has the disadvantage that recorded images cannot be played back. Furthermore, in order to shorten the recording time, many P/S converters and many latch elements are required, resulting in a problem that the circuit becomes complicated.

In view of this, an object of the present invention is to provide an image storage device with improved recording speed.

Another object of the present invention is to provide an image storage device capable of storing a variety of image data.

Another object of the present invention is to provide an image storage device that can efficiently use storage capacity for image data.

Another object of the present invention is to provide an image storage device suitable for nonvolatile memory.

Another object of the present invention is to provide a novel imaging system comprising an imager and an image storage device.

[Means for Solving the Problems] In order to achieve the above object, the first invention of the present application provides a supply means for supplying a plurality of bits of digital image data for a predetermined number of pixels, and a plurality of bits of digital image data supplied by the supply means. It has a plurality of memories for writing data for each predetermined bit.

A second invention of the present application also provides a converting means for converting digital image data of a plurality of bits for a predetermined number of pixels into supplied image data; The converting means includes converted image data and the converting means.

Further, a third invention of the present application provides a supply means for supplying one-pixel multi-bit image data, a compression means for compressing the image data supplied from the supply means, and an image data supplied from the conversion means or the compression means. and control means for controlling display of remaining storage capacity of the memory by selecting any of the uncompressed data by the means and selecting any of the data to be written to the memory.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The same components as in FIG. 2 are given the same reference numerals. 24, eight memory packs 24a, 24b, 24c, 24d corresponding to the 8-bit outputs b7 to bo of the A/D converter 16;
, 24e, 24f.

It is a memory cartridge equipped with 24g and 24h, and is removable from the main body. That is, 8 of the A/D converter 16
Among the bits of bit output b7 to b0, bit b is input to the memory pack 24a, and bit b6 is input to the memory pack 24a.
bit bs is input to memory pack 24c, bit b4 is input to memory pack 24d, bit b3 is input to memory pack 24e, bit b2 is input to memory pack 24f, bit b+ is memory
input into pack 24g, bit bo is memory pack 2
Enter in 4h. Further, 24 is an address controller that counts input pixel clocks and generates address data for the memory packs 24a to 24h; 25 is an image sensor 12, an analog image processing circuit 14, and an A/D converter 1;
This is a clock generation circuit that generates a clock that defines the operation timing of 6.

In this embodiment, the 8-bit image data A/D-converted by the A/D converter 16 was written directly to the memory.
The /D-converted data may be digitally compressed by, for example, DPCM compression, and then written to the memory 24. Further, the address controller is not shown in any of the memories 11 shown in FIGS. 2 to 4, which will be described later, but is included therein.

The object image taken by the photographic lens 1o is converted into an electrical signal by an image sensor 12, as in the conventional example, processed by an analog image processing circuit 14, and converted into 8-bit digital data by an A/D converter 16. A/D converter 16
The output data of is stored bit by bit in the memory packs 24a to 24h of the memory cartridge 24, respectively.

It takes only 1 bit of writing time to record one pixel data to the memory cartridge 24, so it takes 1/8th of the time compared to recording one pixel data to one memory pack. It's over.

In FIG. 1, eight memory packs 2 are installed in the memory cartridge 24 according to the number of output bits of the A/D converter 16.
2a to 22h are provided.

Of course, other combinations may be used as long as the number of memory packs and the number of output bits of the A/D converter match.

FIG. 2 shows a block diagram of another embodiment of the present invention.

26 is a latch circuit consisting of 8 bits x 2 latch elements, 28 is 16 memory packs 30a to 30h, 32
A memory cartridge 34 includes memory cartridges a to 32h, and 34 is a clock generation circuit that generates a clock that defines the operation timing of the image sensor 12, the analog image processing circuit 14, the A/D converter 16, and the latch circuit 26.

Each bit of one 8-bit pixel data is simultaneously recorded in the memory packs 30a to 30h, similar to the memory packs 22a to 22h in the embodiment shown in FIG. Similarly, each bit b7 to b0 of one 8-bit pixel data is recorded simultaneously. The latch circuit 26 alternately distributes the 8-bit output of the A/D converter 16 to the memory packs 30a-30h or the memory packs 32a-32h for each pixel. That is, when the first pixel signal is digitized by the A/D converter 16,
The 8-bit data is latched by the latch circuit 26, and recorded bit by bit in the memory packs 30a to 30h, as in the case of FIG. In the next pixel, the latch circuit 26 latches the output data of the A/D converter 16,
applied to memory packs 32a-32h. As a result, the data of the second pixel is stored in the memory packs 32a to 32h.
recorded in

In this way, by alternately using the memory packs 30a to 30h and the memory packs 32a to 32h for each pixel, the recording time can be reduced to 1/2 compared to the case of recording with only one memory pack. It can be shortened to 16.

Generalizing the case of the embodiment shown in FIG. 2, the A/D converter 1
If the number of output bits of 6 is n, and the number of latch elements of the latch circuit 26 is n x m, then by using n x m memory packs, the recording time is
It can be shortened to 1/nXm). However, n and m are positive integers.

As can be easily understood from the above description, according to this embodiment, the recording time can be significantly shortened without complicating the circuit, and therefore a high continuous shooting speed can be achieved.

Next, a second embodiment of the present invention will be described.

In this embodiment, an all-solid-state camera system uses a semiconductor memory device divided into a plurality of memory areas as an image recording medium, and when recording a normal natural image, one pixel of digital data is stored in parallel. The image signal is supplied to the semiconductor memory device and recorded bit by bit in a different memory area of the semiconductor memory device, and when recording a document image, the image signal is binarized and then stored in a different memory area of the semiconductor memory device for each image. The recording device is shown.

In such a device, compared to the case where one sheet of image data is serially recorded in one memory area, the recording time to the semiconductor memory device can be shortened to a time corresponding to 1/the number of bits. Therefore, the continuous shooting speed can be further increased.

Further, since the document image is binarized and recorded as 1-bit data, it can be recorded in a memory area that is 1/the number of bits when recording a natural image, so that storage efficiency can be improved.

Furthermore, since the circuit configuration can be simple, the circuit does not become complicated.

FIG. 3 is a block diagram of another embodiment of the present invention.

Components that are the same as those in FIG. 2 are denoted by the same reference numerals, and explanations thereof will be omitted. 24 is a system controller that controls the operation of the entire device; 27 is eight memory chips 27a, 27b, 27c, corresponding to the 8-bit outputs b7 to b0 of the ADC 16;
A memory cartridge comprising 27d, 27e, 27f, 27g, and 27h, 28 a clock generation circuit that generates clock pulses that define the operation timing of the image sensor 12, the analog image processing circuit 14, and the ADC 16, and 29 an 8-bit output of the ADC 16. Binarization circuit that binarizes to 1-bit data, 30a, 30b, 30c, 30d
, 30e, 30f, 30g, and 30h are changeover switches for switching between data from the AD'C 16 and data from the binarization circuit 29 in response to a switching signal from the system controller 24, and 31 is for switching between natural picture mode and document mode. This is an image mode switch for

When the release switch 26 is pressed down and closed, the system controller 24 starts the photographing sequence and starts the clock circuit 23. The clock circuit 23 supplies driving pulses to the solid-state image sensor 12 and the like. Photography lens 1
0 is converted into an electrical signal by the image sensor 12, processed by the analog image processing circuit 14, and sent to the ADC.
16 into 8-bit digital data. The binarization circuit 29 binarizes the output data of the ADC 16 according to a predetermined procedure and converts it into 1-bit data.

When recording a natural image, that is, when the image mode changeover switch 31 is closed to the natural image N side (natural image mode), the changeover switches 30a to 30h are activated by the changeover signals S, ~S0 from the system controller 24.
is closed on the n side, and the output data of the ADC 16 is stored bit by bit in the memory chips 27a to 27h of the memory cartridge 27, respectively. Writing one pixel data into the memory cartridge 27 requires only one bit of writing time, so it takes 1/8 of the time compared to recording one pixel data on one memory chip.

On the other hand, when recording a document image, that is, when the image mode changeover switch 31 is closed to the document image side (document mode), the changeover signals 87 to S0 from the system controller 24 are used to select the changeover switches 30a to 30a.
0h is closed to the β side, and the output data of the binarization circuit 29 is transferred to the memory chip 27a of the memory cartridge 27.
~27h.

If the release switch 26 is still closed at the end of the above shooting sequence, the system controller 24 checks the state of the continuous shooting mode changeover switch 25, and if the switch 25 is closed to the continuous shooting C side, Then, a new photographing sequence is started, and when the switch 25 is closed to the single shot S side, photographing is ended.

The operation when recording the document image will be described in more detail. In this embodiment, the system controller 24 stores the number of natural images and document images that have been recorded up to now. When recording a document image, which of the changeover switches 30a to 30h should be closed to the β side and which of the memory chips 27a to 27h should record the document image data is determined as follows.

In other words, if β is the number of document images recorded up to now, then m = (4-1) mod 8 -... ■When m is O, turn switch 30a, when it is l, turn switch 30b, and when m is 30c at 3, 30d at 3, 30e at 4,
Close 30f at 5, 30g at 6, and 30h at 7 to the β side, and connect the corresponding memory chips 27.
Document image data is recorded in any one of a to 27h. Here, the operator nod is an operator that calculates the remainder. Further, in the natural picture mode, the changeover switches 30a to 30g are all switched to the n side.

Furthermore, the memory area corresponding to the number of images to record image data in is determined as follows.

In other words, if n is the number of natural images recorded to date, then in natural image mode p=(β+7)/8+n...■p
New image data may be recorded in the memory area of the second image.

In the document mode, new image data is recorded in the (p-1)th memory area. However, the operator / is an operator that performs integer division.

In FIG. 3, eight memory chips 27a to 2 are installed in the memory cartridge 27 according to the number of output bits of the ADC 16.
7 hours are provided. Of course, the number of memory chips and AD
Other combinations may be used as long as they match the number of output bits of C.

Furthermore, the display driver 33 is controlled to display the remaining capacity on the external display device 35 so that the photographer can check the remaining capacity of the memory, that is, how many images can be taken. In such a case, do the following:

That is, if t is the total number of images that can be recorded in the memory cartridge 27, and S is the remaining capacity of the memory, then in the natural image mode, 5=t-β+1, S, is displayed as the remaining capacity. On the other hand, in the document mode, 5=(t-n)*8-°C, S, is displayed as a numerical value, for example, as the remaining capacity.

Next, the operation of the above embodiment will be explained using FIG. In FIG. 4, when the power (not shown) of the apparatus is turned on, the process goes to S3 depending on which switch 31 is switched to, if it is a natural image mode, or to S5 if it is a document mode.
The flow branches to , the calculation shown in the figure is performed as described above, and the remaining capacity S is displayed on the display 35.

In this state, when the release switch 26 for recording is turned on, the flow advances from S9 to Sll and again, depending on which switch 31 is switched, goes to 313 if it is a natural picture mode or to 313 if it is a document mode. S15 if available
The flow branches to 5ll), and the p-th image memory as shown in the figure is selected, and when in natural image mode, switches 308 to 30g are all switched to the n side and writing is performed to memory chips 27a to 27h. When in the document image mode, among the switches 30a to 30g, m = (f2-
1) The switch corresponding to mod 8 is switched to the 4 side, and writing is performed to any of the memory chips 27a to 27h (S17). If continuous recording mode is set, the flow advances from S19 to S21, and the above-described flow is repeated until recording is turned off.

As can be easily understood from the above explanation, according to this embodiment, recording time can be significantly shortened without complicating the circuit, high continuous shooting speed can be achieved, and when recording document images, Since it occupies only 1/8 the memory area when recording a natural image, storage efficiency can be improved.

In addition, in the above embodiment, multiple bits of data for each pixel were stored in the memory on each side, but next we will discuss an embodiment in which multiple bits of data for each pixel are written to a different EEPROM for each pixel. This will be explained using FIG.

In the following examples, EEFR is used as the image recording medium.
A memory cartridge using an OM chip is used, and continuous image data is stored in different EEs within the memory cartridge.
Disclosed is an apparatus that can configure an all-solid-state camera system that does not require a backup battery without sacrificing continuous shooting speed by switching and recording data by assigning it to a FROM chip.

FIG. 5 is a block diagram showing the configuration of the third embodiment of the present invention, and the same components as in FIG. 2 are designated by the same reference numerals and their explanation will be omitted. 4 is a memory cartridge of this embodiment, 41 is an address controller, and 42 to 49 are EEFs.
A ROM chip, 50 is an address decoder, and 51 is a chip encoder.

To explain the operation of the embodiment shown in FIG. 5, 8-bit image data is output from the solid-state camera body 1 together with the clock signal CLK, and the address controller 41 selects the address signal ADH and chip select according to the input clock signal CLK. Outputs signals C3O-CS7. In this embodiment, the lower three bits AO-A2 of the address signal ADR output from the address controller 41 are input to the address decoder 50. address decoder 50
Then, chip select signals CA◯ to CA7 are output in accordance with the input address signal.

Also, a chip select signal 08ONC87 outputted from the address controller 41 is inputted to the chip encoder 51. The chip encoder 51 outputs an address signal Co-C2 in response to the input chip select signal. The chip select signals CAO-CA7 output from the address decoder 5o are respectively applied to the EEFROM chip 4.
It is connected to the chip select terminals O8 of 2 to 49. The upper 14 bits A3 to A16 of the address signal output from the address controller 41 are the EEPROM.
Lower 14 bits AO of address terminals of chips 42 to 49
Connected to NA13. Further, the address signal Co-C2 output from the chip encoder 51 is the upper three bits A14 to A of the address terminals of the EEPROM chips 42 to 49]
Connected to 6.

With this configuration, in this embodiment, image data is written to a different memory chip for each pixel, and data is written to adjacent memory cells every 8 pixels. In this way, EEFRO with long write access time
It was possible to construct an all-solid-state camera system using the M chip without sacrificing the speed of snapshots, without using a backup battery for retaining image data, and having a memory unit that is removable from the camera body.

Although this embodiment has been described with reference to the case where image data is sequentially written to eight EEFROM chips, it is clear that the present invention is effective with any number of EEFROM chips, not limited to eight. In this embodiment, 8 bits x 128
Although the case where an EEFROM chip with a byte configuration is used has been described, it goes without saying that an EEFROM chip with a different configuration may be used.

As is clear from the above description, according to this embodiment, an all-solid-state power camera system can be constructed without sacrificing continuous shooting speed by using EEFROM which does not require a backup battery and has a long write access time. This eliminates the need to worry about backup battery consumption, making it possible to create an all-solid-state camera system that is easy to use.

Furthermore, the EEFROM shown in this embodiment is shown in FIG.
It may be replaced with the memory 27 shown in FIG. The type of memory is not limited to this.

In such a case, even if the data writing speed is low, data can be written to the memory at high speed,
Furthermore, it is possible to efficiently write a variety of data into memory, such as document mode and natural image mode.

Also, the image compression in this embodiment is MULT I BIT
Although it was decided to binarize the a image data, it is not limited to this, and various other compression methods (for example, DP
CM, block coding, etc.) may be adopted.

[Effects of the Invention] As explained above, according to the present invention, the recording speed can be improved.

Furthermore, according to the present invention, various image data can be stored.

Further, according to the present invention, it is possible to provide an image storage device that is easy to use.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of a first embodiment of the present invention, FIG. 2 is a block diagram of another embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention. 4 is a flowchart showing the operation of the embodiment shown in FIG. 3, FIG. 5 is a block diagram showing the configuration of the third embodiment of the present invention, and FIG. 6 is a flow chart showing the structure of the third embodiment of the present invention. It is a figure which shows an example. 24...System controller 28...Memory 29...Binarization circuit 2nd item--"

Claims (3)

[Claims] (1) An image characterized by having a supply means for supplying digital image data of a plurality of bits for a predetermined number of pixels, and a plurality of memories for writing the plurality of bits of data supplied by the supply means for each predetermined bit. Storage device. (2) A supply means for supplying multiple bits of digital image data for a predetermined number of pixels, a converting means for converting the multiple bits of digital image data supplied by the supply means into compressed digital image data, and conversion by the converting means. 1. An image storage device comprising a selection means for selecting either image data converted by the image data or image data before being converted by the conversion means. (3) supply means for supplying 1-pixel multi-bit image data; compression means for compressing the image data supplied from the conversion means; either data compressed by the compression means or data not compressed by the compression means; 1. An image storage device comprising: writing means for selecting and writing into a memory; and control means for controlling display of remaining storage capacity of the memory in accordance with the selection.