JPH0325955A - Semiconductor device - Google Patents

Abstract

PURPOSE:To achieve a countermeasure to electrostatic breakdown of an arbitrary pin easily by arranging various transistors, resistors, and capacitors in array form on the same substrate, and providing protective diodes against external terminal VCC, GND, and many protective diodes as the countermeasure to electrostatic breakdown between arbitrary terminals. CONSTITUTION:When a positive pulse is applied to a terminal A1, a current flows through EB junction of a transistor Q1 in a forward bias state and through EB junction of a transistor Q2 in a reverse bias state toward a terminal A2, and the EB junction of the transistor Q2 is subjected to breakdown mainly. When diodes D1, D2, D3, D4 are connected between the terminal A1 and the terminal A2, the clamp voltage between the terminal A1 and the terminal A2 will be twice the forward voltage VF. Because the diodes D3, D4 are connected, even if a negative pulse is applied to the terminal A1, the clamp voltage between the terminal A1 and the terminal A2 is 2VF. Though it is clamped by 2VF, when a signal input voltage Vin is larger than 2VF, n diodes may be connected in series so that Vin<n.VF is satisfied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a master slice type semiconductor device in which a plurality of transistors, resistors, and capacitors are arranged in an array.

[Conventional technology]

In recent years, there has been a strong demand for shortened delivery times for LSI development, as typified by gate array systems.

In order to significantly shorten the development period for analog circuits, semiconductor devices using the analog master slice method, in which semiconductor devices such as transistors, various resistors, and MOS capacitors are arranged in an array of several hundred to several thousand elements on the same substrate, have been put into practical use. has been made into

Semiconductor devices using the analog master slice method are usually stored in a state in which a contact hole is formed and a second IAβ layer is deposited. A circuit pattern can be formed on a semiconductor substrate. Analog mask slice has minimum NPN} transistor, PNP} transistor, P+ resistor, P- resistor,
In addition to the basic devices of polysilicon resistors and MOS capacitors, it has built-in output transistors for drivers that can flow several tens of mA, and protection diodes for electrostatic damage to Vcc and GND.

Since the above device is fixed on a mask slice, unless a new mask slice is developed, circuit design and electrostatic damage countermeasures must be performed using elements on a given mask.

[Problem to be solved by the invention]

In a normal design method that does not use an analog master slice, when a circuit is designed using the minimum number of transistors, the electrostatic breakdown strength between external terminals may be lower than the required withstand voltage. In this case, it is generally considered that a resistor of several kΩ is inserted between the external terminals. However, if a resistor is placed on the base side, it may have negative effects such as a decrease in frequency, an increase in noise, and an increase in offset, and it may not be possible to locate the resistor.

In normal design, the device size of the transistors on the path from external terminal to external terminal is increased so that the electrostatic breakdown voltage is sufficiently high. Since the device design and layout design are performed according to the circuit, the above measures can be easily taken.

However, in the conventional analog master 2 chair,
Although there is protection Di against V c c and GND, there are no electrostatic damage prevention elements for the same external terminals, so countermeasures against electrostatic damage, such as connecting the smallest transistors in parallel, are extremely insufficient. Can not. Furthermore, the miniaturization of recent processes and devices has progressed rapidly, and the number of elements that can be mounted on an analog master slice has increased significantly.However, the electrostatic breakdown voltage of single transistors has been rapidly decreasing, so conventional It has been extremely difficult to take measures against electrostatic damage between arbitrary external terminals in analog masks. [Means for Solving the Problems] The present invention provides a structure in which various transistors, various resistors, and capacitors for configuring a circuit are arranged in 7 layers on the same substrate, and protection diodes for external terminals Vcc and GND are arranged on the same substrate. Furthermore, it has a large number of protection diodes to prevent electrostatic damage between arbitrary terminals, thereby providing a highly reliable semiconductor device.

〔Example〕

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

For simplicity, a case is shown in which both bases of NPN transistors constituting a differential circuit are exposed to external terminals.

When a positive pulse is applied to terminal A1, transistor Q1
When the EB junction of transistor Q2 is forward biased, the EB
With the junction reverse biased, current flows toward terminal A2, destroying mainly the EB junction of transistor Q2. Therefore, as shown in Figure 1, diodes D1, D2, D3, D
If the terminal A1 and the terminal A2 are connected as shown in FIG. 4, the voltage between the terminal A1 and the terminal A2 will be clamped by two forward voltages Vy of the diodes. Since diodes D3 and D4 are connected, even if a negative pulse is applied to terminal A1, terminal A1
and terminal A2 are clamped at 2.■.

In the example, it is clamped at 2V, but when the signal input voltage Vin of terminal A1 and terminal A2 exceeds 2VW, it is possible to connect n diodes in series so that Vin<n・■2. good. Since the junction capacitance at both ends is 1/n of the junction capacitance of one, it is advantageous to increase the number of devices connected in series in order to reduce the parasitic capacitance between the terminals.

FIG. 2 shows a schematic cross-sectional view of the diodes D1 to D4 in FIG.
It has a structure with the + layer removed.

In order to strengthen the electrostatic strength of the diode itself and to minimize leakage current in the reverse bias state, an N+ region 7 ( The distance between the cathode and cathode is wide, and the resistance length is long.

FIG. 3 is a top view of an analog master slice using the present invention.

2 1 a, 2 l b, 2 1 c are bonding pads, 22 is P- and P-resistors, 23 is NPN
}Ransistor and PNP }Ransistor, 24 is MOS
Capacitor 25 represents a protection diode. pad 2
1a is connected to the anode of the diode D1 by the IAβ wiring, and the cathode is connected to the anode of the diode D2. Furthermore, the cand of diode D2 is connected to the 7 node of diode D4 and pad 2lb. When the pads 21a and 2lb are adjacent to each other, they can be easily connected as explained above, but when the terminals are far apart, wiring is difficult. Therefore, the Aj2 wiring 26 is wired in a ring shape inside the pad array in advance, and if necessary, this ring-shaped Au wiring 26 is partially cut for use.

FIG. 4 is a plan view of a second embodiment of the invention.

In the first embodiment, a protective diode 25 for preventing electrostatic damage between arbitrary terminals was provided between the pads, but in this embodiment, a protection diode 25 for preventing electrostatic damage from Vcc is provided between the pads. A protection diode 7 and a protection diode 8 to prevent electrostatic damage from being connected to GND are arranged. A protection diode 25 is then arranged inside the pad.

In FIG. 2, the anode electrode 10 and cathode electrode 11 of the protection diode are formed by the IAA wiring, so the fourth
As shown in the figure, the second An wiring 29 is connected to the protective diode 25.
It can be passed directly above. For this reason, protection diode 2
Since the area No. 5 can also be used as a wiring area, the master slice chip does not become large.

〔Effect of the invention〕

As described above, the present invention can easily take measures against electrostatic discharge damage between arbitrary terminals, which has been difficult with conventional analog master slices. In normal analog mask slicing, in order to increase the electrostatic damage strength, several of the smallest transistors are connected in parallel, but in this case, a considerable number of transistors are taken to prevent Stt damage and the circuit is configured. There were cases where this was a hindrance. Furthermore, as a result of the burden placed on layout design, wiring becomes long, parasitic impedance and parasitic capacitance increase, and frequency deterioration occurs. The present invention improves the above points and can easily take measures against electrostatic damage to any pin. Of course, it is not necessary to implement the present invention for all combinations of arbitrary bins, and in most cases, a resistor is equivalently connected in series between arbitrary terminals, and there is no need to take measures against electrostatic damage.
It is only necessary to take measures using a protection diode in special cases as shown in the first embodiment.

According to the present invention, it is possible to proceed with the design efficiently without impairing the electrical characteristics or hindering the layout automation, and the reliability can be improved, so that the device size can be further reduced and a single unit can be used. If the electrostatic breakdown strength of the device becomes even lower, it can be expected that the effectiveness of the present invention will further increase. Regarding the embodiment, only the bipolar analog master slice was described;
MOS Analog Master Slice The present invention is equally applicable to a so-called analog/digital master slice in which an analog circuit and a digital circuit can be constructed on the same substrate using a Bi-CMOS process.

In addition, although Fig. 2 shows the case where the emitter is diffused as a graft base diffusion cathode with 7 nodes in the epitaxial layer, in Bi-COMS, 7 nodes, Even if the cathode is formed, the same effects as those of the present invention can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIG. 2 is an IF1! 3 is a plan view of an analog master slice using the present invention, and FIG. 4 is a plan view of a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P-type substrate, 2... N-type epitaxial layer, 3... Insulating layer, 4... Separation layer, 5...・Graft base, 6...Arsenic-topped polysilicon layer, 7...N+ cathode, 8, 9...Insulating film, 10...7 node electrode , 11... cathode electrode, 21a, 2
lb, 21c...Pounding pad, 22.
...P+ and P-resistance, 23...NPN
and PNP} transistor, 24...MOS capacitor 25...protection diode, 26.
...Second Au wiring, 27, 28...Protection diode, 29...Second Affl wiring.

Claims (1)

[Claims] In a master slice type semiconductor device configured by arranging multiple semiconductor elements such as transistors, resistors, capacitors, etc. in an array on a semiconductor substrate, the electrostatic breakdown voltage between the external terminals excluding the power supply and ground In order to improve the electrostatic breakdown strength, a forward diode is made up of multiple diodes connected in series, and a reverse diode is connected in series. A semiconductor device characterized by being connected in parallel.