CN114068523A

CN114068523A - ESD electrostatic protection structure suitable for high-speed memory circuit

Info

Publication number: CN114068523A
Application number: CN202111370643.1A
Authority: CN
Inventors: 田海燕; 许海龙; 张海波
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2021-11-18
Filing date: 2021-11-18
Publication date: 2022-02-18

Abstract

The invention discloses an ESD electrostatic protection structure suitable for a high-speed memory circuit, and belongs to the field of integrated circuits. The ESD electrostatic protection structure is integrally positioned in the independent deep N well and is not in direct contact with the P-type substrate; the deep N well isolates the ESD device from the P-type substrate, so that each ESD electrostatic protection structure is independent; an N-well ring is arranged on the periphery of the deep N-well in a circle and is connected to a power supply through a well contact N + to provide a potential for the deep N-well; and a circle of P-type substrate contact ring surrounds the periphery of the N-well ring to serve as isolation, and the P-type substrate contact ring is grounded. The ESD electrostatic protection structure has a rapid ESD current discharge path to a power supply and the ground, has a small parasitic effect on a port signal, occupies a small area, is simple to wire, and is easy to layout. The protection structure human body model test reaches more than 4kV, and is suitable for each signal port of a high-speed memory circuit.

Description

ESD electrostatic protection structure suitable for high-speed memory circuit

Technical Field

The present invention relates to the field of integrated circuit technologies, and in particular, to an ESD protection structure for a high speed memory circuit.

Background

Integrated circuits are facing ESD (Electro-Static discharge) threats, and ESD protection circuits are continuously improving. Diode protection devices, ggNMOS (grounded gate NMOS) devices, Silicon Controlled Rectifier (SCR) devices, etc., are ESD electrostatic protection structures widely used in integrated circuits.

Different ESD protection devices are used in different types of circuits, and have their own advantages and disadvantages. When the conventional diode protection device works reversely, the current endurance capacity is low, and the on-resistance is large. The ggNMOS device has high trigger voltage and on-resistance, poor robustness in unit area, and large occupied area and parasitic capacitance. The SCR device has high process requirements, low retention voltage for hysteresis, and is liable to cause latch-up if improperly used.

The working frequency of the high-speed memory circuit exceeds 500MHz, and higher requirements are put on ESD protection devices of ports. The ESD device not only needs to realize the function of quickly discharging ESD current, but also needs to protect the internal circuit from being damaged, and cannot bring too large load to the port, otherwise, the accuracy of reading and writing data at high speed will be challenged.

Disclosure of Invention

The present invention is directed to an ESD protection structure for high speed memory circuits, which solves the problems of the prior art.

To solve the above technical problem, the present invention provides an ESD protection structure suitable for a high speed memory circuit, comprising:

the ESD electrostatic protection structure is integrally positioned in the independent deep N well and is not in direct contact with the P-type substrate; the deep N well isolates the ESD device from the P-type substrate, so that each ESD electrostatic protection structure is independent;

an N-well ring is arranged on the periphery of the deep N-well in a circle and is connected to a power supply through a well contact N + to provide a potential for the deep N-well;

and a circle of P-type substrate contact ring surrounds the periphery of the N-well ring to serve as isolation, and the P-type substrate contact ring is grounded.

Optionally, the ESD protection structure adopts a combination of a parasitic PNP triode, a parasitic NPN triode, and a diode, and has ESD leakage paths to both power and ground; wherein the content of the first and second substances,

the parasitic PNP triode comprises a P +, an N trap and a P trap; the P + is used as an emitting electrode of the parasitic PNP triode, is connected with an interface signal and is square; the N trap is used as a base electrode of the parasitic PNP triode, surrounds the P +, and has no trap contact; the P trap is used as a collector of the parasitic PNP triode and is grounded through a substrate contact P +, the substrate contact P + is annular and surrounds the periphery of the double N + rings;

the parasitic NPN triode comprises a double N + ring, a P trap and an N trap; the double N + rings are used as emitting electrodes of the parasitic NPN triodes, are grounded through metal wires and surround the periphery of the N trap; the P trap is used as a base electrode of the parasitic NPN triode and is grounded through substrate contact P +; the N trap is used as a collector of the parasitic NPN triode and is not contacted with the trap;

the diodes are 2N +/P trap diodes which are connected in parallel and respectively comprise an N + and a P trap; the two N + are connected with port signals and are in a strip shape; the P trap is grounded through a substrate contact N +, and the substrate contact P + surrounds the N + for one circle.

Optionally, the substrate contact P + is annular and surrounds the double N + ring.

In the ESD electrostatic protection structure suitable for the high-speed memory circuit, the quick ESD current discharge path is provided for both a power supply and the ground, the parasitic effect brought to a port signal is small, the occupied area of the whole ESD protection structure is small, the wiring is simple, and the layout is easy to arrange. The ESD HBM (human body model) test of the protection structure reaches more than 4kV, and the protection structure is suitable for each signal port of a high-speed memory circuit.

Drawings

Fig. 1 is a schematic plan view of an ESD electrostatic protection structure provided in the present invention;

FIG. 2 is a schematic diagram of a lateral structure of an ESD protection structure provided by the present invention;

fig. 3 is a schematic longitudinal structural diagram of the ESD electrostatic protection structure provided in the present invention.

Detailed Description

An ESD protection structure for a high speed memory circuit according to the present invention is further described in detail with reference to the accompanying drawings and the embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

The invention provides an ESD electrostatic protection structure suitable for a high-speed memory circuit, which is structurally shown in figure 1, wherein the upper part is a combination of a parasitic PNP triode and a parasitic NPN triode, the lower part is two N +/P well diodes which are connected in parallel, the ESD electrostatic protection structure adopts a mode of combining the parasitic PNP triode, the parasitic NPN triode and the diodes, and an ESD discharge path is arranged on a power supply and the ground. The whole structure is arranged in the deep N well 1 and is not in direct contact with the P-type substrate 11, the ESD device is isolated from the P-type substrate 11 by the deep N well 1, each ESD electrostatic protection structure is independent, and interference of high-frequency signals to a large substrate is avoided. An N-well ring 7 is arranged on the periphery of the deep N-well 1 in a circle, and the N-well ring 7 is connected to a power supply through a well contact N + to provide a potential for the deep N-well 1. The outer periphery of the N-well ring 7 is surrounded by a ring of grounded P-type substrate contact rings 9, which serve as isolation.

Fig. 2 is a schematic cross-sectional view of fig. 1 taken transversely, showing the vertical structure of the parasitic PNP transistor and parasitic NPN transistor. The central part is P +3 made in the N trap 2, the P +3 connects the port signal, it is the emitter of the parasitic PNP triode; the N trap 2 is a base electrode of a parasitic PNP triode, has no trap contact, but is indirectly connected with a power supply through the deep N trap 1, and is equivalent to be connected with the power supply through a section of N trap resistor in series. The P-well 10 adjacent to the N-well 2 forms the collector of the parasitic PNP transistor, the potential of the P-well 10 is provided by the substrate contact P +6, and the substrate contact P +6 is grounded during the chip operation, which is equivalent to connecting a segment of P-well resistor in series to the ground. Meanwhile, the P trap 10 is also used as a base electrode of the parasitic NPN triode and is grounded through a substrate contact P +6, the adjacent N traps 2 are collector electrodes and are not contacted with the traps, the grounded double N + rings 4 are emitter electrodes, the double N + rings 4 are grounded through metal wires, and the three parts form the parasitic NPN triode.

Fig. 3 is a schematic cross-sectional view of fig. 1 taken along a longitudinal cut, and the left half additionally illustrates the longitudinal structure of the N +/P well diode. The diode is composed of N +5 and a P-well 10, the potential of said P-well 10 being provided by a substrate contact P + 6. The N + ends of the N +/P well diodes are 2, the size is consistent, the N + ends are connected to the ports through metal wires, and the substrate contacts P +6 are annularly and symmetrically arranged around each N + end.

The ESD electrostatic protection structure has a rapid ESD current discharge path for both power and ground. When the port performs an ESD HBM (human body model) test on a power supply, if the port applies positive pulse relative to the power supply, a parasitic diode formed by the P +3 and the N trap 2 is conducted in the forward direction, and ESD current is discharged to the power supply through the deep N trap 1. If the port applies negative pulse relative to the power supply, current flows through the triggered ggNMOS device and flows through the N +/P well diode which is conducted in the positive direction by virtue of the ggNMOS device between the power supply and the ground, and an ESD leakage discharge circulation path is formed.

When an ESD (electro-static discharge) HBM (human body model) test is carried out on a port to the ground, if a positive pulse is applied to the port relative to the ground, a base region punch-through effect occurs when the parasitic PNP triode is narrow in base region width, and with the increase of voltage on the port, a P +/N well junction is positively biased, and the parasitic PNP triode is started. The current flows through the voltage drop formed by the equivalent P-well resistor, then the parasitic NPN triode is turned on, and the ESD current at the port is discharged to the ground. If the port applies a negative pulse relative to the ground, the N +/P well diode conducts in the forward direction, and ESD current is discharged rapidly.

The structure can be realized by conventional process steps without additional layout, and no matter positive or negative ESD pulse exists, the port has ESD discharge paths to a power supply and ground, so that the ESD design capability of HBM 4kV is achieved.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. An ESD protection structure for high speed memory circuits, comprising:

the whole ESD electrostatic protection structure is positioned in the independent deep N well (1) and is not in direct contact with the P-type substrate (11); the deep N well (1) isolates the ESD device from the P-type substrate (11), so that each ESD electrostatic protection structure is independent;

an N-well ring (7) is arranged on the periphery of the deep N-well (1) in a circle, and the N-well ring (7) is connected to a power supply through a well contact N + (8) to provide electric potential for the deep N-well (1);

the periphery of the N well ring (7) surrounds a circle of P-type substrate contact ring (9) to serve as isolation, and the P-type substrate contact ring (9) is grounded.

2. The ESD protection structure for high speed memory circuits according to claim 1, wherein the ESD protection structure employs a combination of parasitic PNP transistor, parasitic NPN transistor, and diode, with ESD leakage paths to both power and ground; wherein the content of the first and second substances,

the parasitic PNP triode comprises a P + (3), an N trap (2) and a P trap (10); the P + (3) is used as an emitting electrode of the parasitic PNP triode, is connected with an interface signal and is square; the N trap (2) is used as a base electrode of the parasitic PNP triode, surrounds the P + (3) and has no trap contact; the P trap (10) is used as a collector electrode of the parasitic PNP triode and is grounded through a substrate contact P + (6), and the substrate contact P + (6) is annular and surrounds the periphery of the double N + rings (4);

the parasitic NPN triode comprises a double N + ring (4), a P trap (10) and an N trap (2); the double N + rings (4) are used as emitting electrodes of the parasitic NPN triodes, are grounded through metal wires and surround the N trap (2); the P well (10) is used as a base electrode of the parasitic NPN triode and is grounded through a substrate contact P + (6); the N trap (2) is used as a collector of the parasitic NPN triode and has no trap contact;

the diodes are 2N +/P trap diodes which are connected in parallel and respectively comprise an N + (5) and a P trap (10); the two N + (5) are connected with port signals and are in a strip shape; the P trap (10) is grounded through a substrate contact N + (6), and the substrate contact P + (6) surrounds the N + (5) for one circle.

3. The ESD protection structure for high speed memory circuit according to claim 2, wherein the substrate contact P + (6) is ring-shaped and surrounds the double N + ring (4).