JPH03259553A - Resin sealing of lead frame and semiconductor device - Google Patents
Resin sealing of lead frame and semiconductor deviceInfo
- Publication number
- JPH03259553A JPH03259553A JP5885790A JP5885790A JPH03259553A JP H03259553 A JPH03259553 A JP H03259553A JP 5885790 A JP5885790 A JP 5885790A JP 5885790 A JP5885790 A JP 5885790A JP H03259553 A JPH03259553 A JP H03259553A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor chip
- lead frame
- chip support
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 title claims abstract description 79
- 229920005989 resin Polymers 0.000 title claims abstract description 79
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000007789 sealing Methods 0.000 title claims description 18
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000005538 encapsulation Methods 0.000 claims 1
- 230000007547 defect Effects 0.000 description 7
- 238000010292 electrical insulation Methods 0.000 description 7
- 238000000465 moulding Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の樹脂パンケージング技術に関し
、特に、Ｓ Ｉ Ｃ（Ｓｉｎｇｌｅ Ｉｎ−Ｌｉｎｅ
Ｐａｃｋａ−ｇｅ）タイプの樹脂パッケージにおいて適
用されるリードフレームの形状の改良とこの使用に適合
する半導体装置の樹脂封止法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to resin pancaging technology for semiconductor devices, and in particular, to SIC (Single In-Line) technology.
The present invention relates to an improvement in the shape of a lead frame used in a lead frame type resin package and a resin sealing method for a semiconductor device suitable for this use.
従来、パワートランジスタ等の樹脂封止形半導体装置に
使用されるリードフレームは、第３図に示すように、半
導体チップ２を半田付は等により固着すべき表面１ａ及
び外部ヒートシンクにネジ等を介して固定するための孔
１ｂを備えた放熱板の役割も果たす半導体チップ支持板
部ｌと、相隣接して連結した３本のり一ド３ａ、３ｂ、
３ｃとを有している。中央のり一ド３ｂは連結リードと
して半導体チップ支持板部１の一方の端部に屈曲部を介
して連結しており、また各リード３ａ、３ｂ、３ｃ・・
・は共通接続線条（ストリ・シブ）３ｄで連結されると
共に、各半導体チップ支持板部ｌの他方の端部も分岐連
結部４ａを介して１条の共通接続線条４に連結されてい
る。なお、この共通接続線条４のないリードフレームも
使用されている。Conventionally, a lead frame used for a resin-sealed semiconductor device such as a power transistor, as shown in FIG. a semiconductor chip support plate portion l which also serves as a heat sink and has a hole 1b for fixing the semiconductor chip;
3c. The central glue 3b is connected as a connecting lead to one end of the semiconductor chip support plate 1 via a bent part, and each lead 3a, 3b, 3c, . . .
* are connected by a common connecting line 3d, and the other end of each semiconductor chip support plate part l is also connected to one common connecting line 4 via a branch connecting part 4a. There is. Note that a lead frame without this common connection line 4 is also used.
この種のリードフレームを用いた半導体の組立において
は、まず半導体チップ支持板部１の孔１ｂとリード側の
端部との間に半導体チップ２がマウントされ、半導体チ
ップ２の電極とり−ド３ａ。In assembling a semiconductor using this type of lead frame, the semiconductor chip 2 is first mounted between the hole 1b of the semiconductor chip support plate 1 and the end on the lead side, and the electrode lead 3a of the semiconductor chip 2 is mounted. .
３Ｃにおいて共通接続線条３ｄから半導体チップ支持板
部側へ突出した領域とが金属細線５ａ、５ｂを以て電気
的に接続される。3C, a region protruding from the common connection line 3d toward the semiconductor chip support plate portion is electrically connected by thin metal wires 5a and 5b.
このようにマウンティングとボンディングが施されたリ
ードフレームに対する樹脂封止法としては、第４図（Ａ
）に示すように、上下の金型６゜７でリードフレームの
リード３ａ、３ｂ、３ｃ側と共通接続線条４側とを挟み
込み、金型キャビティ８内に半導体チップ２を搭載した
半導体チップ支持板部１を宙吊り状態に両端支持し、共
通接続線条４例のゲート部６ａから金型キャビティ８内
へ樹脂が充填される。その後共通接続線条３ｄ及び分岐
連結部４ａが切断される。これにより、第５図に示すよ
うに、半導体チップ支持板部１．半導体チップ２．金属
軸１！５ａ、５ｂの全周囲及びリード３ａ、３ｂ、３ｃ
の屈曲部近傍が樹脂材にて被覆される。モールドされた
樹脂外囲器９において半導体チップ支持板部１の表面ｌ
ａ側は肉厚部９ａで、裏面ｌｂ側は肉薄部９ｂとされて
いる。A resin sealing method for a lead frame that has been mounted and bonded in this way is shown in Figure 4 (A
), the leads 3a, 3b, 3c side and the common connection line 4 side of the lead frame are sandwiched between the upper and lower molds 6°7, and the semiconductor chip 2 is mounted in the mold cavity 8 to support the semiconductor chip. The plate portion 1 is supported at both ends in a suspended state, and resin is filled into the mold cavity 8 through the gate portions 6a of the four common connecting wires. Thereafter, the common connecting line 3d and the branch connecting portion 4a are cut. As a result, as shown in FIG. 5, the semiconductor chip support plate portion 1. Semiconductor chip 2. The entire periphery of the metal shafts 1!5a, 5b and the leads 3a, 3b, 3c
The vicinity of the bent portion is covered with a resin material. The surface l of the semiconductor chip support plate portion 1 in the molded resin envelope 9
The a side is a thick part 9a, and the back side lb is a thin part 9b.
また共通接続線条４のないリードフレームを使用する場
合には、第６図（Ａ）に示すように、上下の金型６．７
でリードフレームのリード３ａ。Furthermore, when using a lead frame without the common connecting line 4, as shown in FIG. 6(A), the upper and lower molds 6.
and lead 3a of the lead frame.
３ｂ、３ｃ側を挟み込んでこれを片持ち支持する一方、
その反対側の表裏面を位置決めピン１０ａ。While sandwiching the 3b and 3c sides and supporting this in a cantilever manner,
The front and back surfaces on the opposite side are positioning pins 10a.
１０ｂで支えた状態で保持し、しかる後第６図（Ｂ）に
示すように、ゲート部６ａ側から金型キャビティ８内へ
樹脂１１が充填される。この後共通接続線条３ｄが切断
される。これにより第７図に示すように樹脂外囲器１２
が成形され、半導体チップ支持板部１０表面ｌａ側は肉
厚部１２ａで、裏面ｌｂ側は肉薄部１２ｂとされている
（特開昭６３−６２２３９号）。The resin 11 is then held in a state where it is supported by the mold cavity 8 from the gate portion 6a side, as shown in FIG. 6(B). After this, the common connecting line 3d is cut. As a result, as shown in FIG. 7, the resin envelope 12
The semiconductor chip support plate portion 10 has a thick wall portion 12a on the front surface la side and a thin wall portion 12b on the back surface lb side (Japanese Unexamined Patent Publication No. 63-62239).
樹脂封止形半導体装置の肉薄部９ａ、１２ｂには例えば
第８図に示すようにネジ１３により外部ヒートシンク１
４が取付けられるため、肉薄部９ａ、１２ｂは熱伝導性
に優れていなければならないが、半導体チップ２と外部
ヒートシンク１４とはその肉薄部９ａ、１２ｂで電気的
絶縁を維持することが必要である。この電気的絶縁性は
肉薄部９ａ、１２ｂの樹脂層を厚くするほど高まるが、
反面、熱伝導性が悪化する。電気的絶縁性と熱伝導性を
共に満足する樹脂層の厚さは通常０．３〜０．６ｍｍ程
度とされ、樹脂封止法においては肉薄部９ａ、Ｉ２ｂの
樹脂層の均一な厚さ制御が重要である。For example, as shown in FIG. 8, an external heat sink 1 is attached to the thin wall portions 9a and 12b of the resin-sealed semiconductor device using screws 13.
4 is attached, the thin parts 9a and 12b must have excellent thermal conductivity, but it is necessary to maintain electrical insulation between the semiconductor chip 2 and the external heat sink 14 at the thin parts 9a and 12b. . This electrical insulation increases as the resin layer of the thin parts 9a and 12b becomes thicker.
On the other hand, thermal conductivity deteriorates. The thickness of the resin layer that satisfies both electrical insulation and thermal conductivity is usually about 0.3 to 0.6 mm, and in the resin sealing method, the thickness of the resin layer in the thin parts 9a and I2b is controlled to be uniform. is important.
ところで第４図に示す樹脂封止法においては、リードフ
レームの両端支持は確実であるので、肉薄部９ａの厚さ
制御が容易となり、上記の問題は発生しないものの、樹
脂封止後においては共通接続細条４の分岐連結部４ａを
切除するので、切り残し部４ａ’が必然的に生じてしま
う。この切り残し部４ａ’は外部ヒートシンクに近接し
ており、しかも切り残し部４ａは電界集中を誘起する尖
端を有するので、両者間には電気放電が発生する虞があ
る。By the way, in the resin sealing method shown in FIG. 4, since both ends of the lead frame are reliably supported, it is easy to control the thickness of the thin part 9a, and the above problem does not occur. Since the branch connecting portion 4a of the connecting strip 4 is cut off, an uncut portion 4a' is inevitably generated. This uncut portion 4a' is close to the external heat sink, and since the uncut portion 4a has a tip that induces electric field concentration, there is a possibility that electric discharge may occur between the two.
一方、第６図に示す樹脂封止法においては、共通接続線
条４のないリードフレームを使用するので、第５図に示
す如くの切り残し部４ａ′は存在しないが、片持ち支持
された半導体チップ支持板部工の先端を支える位置決め
ピン１０ａ、１０ｂが樹脂充填中の溶融樹脂状態下で引
き抜かれるため、その際、ゲート部６ａより注入する樹
脂の圧力によって半導体チップ支持板部ｌが上下に揺れ
動いてしまい、肉薄部１２ｂの樹脂厚の適正化を損なう
。On the other hand, in the resin sealing method shown in FIG. 6, since a lead frame without the common connection line 4 is used, there is no uncut portion 4a' as shown in FIG. Since the positioning pins 10a and 10b that support the tip of the semiconductor chip support plate are pulled out in the molten state during resin filling, the pressure of the resin injected from the gate part 6a causes the semiconductor chip support plate l to move up and down. This causes the resin to sway, impairing optimization of the resin thickness of the thin portion 12b.
また注入樹脂の圧力の影響を回避するため、半凝固状態
で位置決めピン１０ａ、１０ｂで引き抜くと、そのピン
跡に樹脂が廻り込み難く、未充填状態ままとなって成形
欠陥を生じる。特に肉薄部１２ｂの成形欠陥は電気的絶
縁性を損なう。Furthermore, in order to avoid the influence of the pressure of the injected resin, if the resin is pulled out in a semi-solidified state using the positioning pins 10a and 10b, the resin is difficult to wrap around the pin marks and remains in an unfilled state, resulting in molding defects. In particular, molding defects in the thin portion 12b impair electrical insulation.
そこで、本発明は上記問題点を解決するものであり、そ
の課題は、片持ち支持と位置決めピンによる支持であり
ながら、樹脂の導入方向の工夫と樹脂圧の利用により、
肉薄部側の位置決めピンを不要とし、樹脂充填時におけ
る位置決めピンの引き抜き過程での半導体チップ支持板
部の揺れ動きを極力防止して、樹脂外囲器の肉薄部の厚
さを均−適正比できると共に、取り付けるべき外部ヒー
トシンクとの間での電気放電の発生も解消できるような
リードフレームとこれを使用する半導体装置の樹脂封止
法を提供することにある。Therefore, the present invention is intended to solve the above-mentioned problems, and the problem is that while supporting with cantilever support and positioning pins, by devising the direction of resin introduction and using resin pressure,
Eliminates the need for positioning pins on the thin wall side, prevents swinging of the semiconductor chip support plate as much as possible during the process of pulling out the positioning pins during resin filling, and allows the thickness of the thin wall section of the resin envelope to be evenly and appropriately proportioned. Another object of the present invention is to provide a lead frame that can eliminate the occurrence of electrical discharge between it and an external heat sink to be attached, and a resin sealing method for a semiconductor device using the lead frame.
〔課題を解決するための手段］
上記課題を解決するために、本発明の講じた手段は、半
導体チップを固着すべき第１表面を有する半導体チップ
支持部と、相隣接して連結した複数のリードと、これら
リードのうち該半導体チップ支持部の一方の端部にて連
結した少なくとも１つの連結リードとを備えたリードフ
レームにおいて、該半導体チップ支持部の他方の端部に
て、第２表面側に臨む段差部又は傾斜部を備える張出部
を設けたものである。[Means for Solving the Problems] In order to solve the above problems, the means taken by the present invention is to provide a semiconductor chip support portion having a first surface to which a semiconductor chip is to be fixed, and a plurality of adjacently connected In a lead frame including a lead and at least one connecting lead among these leads connected at one end of the semiconductor chip support, the second surface is connected at the other end of the semiconductor chip support. It is provided with an overhanging portion having a stepped portion or an inclined portion facing the side.
またかかる形状のリードフレームを使用する半導体装置
の樹脂封止法において、本発明の講じた手段は、前記連
結リード側を金型で支持すると共に、前記金型キャビテ
ィ内の前記半導体チップ支持部の第２の表面側に対し前
記段差部又は傾斜部側を経由させて溶融樹脂を注入する
ものである。Further, in a method of resin encapsulating a semiconductor device using a lead frame having such a shape, the means taken by the present invention is such that the connecting lead side is supported by a mold, and the semiconductor chip supporting portion in the mold cavity is supported by a mold. The molten resin is injected into the second surface side via the stepped portion or the inclined portion side.
半導体チップ支持部の段差部側から金型キャビティ内へ
樹脂注入を行なうと、まず溶融樹脂は段差部又は傾斜部
により案内されて半導体チップ支持部の第２の表面側へ
充填される。第２の表面側での充填樹脂量が増すにつれ
、その樹脂圧により半導体チップ支持部が位置決めピン
側に押され、金型キャビティと第２の表面との間隔が所
定値に維持され、この隙間に樹脂が余すこなく充満する
。When resin is injected into the mold cavity from the stepped portion side of the semiconductor chip supporting portion, the molten resin is first guided by the stepped portion or the inclined portion and is filled into the second surface side of the semiconductor chip supporting portion. As the amount of resin filled on the second surface side increases, the resin pressure pushes the semiconductor chip support part toward the positioning pin side, and the distance between the mold cavity and the second surface is maintained at a predetermined value. is completely filled with resin.
このため底形される樹脂外囲器の肉薄部の厚さが常に適
正値に設定される。For this reason, the thickness of the thin portion of the bottom-shaped resin envelope is always set to an appropriate value.
注入樹脂量が更に増すと、第１の表面と金型キャビティ
との間に溶融樹脂が流れ込み充満することになる、。そ
して樹脂の充満が完了した直後、位置決めピンを金型キ
ャビティ内から引き抜くことにより、溶融樹脂がピン跡
にも廻り込むので、肉厚部側は殆ど成形欠陥が現れない
。If the amount of injected resin increases further, molten resin will flow and fill the space between the first surface and the mold cavity. Immediately after filling with resin is completed, by pulling out the positioning pin from the mold cavity, the molten resin also flows around the pin marks, so that almost no molding defects appear on the thick side.
このように、注入樹脂を案内導入するリードフレームの
段差部又は傾斜部の存在によって、金型キャビティ内で
第２の表面側の肉薄部底形空間にまず溶融樹脂を充満さ
せてから、次に第２の表面側の肉厚部底形空間に溶融樹
脂を充満させるいわば２段樹脂封止法であるため、露出
した切り残し部がなくて電気放電の発生の虞がないのは
勿論のこと、肉薄部の厚さが常に適正値に設定されるの
で、電気的絶縁性と熱伝導性が共に満たされ、また成形
欠陥等を極力排除できる。In this way, due to the presence of the stepped part or the inclined part of the lead frame that guides and introduces the injected resin, the bottom space of the thin wall part on the second surface side in the mold cavity is first filled with molten resin, and then Since it is a so-called two-stage resin sealing method in which the bottom-shaped space of the thick part on the second surface side is filled with molten resin, there is no exposed uncut portion and there is of course no risk of electrical discharge occurring. Since the thickness of the thin portion is always set to an appropriate value, both electrical insulation and thermal conductivity are satisfied, and molding defects can be eliminated as much as possible.
〔実施例］ 次に、本発明の実施例を添付図面に基づいて説明する。〔Example] Next, embodiments of the present invention will be described based on the accompanying drawings.
第１図（Ａ）は本発明に係るリードフレームの一実施例
を示す側面図で、第１図（Ｂ）は同実施例を示す正面図
である。FIG. 1(A) is a side view showing one embodiment of a lead frame according to the present invention, and FIG. 1(B) is a front view showing the same embodiment.
このリードフレームは金属材質からなり、半導体チップ
２を半田付は等により固着すべき第１の表面１ａ及び外
部ヒートシンクにネジ等を介して固定するための孔１ｂ
を備えた放熱板の役割も果たす半導体チップ支持板部１
と、相隣接して連結した３本のリード３ａ、３ｂ、３ｃ
とを有しており、中央のり一ド３ｂは半導体チップ支持
板部１の一方の端部に屈曲部を介して連結している。ま
た各リード３ａ、３ｂ、３ｃ・・・は共通接続線条（ス
トリップ）３ｄで連結されている。半導体チ・ンプ支持
板部１の孔１ｂと下端との間には半導体チップ２がマウ
ントされ、半導体チップ２の電極とり一ド３ａ、３ｃの
共通接続線条３ｄから半導体チップ支持板部側へ突出し
た領域とが金属細線５ａ、５ｂを以て電気的に接続され
る。This lead frame is made of a metal material, and has a first surface 1a to which the semiconductor chip 2 is fixed by soldering or the like, and a hole 1b for fixing it to an external heat sink via a screw or the like.
Semiconductor chip support plate part 1 that also serves as a heat sink with
and three leads 3a, 3b, 3c connected adjacent to each other.
The central glue 3b is connected to one end of the semiconductor chip support plate portion 1 via a bent portion. Further, the leads 3a, 3b, 3c, . . . are connected by a common connecting line (strip) 3d. A semiconductor chip 2 is mounted between the hole 1b and the lower end of the semiconductor chip support plate 1, and a common connection line 3d of the electrode leads 3a, 3c of the semiconductor chip 2 is connected to the semiconductor chip support plate side. The protruding regions are electrically connected using thin metal wires 5a and 5b.
半導体チップ支持板部１においてリード側とは反対側の
端部には第１図（Ａ）に示すような段差部２０ａを有す
る張出部２０が一体的に連結されている。この張出部２
０の幅は半導体チップ支持板部１と同幅状に形成されて
おり、段差部２０ａは第１の表面１、ａの裏面の第２の
表面ＩＣ側に向いている。An overhang 20 having a step 20a as shown in FIG. 1(A) is integrally connected to the end of the semiconductor chip support plate 1 opposite to the lead side. This overhang 2
0 is formed to have the same width as the semiconductor chip support plate portion 1, and the stepped portion 20a faces the second surface IC side of the back surface of the first surface 1, a.
また張出部２０はその厚さ方向で第１の表面１ａより段
差部２０ａの段差部だけ突出している。Further, the projecting portion 20 projects from the first surface 1a in the thickness direction by the step portion of the step portion 20a.
まず、第２図（Ａ）に示すように、金型１６．１７でリ
ード３ａ、３ｂ、３ｃ側を挟み込み、金型キャビティイ
エ８内でリードフレームを片持ち支持する。この片持ち
支持構造を採用する点は第６図に示す従来方法と同様で
あるが、張出部２０における第１の表面ｌａ側には位置
決めピン１９を繰り出し臨ませであるものの、第２の表
面ＩＣ側には位置決めピンが存在せず、この点が第６図
に示す従来方法と相違する。したがって第２の表面ＩＣ
側には位置決めピンがないので、金型キャビティイエ８
内のリードフレームは撓んでいる。First, as shown in FIG. 2A, the leads 3a, 3b, and 3c are sandwiched between the molds 16 and 17, and the lead frame is cantilevered in the mold cavity 8. The adoption of this cantilever support structure is similar to the conventional method shown in FIG. There is no positioning pin on the front IC side, which is different from the conventional method shown in FIG. 6. Therefore, the second surface IC
There is no positioning pin on the side, so the mold cavity
The lead frame inside is bent.
次に、段差部２０ａ側に臨むゲート部１６ａから金型キ
ャビティ４１日内へ溶融樹脂Ｐを注入する。注入された
溶融樹脂Ｐはまず段差部２０ａに進入し、第２図（Ｂ）
に示すように、その樹脂圧で張出部２０側を押し上げる
。張出部２０の浮き上がりはストツパとして機能する位
置決めピン１つにより所定位置で抑止され、これにより
第２の表面ＩＣと金型１７との間に所定の間隙Ｇ（本実
施例では約１ｍｍ）が維持されることになる。この開か
れた間隙Ｇへ溶融樹脂Ｐが徐々に送り込まれ、この間隙
Ｇが溶融樹脂Ｐで充満すると、溶融樹脂Ｐは第１の表面
ｌａ側に進入し、やがて金型キャビティイエ８内には溶
融樹脂Ｐが充満する。そして溶融樹脂Ｐの充填が完了す
る際、位置決めピン１９が引き抜かれる。Next, the molten resin P is injected into the mold cavity 41 from the gate portion 16a facing the stepped portion 20a side. The injected molten resin P first enters the stepped portion 20a, and as shown in FIG.
As shown in , the resin pressure pushes up the projecting portion 20 side. Lifting of the overhang 20 is prevented at a predetermined position by a single positioning pin that functions as a stopper, thereby creating a predetermined gap G (approximately 1 mm in this embodiment) between the second surface IC and the mold 17. It will be maintained. The molten resin P is gradually fed into this opened gap G, and when this gap G is filled with the molten resin P, the molten resin P enters the first surface la side and eventually enters the mold cavity 8. It is filled with molten resin P. Then, when filling with the molten resin P is completed, the positioning pin 19 is pulled out.
位置決めピン１９の引抜き時点では間隙Ｇの樹脂の硬化
が第１表面ｌａ側の溶融樹脂のそれに比して進んでいる
ので、位置決めピンＩ９の引抜きによって間隙Ｇの厚さ
変化を惹起することはなく、またピン跡に溶融樹脂が充
分廻り込むので、成形欠陥も問題とならない。At the time of pulling out the positioning pin 19, the hardening of the resin in the gap G is more advanced than that of the molten resin on the first surface la side, so pulling out the positioning pin I9 does not cause a change in the thickness of the gap G. Also, since the molten resin sufficiently wraps around the pin marks, molding defects do not become a problem.
換言すれば、封止工程においては、注入樹脂を段差部２
０の案内作用で肉薄部を形成すべき領域に導入し、その
樹脂圧を利用して肉薄部の厚さが適正値に自動設定され
る。このため、封止時における第２の表面ｌｃ側すなわ
ち肉薄部側の位置決めピンの使用を排除できたので、肉
薄部側の電気的絶縁性の劣化や成形欠陥などが解消され
、信頼性の高い樹脂封止型半導体装置を提供できる。In other words, in the sealing process, the injected resin is
The resin is introduced into the area where the thin part is to be formed by the guiding action of 0, and the thickness of the thin part is automatically set to an appropriate value using the resin pressure. Therefore, the use of positioning pins on the second surface lc side, that is, on the thin wall side, during sealing can be eliminated, eliminating deterioration of electrical insulation and molding defects on the thin wall side, resulting in high reliability. A resin-sealed semiconductor device can be provided.
なお、上記実施例における張出部２０すなわち段差部２
０ａは溶融樹脂の金型キャビティ内への導入方向をリー
ドフームの第２の表面下に向ける意義を有するものであ
り、この機能を備える形状であれば上記張出部２０すな
わち段差部２０ａに限らない。Note that the projecting portion 20 in the above embodiment, that is, the stepped portion 2
0a has the meaning of directing the introduction direction of the molten resin into the mold cavity below the second surface of the lead frame, and is not limited to the above-mentioned overhanging part 20, that is, the step part 20a, as long as it has a shape that has this function. .
例えば張出部が傾斜したものでも良いが、位置決めピン
との当接位置の精度にバラツキを生しないよう傾斜角精
度を入念に設定する必要があろう。For example, the projecting portion may be inclined, but it is necessary to carefully set the inclination angle accuracy so as not to cause variations in the accuracy of the contact position with the positioning pin.
また張出部２０の幅は半導体チップ支持板部の幅と同一
である必要もなく、単にリードフレームの製作容易性の
点から等帽状に設定される。Further, the width of the projecting portion 20 does not need to be the same as the width of the semiconductor chip support plate portion, and is set to have a uniform cap shape simply from the viewpoint of ease of manufacturing the lead frame.
以上説明したように、本発明は、樹脂封止時における溶
融樹脂の注入方向を案内規制する手段としてリードフレ
ーム側に段差部を設け、またかかる形状のリードフレー
ムを使用する樹脂封止法において樹脂圧を利用して成形
すべき肉薄部の厚さを均一に制御する点に特徴を有する
ものであるから、次の効果を奏する。As explained above, the present invention provides a stepped portion on the lead frame side as a means for guiding and regulating the injection direction of molten resin during resin sealing, and also provides resin in a resin sealing method using a lead frame having such a shape. Since it is characterized in that the thickness of the thin part to be formed is uniformly controlled using pressure, the following effects are achieved.
すなわち、リードフレームの露出した切り残し部がなく
、取付けられる外部ヒートシンクとの間に電気放電の発
生の虞がないのは勿論のこと、肉薄部の厚さが常に適正
値に設定されるので、電気的絶縁性と熱伝導性が共に満
たされる。また封止工程において肉薄部側を位置決め部
材で支持する必要がないので、ピン跡などの成形欠陥が
発生せず、高信頼性の樹脂封止型半導体装置を提供でき
る。In other words, there is no exposed uncut portion of the lead frame, and there is no risk of electrical discharge occurring between the lead frame and the attached external heat sink, and the thickness of the thin wall portion is always set to an appropriate value. Both electrical insulation and thermal conductivity are satisfied. Furthermore, since there is no need to support the thin portion side with a positioning member in the sealing process, molding defects such as pin marks do not occur, and a highly reliable resin-sealed semiconductor device can be provided.
第１図（Ａ）は本発明に係るリードフレームの一実施例
を示す側面図で、第１図（Ｂ）は同実施例を示す正面図
である。
第２図（Ａ）、 （Ｂ）は第１図示リードフレームを
使用した樹脂封止法を示す縦断面図である。
第３図は、従来樹脂封止形半導体装置に使用されるリー
ドフレームの一例を示す正面図である。
第４図は、第３図示のリードフレームを使用する樹脂封
止法を示す縦断面図である。
第５図、は同樹脂封止法により作製された樹脂封止形半
導体装置を縦断面図である。
第６図（Ａ）、（Ｂ）は従来の別のリードフレ−ムを使
用する樹脂封止法を示す縦断面図である。
第７図（Ａ）は同樹脂封止法により作製された樹脂封止
形半導体装置を縦断正面図で、第７図（Ｂ）は同装置の
縦断側面図である。
第８図は第７図示の樹脂封止形半導体装置に外部ヒート
シンクを取り付けた状態を示す斜視図である。
〔符号の説明〕
１・・・半導体チップ支持板部
Ｌａ・・・第１の表面
１ｂ・・・孔
１ｃ・・・第２の表面
２・−・半導体チップ
３ ａ、 ３ ｂ、 ３ ｃ・−リード３ｄ・・・
共通接続線条
５ａ、５ｂ・・−金属細線
１６、１７・・・金型
１６ａ・・・ゲート部
１８・・・金型キャビティ
１９・・・位置決めピン
２０・・・張出部
２０ａ・・・段差部
Ｐ・・・溶融樹脂。FIG. 1(A) is a side view showing one embodiment of a lead frame according to the present invention, and FIG. 1(B) is a front view showing the same embodiment. FIGS. 2A and 2B are vertical sectional views showing a resin sealing method using the lead frame shown in the first figure. FIG. 3 is a front view showing an example of a lead frame used in a conventional resin-sealed semiconductor device. FIG. 4 is a longitudinal sectional view showing a resin sealing method using the lead frame shown in FIG. FIG. 5 is a longitudinal cross-sectional view of a resin-sealed semiconductor device manufactured by the same resin-sealing method. FIGS. 6(A) and 6(B) are vertical sectional views showing another conventional resin sealing method using a lead frame. FIG. 7(A) is a longitudinal sectional front view of a resin-sealed semiconductor device manufactured by the same resin encapsulating method, and FIG. 7(B) is a longitudinal sectional side view of the same device. FIG. 8 is a perspective view showing the resin-sealed semiconductor device shown in FIG. 7 with an external heat sink attached. [Explanation of symbols] 1... Semiconductor chip support plate portion La... First surface 1b... Hole 1c... Second surface 2... Semiconductor chip 3 a, 3 b, 3 c... -Lead 3d...
Common connection filaments 5a, 5b...-Thin metal wires 16, 17...Mold 16a...Gate portion 18...Mold cavity 19...Positioning pin 20...Protrusion portion 20a... Stepped portion P: Molten resin.
Claims (2)
体チップ支持部と、相隣接して連結した複数のリードと
、これらリードのうち該半導体チップ支持部の一方の端
部にて連結した少なくとも１つの連結リードとを備え、
該半導体チップ支持部の他方の端部側にて、第１の表面
とは反対側の第２表面側に臨む段差部又は傾斜部を有す
る張出部が形成されていることを特徴とするリードフレ
ーム。(1) A semiconductor chip support portion having a first surface to which a semiconductor chip is to be fixed, a plurality of leads connected adjacent to each other, and at least one of these leads connected at one end of the semiconductor chip support portion. Equipped with one connecting lead,
A lead characterized in that, on the other end side of the semiconductor chip support part, an overhang part having a stepped part or an inclined part facing a second surface side opposite to the first surface is formed. flame.
半導体装置の樹脂封止法であって、前記連結リード側を
金型で支持すると共に、前記半導体チップ支持部の第１
表面側に対し少なくとも１つの位置決め部材を配した後
、少なくとも溶融樹脂の充填初期においては、前記金型
キャビティ内の前記半導体チップ支持部の第２の表面側
に対し前記段差部又は傾斜部側を経由させて溶融樹脂を
注入することを特徴とする半導体装置の樹脂封止法。(2) A resin sealing method for a semiconductor device using the lead frame according to claim 1, wherein the connecting lead side is supported by a mold, and the first part of the semiconductor chip supporting part is
After disposing at least one positioning member on the front surface side, at least in the initial stage of filling the molten resin, the stepped portion or the inclined portion side is placed on the second surface side of the semiconductor chip support portion in the mold cavity. A resin encapsulation method for semiconductor devices characterized by injecting molten resin through the resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5885790A JPH03259553A (en) | 1990-03-09 | 1990-03-09 | Resin sealing of lead frame and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5885790A JPH03259553A (en) | 1990-03-09 | 1990-03-09 | Resin sealing of lead frame and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03259553A true JPH03259553A (en) | 1991-11-19 |
Family
ID=13096373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5885790A Pending JPH03259553A (en) | 1990-03-09 | 1990-03-09 | Resin sealing of lead frame and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03259553A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156606A (en) * | 2004-11-29 | 2006-06-15 | Nippon Inter Electronics Corp | Method for manufacturing semiconductor device |
-
1990
- 1990-03-09 JP JP5885790A patent/JPH03259553A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156606A (en) * | 2004-11-29 | 2006-06-15 | Nippon Inter Electronics Corp | Method for manufacturing semiconductor device |
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