JPH03259521A - Manufacture of soi substrate - Google Patents

Manufacture of soi substrate

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Publication number
JPH03259521A
JPH03259521A JP5890090A JP5890090A JPH03259521A JP H03259521 A JPH03259521 A JP H03259521A JP 5890090 A JP5890090 A JP 5890090A JP 5890090 A JP5890090 A JP 5890090A JP H03259521 A JPH03259521 A JP H03259521A
Authority
JP
Japan
Prior art keywords
layer
grooves
layers
thin
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5890090A
Other languages
Japanese (ja)
Inventor
Toru Miyayasu
宮保 徹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5890090A priority Critical patent/JPH03259521A/en
Publication of JPH03259521A publication Critical patent/JPH03259521A/en
Pending legal-status Critical Current

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  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To obtain a superthin film SOI substrate having an Si active layer of uniform thickness, by a method wherein, after a stuck SOI substrate is formed, trenches wherein widths and intervals are changed are formed to a depth wherein an SiO2 layer is exposed. CONSTITUTION:SiO2 of Si substrate, on which surfaces SiO2 films are formed, are brought into contact with each other and heated, thereby sticking the substrates. A thinly polished Si layer 5a is formed on an Si substrate 3, via an SiO2 layer 4. By patterning the Si layer 5a, narrow trenches 6a-6k of 2mum in width are formed to expose the SiO2 layer, 4 thereby forming Si layers 7a-7d and narrow Si layers 8a-8h. Amine based aqueous solution wherein the Si polishing speed is much higher than the SiO2 polishing speed is used; polishing is performed by using an expanded polyurethane cloth; all Si layers 8a-8h are eliminated and very thin Si layers 9a-9d constituted of the residual Si layers 7a-7d are formed. By this constitution, a superthin film SOI substrate having a very thin Si active layer of uniform thickness can be obtained.

Description

【発明の詳細な説明】 〔概要] SOI基板の製造方法に係り、特に張り合わせSOI基
板の製造方法に関し。
DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing an SOI substrate, particularly a method of manufacturing a bonded SOI substrate.

均一な厚さの極薄Si層を有するSOI蟇板を形成する
方法を目的とし。
The purpose of this study is to provide a method for forming an SOI tombstone having an ultrathin Si layer of uniform thickness.

5iOz層と、該SiO□層の上下のSi層からなる張
り合わせSOI基板の片面を研削して、FilいSi層
を形成する工程と、該薄いSi層にSiO□層を露出す
る複数の溝を形成し、溝間の距離の大きいSi層と溝間
の距離の小さいSi層を形成する工程と、 Singに
対してSiを選択的に研磨する研磨剤を用いて全面を研
磨する工程とを有し、前記溝間の距離の小さいSi層を
研磨除去して、 SiO□層を露出するとともに、前記
溝間の距離の大きいSi層を残して極薄Si層を形成す
るSOI基板の製造方法により構成する。
A step of grinding one side of a bonded SOI substrate consisting of a 5iOz layer and Si layers above and below the SiO□ layer to form a thin Si layer, and forming a plurality of grooves in the thin Si layer to expose the SiO□ layer. A process of forming an Si layer with a large distance between grooves and a Si layer with a small distance between grooves, and a process of polishing the entire surface using an abrasive that selectively polishes Si with respect to Sing. Then, according to a method for manufacturing an SOI substrate, the Si layer with a small distance between the grooves is removed by polishing to expose the SiO□ layer, and the Si layer with a large distance between the grooves is left to form an extremely thin Si layer. Configure.

〔産業上の利用分野〕[Industrial application field]

本発明はSO■基板の製造方法に係り、特に張り合わせ
SOI基板の製造方法に関する。
The present invention relates to a method for manufacturing an SOI substrate, and more particularly to a method for manufacturing a bonded SOI substrate.

SOI基板は素子特性や素子間分離の点でバルク基板よ
り優れているが、そのなかでも、バルクの結晶性が生か
せる張り合わせSOI基板が注目されている。
SOI substrates are superior to bulk substrates in terms of element characteristics and isolation between elements, but among them, bonded SOI substrates that take advantage of bulk crystallinity are attracting attention.

第3図(a)乃至(c)は張り合わせSOI基板の製造
工程を示す。
FIGS. 3(a) to 3(c) show the manufacturing process of a bonded SOI substrate.

表面に5iOz膜1bの形成されたSi基板1aと2表
面にSiO2膜2bの形威されたSi基板2aの5i0
2膜を向き合わせる(第3図(a)参照)。
Si substrate 1a with 5iOz film 1b formed on the surface and 5i0 of Si substrate 2a with SiO2 film 2b formed on the surface.
The two membranes are faced to each other (see Figure 3(a)).

Si基板1aとSi基板2aのSiO□膜を接触させて
加熱し張り合わせる。片側のSi基板は支持基板3とな
り1反対側のSi基板は将来Si活性層を形成する素子
基板5となり、その間にSiO□層4が形威される(第
3図(b)参照)。
The SiO□ films of the Si substrate 1a and the Si substrate 2a are brought into contact and heated and bonded together. The Si substrate on one side becomes a supporting substrate 3, and the Si substrate on the opposite side becomes an element substrate 5 on which a Si active layer will be formed in the future, and a SiO□ layer 4 is formed between them (see FIG. 3(b)).

素子基板5を研削して薄いSi層5aを得る(第3図(
c)参照)。
The element substrate 5 is ground to obtain a thin Si layer 5a (see Fig. 3).
c).

このような張り合わせSOI基板の中でも、Si活性層
の膜厚が0.5μm以下の超薄膜SOI基板が、近年注
目されている。この超薄膜SOI基板の作製においては
、素子形成を行うSi活性層の膜厚の面内のばらつきを
支持基板3の厚さのばらつき以下に抑える必要があるこ
とから、裏面基準の研削技術や研磨技術を用いてSi活
性層を形成することは不可能であり、均一な厚さのSi
活性層を形成できる新しい技術が必要である。
Among such bonded SOI substrates, ultra-thin film SOI substrates in which the Si active layer has a thickness of 0.5 μm or less have attracted attention in recent years. In manufacturing this ultra-thin film SOI substrate, it is necessary to suppress in-plane variations in the thickness of the Si active layer on which elements are formed to less than variations in the thickness of the supporting substrate 3. It is impossible to form a Si active layer using techniques, and it is impossible to form a Si active layer with a uniform thickness.
New techniques are needed to form active layers.

(従来の技術〕 超薄膜SOI基板作製の従来例の製造工程を第2図(a
)乃至(e)に示す。以下、これらの図を参照しながら
説明する。
(Prior art) The conventional manufacturing process for producing an ultra-thin SOI substrate is shown in Figure 2 (a).
) to (e). The following description will be made with reference to these figures.

第2図(a)参照 この図は支持基板3上にSiO□層4.その上に薄いS
i層5の形成された張り合わせ基板を示す。
Refer to FIG. 2(a). This figure shows a SiO□ layer 4 on a support substrate 3. A thin S on top of that
A laminated substrate on which an i-layer 5 is formed is shown.

第2図(b)参照 薄いSi層5に溝6を形威してSiO□層4を露出させ
る。
Refer to FIG. 2(b), a groove 6 is formed in the thin Si layer 5 to expose the SiO□ layer 4.

第2図(c)参照 全面に2例えばCVD法によりSiO□を堆積し。See Figure 2(c) For example, SiO□ is deposited on the entire surface by the CVD method.

5iOz膜10を形威する。A 5iOz film 10 is formed.

第2図(d)参照 SiO□膜10をマスクを用いてパターニングすること
により、溝6の底にのみSiO□膜10を残す。
By patterning the SiO□ film 10 using a mask (see FIG. 2(d)), the SiO□ film 10 is left only at the bottom of the groove 6.

第2図(e)参照 Siは研磨されるがSiO□は研磨されないアミン系水
溶液を用いて研磨し、薄いSi層5aの高さを5in2
膜10の上面と一致するまで減じる。
Refer to FIG. 2(e).Si is polished but SiO□ is not polished. Polishing is performed using an amine-based aqueous solution, and the height of the thin Si layer 5a is reduced to 5in2.
Reduce until it coincides with the top surface of membrane 10.

このようにして、 5iOz膜10の厚さのSi活性層
を持つ超薄膜SOI基板が作製される。
In this way, an ultra-thin SOI substrate having a Si active layer with a thickness of 5iOz film 10 is fabricated.

ところで、この従来法は、全面に5iOz膜10を形威
し1次にマスクを用いてこのSiO□膜10をパターニ
ングして溝6の底にのみSiQ□膜10を残す工程が煩
雑であり、また、マスク合わせがずれると、残る5i(
h膜10が溝6からはみ出てしまうといった問題があっ
た。
By the way, in this conventional method, the process of forming the 5iOz film 10 on the entire surface and patterning the SiO□ film 10 using a primary mask to leave the SiQ□ film 10 only at the bottom of the groove 6 is complicated. Also, if the mask alignment is misaligned, the remaining 5i (
There was a problem that the h-film 10 protruded from the groove 6.

〔発明が解決しようとする課題] 本発明は、全面に5iOz膜10を形成し1次にマスク
を用いてこの5i02膜10をパターニングして溝6の
底にのみSiO□膜10を残すという上述の工程を必要
とせず、しかも均一な厚さのSi活性層を持つ超3yS
0)基板を作製できる方法を提供することを目的とする
[Problems to be Solved by the Invention] The present invention has the above-mentioned method in which a 5iOz film 10 is formed on the entire surface and the 5iO2 film 10 is first patterned using a mask to leave the SiO□ film 10 only at the bottom of the groove 6. Super 3yS that does not require any process and has a Si active layer of uniform thickness.
0) The purpose is to provide a method for manufacturing a substrate.

[課題を解決するための手段] 第1図(a)乃至(d)は本発明の実施例の製造工程を
示す断面図である。
[Means for Solving the Problems] FIGS. 1(a) to 1(d) are cross-sectional views showing the manufacturing process of an embodiment of the present invention.

上記課題は、 SiO□層4と、該5tOz層4の上下
のSi層からなる張り合わせSOI基板の片面を研削し
て、薄いSi層5aを形成する工程と、該薄いSi層5
aに5iOz層4を露出する複数の溝6a乃至6kを形
威し、溝間の距離の大きいSi層7a乃至7dと溝間の
距離の小さいSi層8a乃至8hを形成する工程と、 
SiO□に対してSiを選択的に研磨する研磨剤を用い
て全面を研磨する工程とを有し、前記溝間の距離の小さ
いSi層8a乃至8hを研磨除去して、 SiO□層を
露出するとともに、前記溝間の距離の大きいSi層7a
乃至7dを残して極薄Si層9a乃至9dを形成するS
Ol基板の製造方法によって解決される。
The above-mentioned problems include a step of grinding one side of a bonded SOI substrate consisting of an SiO□ layer 4 and Si layers above and below the 5tOz layer 4 to form a thin Si layer 5a, and a step of forming a thin Si layer 5a.
a step of forming a plurality of grooves 6a to 6k exposing the 5iOz layer 4, and forming Si layers 7a to 7d with large distances between the grooves and Si layers 8a to 8h with small distances between the grooves;
A step of polishing the entire surface using an abrasive that selectively polishes Si with respect to SiO□, and polishing away the Si layers 8a to 8h with a small distance between the grooves to expose the SiO□ layer. At the same time, the Si layer 7a having a large distance between the grooves
S to form ultra-thin Si layers 9a to 9d, leaving 7d to 7d.
This problem is solved by a method for manufacturing an Ol substrate.

〔作用〕[Effect]

本発明では、薄いSii層aにSiO□層4を露出する
複数の溝68乃至6kを形成し、溝間の距離の大きいS
ii層a乃至7dと溝間の距離の小さいSii層a乃至
8hを形成している。このような状態を、 SiO□に
対してSiを選択的に研磨する研磨剤を用いて全面を研
磨すると、溝間の距離の小さいSii層a乃至8hが溝
間の距離の大きいSii層a乃至7dよりも研磨速度が
大きくなり、さらに、溝間の距離の小さいSii層a乃
至8hが研磨除去されてSiO□FJ4が露出して露出
するSiO2層4の面積が大きくなると、残存する溝間
の距離の大きいSii層a乃至7dはほとんど研磨され
なくなる。これは本発明者が発見した現象で何故そのよ
うになるかというと、溝間の距離の小さいSi層では溝
間の距離の大きいSi層に比べて研磨時にかかる圧力が
大きく、研磨剤の入替え速度が大きいために研磨速度が
大きくなり、さらに。
In the present invention, a plurality of grooves 68 to 6k are formed in the thin Sii layer a to expose the SiO□ layer 4, and S
Sii layers a to 8h having a small distance between the grooves are formed with the Sii layers a to 7d. When such a state is polished on the entire surface using a polishing agent that selectively polishes Si with respect to SiO When the polishing rate is higher than 7d, and when the Sii layers a to 8h with the short distance between the grooves are removed by polishing and the exposed area of the SiO2 layer 4 becomes large, the area between the remaining grooves becomes larger. The Sii layers a to 7d, which have a large distance, are hardly polished. This is a phenomenon discovered by the present inventor, and the reason why it happens is that the pressure applied during polishing is greater in a Si layer with a small distance between grooves than in a Si layer with a large distance between grooves, and the polishing agent must be replaced. The polishing rate is large due to the large speed, and even more.

露出するSing層の面積が大きくなると、研磨剤は露
出したSing層の上を流れて残存する溝間の距離の大
きいSi[に供給されなくなるからであると考えられる
This is believed to be because when the exposed area of the Sing layer becomes larger, the abrasive flows over the exposed Sing layer and is no longer supplied to the remaining Si where the distance between the grooves is large.

残存する溝間の距離の大きいSi層の厚さは研磨の際の
圧力、溝間の距離の小さいSi層との面積の比、溝の幅
とその本数等によって変えることができる。溝の幅、溝
の本数、溝間の距離の小さいSi層の数を増やすと残存
する溝間の距離の大きいSi層の厚さは大きくなる傾向
にある。
The thickness of the remaining Si layer with a large distance between grooves can be changed depending on the pressure during polishing, the area ratio to the Si layer with a small distance between grooves, the width of the grooves, the number of grooves, etc. If the width of the grooves, the number of grooves, and the number of Si layers with small distances between grooves are increased, the thickness of the remaining Si layers with large distances between grooves tends to increase.

それゆえ、溝間の距離の大きいSi層の面積と厚さに応
じて、溝の幅、溝の本数、溝間の距離の小さいSi層の
幅と数を選択することにより1極’FJt S i層を
もつ張り合わせSOI基板を作製することができる。
Therefore, by selecting the groove width, the number of grooves, and the width and number of the Si layer with a small distance between grooves according to the area and thickness of the Si layer with a large distance between grooves, a single-pole 'FJt S A bonded SOI substrate with an i-layer can be produced.

〔実施例] 第1図(a)乃至(d)は超薄膜SOI基板を製造する
実施例の製造工程を示す断面図であり、以下これらの図
を参照しながら説明する。
[Example] FIGS. 1(a) to 1(d) are cross-sectional views showing the manufacturing process of an example for manufacturing an ultra-thin film SOI substrate, and the following description will be made with reference to these figures.

第1図(a)参照 厚さ0.5μmのSiO□膜の形成されたSi基板を張
り合わせ、その片面を研削して厚さ2μmまで薄膜化す
る。第1図(a)で3は厚さ600μmのSi基板、4
は厚さ1μmのSiO□層、 5aは厚さ2μmの薄い
Si層である。
Referring to FIG. 1(a), Si substrates on which a SiO□ film with a thickness of 0.5 μm has been formed are bonded together, and one side thereof is ground to reduce the thickness to 2 μm. In Fig. 1(a), 3 is a 600 μm thick Si substrate, 4
5a is a SiO□ layer with a thickness of 1 μm, and 5a is a thin Si layer with a thickness of 2 μm.

第1図(b)参照 薄いSii層aを通常のフォトリソグラフィーの工程に
よりパターニングして2幅2μmの複数の溝6a乃至6
kを形成し5102層4を露出させる。
Refer to FIG. 1(b), a thin Sii layer a is patterned by a normal photolithography process to form a plurality of grooves 6a to 6 with a width of 2 μm.
5102 layer 4 is exposed.

溝の間隔の広い所では溝間の距離の大きいSii層a乃
至?d C幅40μm)が形成される。溝の間隔の小さ
い所では溝間の距離の小さいSii層a乃至8h(幅2
μm)が形成される。
In places where the grooves are widely spaced, Sii layers a to ? dC width 40 μm) is formed. In places where the distance between the grooves is small, Sii layers a to 8h (width 2
μm) is formed.

第1図(c)参照 研磨剤としてSiの研磨速度がSingの研磨速度に比
べて10’倍以上大きいアミン系水溶液を用い研磨布と
して発泡ポリウレタンパッドを用いて研磨した。
Referring to FIG. 1(c), polishing was carried out using an amine-based aqueous solution in which the polishing rate of Si is 10' times higher than that of Sing as a polishing agent, and a foamed polyurethane pad as a polishing cloth.

溝間の距離の小さいSii層a乃至8hに対する研磨速
度は溝間の距離の大きいSii層a乃至7dに対する研
磨速度よりも大きかった。
The polishing rates for Sii layers a to 8h with short distances between grooves were higher than the polishing rates for Sii layers a to 7d with long distances between grooves.

第1図(d)参照 さらに研磨をつづけ、溝間の距離の小さいSii層a乃
至8hが研磨除去され、その下のSing層4が露出す
ると、 SiO□層4が研磨されなくなるだけでなく、
残存する距離の大きい5iFJ7a乃至7dも研磨され
なくなった。そして、Si層の厚さが0.l ±0.0
1μmの極薄31層9a乃至9dが得られた。極薄31
層9a乃至9dは厚さの均一性は良好であった。
Refer to FIG. 1(d) When the polishing is continued and the Sii layers a to 8h with the short distance between the grooves are removed by polishing and the Sing layer 4 underneath is exposed, not only the SiO□ layer 4 is no longer polished.
5iFJ7a to 7d, which had a large remaining distance, were no longer polished. Then, the thickness of the Si layer is 0. l ±0.0
Thirty-one ultrathin layers 9a to 9d of 1 μm were obtained. Ultra thin 31
Layers 9a to 9d had good thickness uniformity.

このようにして、非常に薄(均一な膜厚のSi活性層を
もつ超薄膜SOI基板が作製できた。
In this way, an ultra-thin SOI substrate having a very thin (uniform thickness) Si active layer was fabricated.

なお、極薄31層9a乃至9dの厚さは、溝間の距離の
小さいSi層の幅と本数、溝の幅とその本数によって変
えることができる。溝間の距離の大きいSi層の幅を一
定にし、溝の幅、溝の本数、溝間の距離の小さいSi層
の数を増やすと、残存する極薄31層9a乃至9dの厚
さは大きくなる。
Note that the thickness of the ultra-thin 31 layers 9a to 9d can be changed depending on the width and number of Si layers with small distances between grooves, and the width and number of grooves. If the width of the Si layer with a large distance between grooves is kept constant and the width of the grooves, the number of grooves, and the number of Si layers with a small distance between grooves are increased, the thickness of the remaining ultra-thin 31 layers 9a to 9d will increase. Become.

〔発明の効果〕〔Effect of the invention〕

以上説明したように1本発明によれば、張り合わせSO
I基板を形成した後に幅や間隔を変えた溝を複数本Si
O□層が露出する深さまで形成して研磨するのみで、均
一な厚さのSi活性層をもつ超薄膜SOI基板を作製す
ることができる。
As explained above, according to the present invention, the lamination SO
After forming the I-substrate, multiple grooves with different widths and intervals are formed on the Si.
By simply forming and polishing the O□ layer to a depth where it is exposed, an ultra-thin SOI substrate having a Si active layer of uniform thickness can be produced.

本発明は張り合わせSOI基板を用いるデバイスの性能
向上と歩留り向上に寄与するところが大きい。
The present invention greatly contributes to improving the performance and yield of devices using bonded SOI substrates.

【図面の簡単な説明】[Brief explanation of drawings]

第1図<a)乃至(d)は実施例の製造工程を説明する
ための断面図。 第2図(a)乃至(e)は従来例の製造工程を説明する
ための断面図。 第3図(a)乃至(c)は張り合わせSOr基板の製造
工程を説明するための断面図 である。 図において。 la、 2aはSi基板。 lb、 2bはSiO□膜。 3は支持基板 4はSiO□層。 5は素子基板。 5aは薄いSi層 6.6a乃至6には溝。 7a乃至7dは溝間の距離の大きいSi層。 8a乃至8hは溝間の距離の小さいSi層。 9a乃至9dは極薄Si層 10はSiO□膜 (d) 実施例c′)製遠工手! 第 1 図 (e) 従来例の製苺工J呈 第 2 図
FIGS. 1A to 1D are cross-sectional views for explaining the manufacturing process of the embodiment. FIGS. 2(a) to 2(e) are cross-sectional views for explaining the manufacturing process of a conventional example. FIGS. 3(a) to 3(c) are cross-sectional views for explaining the manufacturing process of the bonded SOr substrate. In fig. la and 2a are Si substrates. lb and 2b are SiO□ films. 3, the support substrate 4 is a SiO□ layer. 5 is an element substrate. 5a is a thin Si layer 6. 6a to 6 are grooves. 7a to 7d are Si layers with large distances between grooves. 8a to 8h are Si layers with small distances between grooves. 9a to 9d, the ultra-thin Si layer 10 is a SiO□ film (d) Example c') Fig. 1 (e) Conventional strawberry making process Fig. 2

Claims (1)

【特許請求の範囲】  SiO_2層(4)と、該SiO_2層(4)の上下
のSi層からなる張り合わせSOI基板の片面を研削し
て、薄いSi層(5a)を形成する工程と, 該薄いSi層(5a)にSiO_2層(4)を露出する
複数の溝(6a乃至6k)を形成し、溝間の距離の大き
いSi層(7a乃至7d)と溝間の距離の小さいSi層
(8a乃至8h)を形成する工程と, SiO_2に対してSiを選択的に研磨する研磨剤を用
いて全面を研磨する工程とを有し、 前記溝間の距離の小さいSi層(8a乃至8h)を研磨
除去して、SiO_2層を露出するとともに、前記溝間
の距離の大きいSi層(7a乃至7d)を残して極薄S
i層(9a乃至9d)を形成することを特徴とするSO
I基板の製造方法。
[Claims] A step of forming a thin Si layer (5a) by grinding one side of a bonded SOI substrate consisting of a SiO_2 layer (4) and Si layers above and below the SiO_2 layer (4); A plurality of grooves (6a to 6k) exposing the SiO_2 layer (4) are formed in the Si layer (5a), and the Si layer (7a to 7d) with a large distance between grooves and the Si layer (8a) with a small distance between grooves are formed. and a step of polishing the entire surface using an abrasive that selectively polishes Si with respect to SiO_2. The SiO_2 layer is exposed by polishing and removed, and the Si layer (7a to 7d) with a large distance between the grooves is left and an ultra-thin S
SO characterized by forming an i-layer (9a to 9d)
Method for manufacturing an I-board.
JP5890090A 1990-03-09 1990-03-09 Manufacture of soi substrate Pending JPH03259521A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5890090A JPH03259521A (en) 1990-03-09 1990-03-09 Manufacture of soi substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5890090A JPH03259521A (en) 1990-03-09 1990-03-09 Manufacture of soi substrate

Publications (1)

Publication Number Publication Date
JPH03259521A true JPH03259521A (en) 1991-11-19

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP5890090A Pending JPH03259521A (en) 1990-03-09 1990-03-09 Manufacture of soi substrate

Country Status (1)

Country Link
JP (1) JPH03259521A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05160088A (en) * 1991-12-05 1993-06-25 Fujitsu Ltd Semiconductor substrate manufacturing method and device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05160088A (en) * 1991-12-05 1993-06-25 Fujitsu Ltd Semiconductor substrate manufacturing method and device
US5399233A (en) * 1991-12-05 1995-03-21 Fujitsu Limited Method of and apparatus for manufacturing a semiconductor substrate

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