JPH03257941A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03257941A JPH03257941A JP5719490A JP5719490A JPH03257941A JP H03257941 A JPH03257941 A JP H03257941A JP 5719490 A JP5719490 A JP 5719490A JP 5719490 A JP5719490 A JP 5719490A JP H03257941 A JPH03257941 A JP H03257941A
- Authority
- JP
- Japan
- Prior art keywords
- pads
- semiconductor device
- protruding electrodes
- internal circuit
- static electricity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims 1
- 230000005611 electricity Effects 0.000 abstract description 6
- 230000003068 static effect Effects 0.000 abstract description 6
- 238000002845 discoloration Methods 0.000 abstract description 5
- 238000011109 contamination Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000010186 staining Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、フィルムキャリア、ＣＯＧ （チップ・オン
・グラス〉等によって実装される半導体装置に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device mounted by a film carrier, COG (chip on glass), or the like.
従来の技術
半導体装置を高密度実装する技術としては、フィルムキ
ャリア、ＣＯＧ （チップ・オン・グラス〉等の技術が
ある。フィルムキャリアによる方法は、半導体装置表面
に形威されたパッド上に金等の導電性の物質で突起電極
を形威し、半導体装置上のパッドの配置に対応して作ら
れた＃４箔製のインナーリード群とを一部ボンディング
し、さらに、これらのリード群の他端をプリント基板等
の電極にボンディングする技術である。また、ＣＯＧに
よる方法は、上と同様に形成された突起電極を、パッド
の配置に対応して作られた、プリント基板上の電極に直
接ボンディングする技術である。Conventional technology Technologies for high-density packaging of semiconductor devices include film carrier and COG (chip-on-glass) technologies.The method using film carriers uses gold, etc., on pads formed on the surface of semiconductor devices. A protruding electrode is formed using a conductive material, and a part of the inner lead group made of #4 foil is bonded to the inner lead group made in accordance with the arrangement of the pads on the semiconductor device. This is a technology in which the ends are bonded to electrodes on a printed circuit board, etc.Also, in the COG method, a protruding electrode formed in the same manner as above is directly bonded to an electrode on a printed circuit board made in accordance with the arrangement of pads. This is a bonding technology.
このような実装をするための半導体装置のパッド近傍に
は、第２図に示すように、Ａｅ等の配線金属４の一部で
形成されたパッドと、その中心付近以外を覆う表面保護
膜５とが設けられており、その表面保護膜５の開口部を
覆うように、バリアメタル層６が設けられ、その上に表
面保護膜５の開口部を完全に覆うように金等で１０〜２
０μｍの高さの突起電極７が形成されている。配線金属
４、表面保護膜５．バリアメタル層６は、すべて１μｍ
程度の高さであるため、突起電極７が不規則に並んでい
る場合には、ボンディング時に突起電極７にかかる圧力
に差が生じ、突起電極７とインナーリード８の接続の弱
い筺所が生じる。このため、従来より第３図に示すよう
に、パッドの配置が不規則になる場合は、内部回路３と
接続されないダミーのパッド２を形成し、このダミーの
パッド２の上にも突起電極を形威し、パッドが均等に配
置されるようにしている。Near the pads of the semiconductor device for such mounting, as shown in FIG. A barrier metal layer 6 is provided so as to cover the opening of the surface protective film 5, and a layer of gold or the like is deposited on the barrier metal layer 6 to completely cover the opening of the surface protective film 5.
A protruding electrode 7 having a height of 0 μm is formed. Wiring metal 4, surface protection film 5. Barrier metal layer 6 is all 1 μm
If the protruding electrodes 7 are arranged irregularly, there will be a difference in the pressure applied to the protruding electrodes 7 during bonding, resulting in weak connections between the protruding electrodes 7 and the inner leads 8. . For this reason, as shown in FIG. 3, conventionally, when the pad arrangement is irregular, a dummy pad 2 that is not connected to the internal circuit 3 is formed, and a protruding electrode is also placed on this dummy pad 2. The shape is strong and the pads are evenly distributed.
発明が解決しようとする課題
以上のような従来の半導体装置では、内部回路３に接続
されていない突起電極が電気的に浮いており、製造工程
で、静電気等により帯電し、ダスト等が付着し、パッド
の汚れや変色等を引き起こしやすくなる。Problems to be Solved by the Invention In the conventional semiconductor device as described above, the protruding electrodes that are not connected to the internal circuit 3 are electrically floating, and during the manufacturing process, they become charged due to static electricity, etc., and dust etc. adhere to them. , the pad becomes more likely to become dirty or discolored.
本発明は、上記問題点を解決する半導体装置を提供する
ものである。The present invention provides a semiconductor device that solves the above problems.
課題を解決するための手段
この目的を達成するために本発明では、内部回路と接続
していない金属突起電極の電位を固定することを特徴と
している。Means for Solving the Problems In order to achieve this object, the present invention is characterized in that the potential of the metal protrusion electrodes that are not connected to the internal circuit is fixed.
作用
このようにすれば、内部回路と接続していない金属突起
電極は、電気的に浮いた状態ではなくなり、製造工程で
静電気により帯電することがなくなり、汚染・変色等の
問題が解決できる。By doing this, the metal projecting electrodes that are not connected to the internal circuit will no longer be in an electrically floating state and will not be charged with static electricity during the manufacturing process, thus solving problems such as contamination and discoloration.
実施例
内部回路と接続していない突起電極を接地電位に固定し
た場合の本発明の一実施例について第１図とともに説明
する。Embodiment An embodiment of the present invention in which a protruding electrode not connected to an internal circuit is fixed to a ground potential will be described with reference to FIG.
第１図に示す半導体装置においても内部回路３と接続さ
れるパッド１の並びの中にパッドを均等に配置するため
に設けられた内部回路３と接続していないパッド（ダミ
ーパッド〉２がある。本実施例ではこのダミーパッド２
をＡｅ配線でＰウェルに接続することにより、ダミーパ
ッド２上の突起電極を接地電位に固定する構造とする。In the semiconductor device shown in FIG. 1, there are pads (dummy pads) 2 that are not connected to the internal circuit 3 and are provided to evenly arrange the pads in the row of pads 1 that are connected to the internal circuit 3. .In this embodiment, this dummy pad 2
By connecting the dummy pad 2 to the P well with an Ae wiring, the protruding electrode on the dummy pad 2 is fixed to the ground potential.
この結果、この構造の半導体装置では、静電気等により
、突起電極が帯電せず、汚れ、変色等の問題を解決する
ことができる。As a result, in the semiconductor device having this structure, the protruding electrodes are not charged due to static electricity or the like, and problems such as staining and discoloration can be solved.
なお、本実施例では、突起電極を接地電位に固定したが
、接地電位以外のどの電位に固定したとしても、同様の
効果が期待できる。In this embodiment, the protruding electrode is fixed to the ground potential, but the same effect can be expected even if the protruding electrode is fixed to any potential other than the ground potential.
発明の効果
本発明は、半導体装置の内部回路と接続していない浮遊
電位の突起電極に対して電位を固定することにより、静
電気等による帯電を防ぎ、突起電極の汚染、変色等を防
ぐことができる半導体装置を実現できるものである。Effects of the Invention The present invention prevents charging due to static electricity and the like by fixing the potential of a protruding electrode with a floating potential that is not connected to the internal circuit of a semiconductor device, thereby preventing contamination, discoloration, etc. of the protruding electrode. It is possible to realize a semiconductor device that can
第１図は本発明の一実施例における半導体装置の平面図
、第２図は突起電極を有するパッド部分の構造とインナ
ーリードとの関係を示す断面図、第３図は従来の電位を
固定しないパッドを有する半導体装置の平面図である。
１・・・・・・内部回路と接続されたパッド、２・・・
・・・内部回路と接続していないダミーパッド、３・・
・・・・内部回路、４・・・・・・配線金属層、５・・
・・・・表面保護膜、６・・・・・・バリアメタル層、
７・・・・・・突起電極、８・・・・・・インナーリー
ド。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the structure of a pad portion having a protruding electrode and the relationship between the inner lead, and FIG. 3 is a conventional method in which the potential is not fixed. FIG. 2 is a plan view of a semiconductor device having pads. 1... Pad connected to internal circuit, 2...
...Dummy pad not connected to the internal circuit, 3...
...Internal circuit, 4...Wiring metal layer, 5...
...Surface protective film, 6...Barrier metal layer,
7...Protruding electrode, 8...Inner lead.
Claims (1)
極をもち、かつ上記金属突起電極を定電位に固定したこ
とを特徴とする半導体装置。1. A semiconductor device comprising a metal protrusion electrode not connected to an internal circuit on a semiconductor substrate, the metal protrusion electrode being fixed at a constant potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5719490A JPH03257941A (en) | 1990-03-08 | 1990-03-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5719490A JPH03257941A (en) | 1990-03-08 | 1990-03-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03257941A true JPH03257941A (en) | 1991-11-18 |
Family
ID=13048678
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5719490A Pending JPH03257941A (en) | 1990-03-08 | 1990-03-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03257941A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006269592A (en) * | 2005-03-23 | 2006-10-05 | Fuji Photo Film Co Ltd | Solid-state image sensor and manufacturing method thereof |
-
1990
- 1990-03-08 JP JP5719490A patent/JPH03257941A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006269592A (en) * | 2005-03-23 | 2006-10-05 | Fuji Photo Film Co Ltd | Solid-state image sensor and manufacturing method thereof |
| JP4677260B2 (en) * | 2005-03-23 | 2011-04-27 | 富士フイルム株式会社 | Manufacturing method of solid-state imaging device |
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