JPH0325751B2 - - Google Patents

Info

Publication number
JPH0325751B2
JPH0325751B2 JP56173510A JP17351081A JPH0325751B2 JP H0325751 B2 JPH0325751 B2 JP H0325751B2 JP 56173510 A JP56173510 A JP 56173510A JP 17351081 A JP17351081 A JP 17351081A JP H0325751 B2 JPH0325751 B2 JP H0325751B2
Authority
JP
Japan
Prior art keywords
voltage
circuit
battery
counter
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56173510A
Other languages
Japanese (ja)
Other versions
JPS5873879A (en
Inventor
Yoshikazu Kageyama
Sakon Nagasaki
Mineo Mino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56173510A priority Critical patent/JPS5873879A/en
Priority to US06/436,351 priority patent/US4521735A/en
Priority to KR8204831A priority patent/KR860002001B1/en
Publication of JPS5873879A publication Critical patent/JPS5873879A/en
Publication of JPH0325751B2 publication Critical patent/JPH0325751B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G01R19/16538—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies
    • G01R19/16542—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies for batteries
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/3644—Constructional arrangements
    • G01R31/3646—Constructional arrangements for indicating electrical conditions or variables, e.g. visual or audible indicators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/3644—Constructional arrangements
    • G01R31/3648—Constructional arrangements comprising digital calculation means, e.g. for performing an algorithm

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は、バツテリを使用する装置において、
バツテリの残量電圧の検出と装置が動作可能な最
低電圧（以後UNDER CUT電圧VUCUTと呼ぶ）
との検出を同一回路によつて行ない、バラツキの
ない高品質なバツテリ残量検出を提供するもので
ある。 本発明の具体的一例をポータブルVTRを用い
て説明する。 従来のポータブルVTRにおいてのバツテリ残
量検出方式は、針式メータ方式と、バツテリ電圧
をいくつかの基準電圧を変えた比較器に入力して
検出する方式とがある。まず第一の針式メータ方
式においては、UNDER CUT電圧を検出する回
路とは別にバツテリ残量検出回路が必要であり、
使用する部品のバラツキを考慮すると、針式メー
タの調整と、UNDER CUT電圧検出の調整との
２種類の調整が必要となり、高価なものとなつて
いる。第２のそれぞれ基準電圧を変えた比較器を
使用する方式は、バツテリ残量電圧を比較する基
準電圧の数の比較器が必要であり、使用する各部
品のバラツキを考慮すると各比較器全てに基準電
圧の調整が必要となる。あるいは、UNDER
CUT電圧を検出する比較器のみ調整にすると、
バツテリ残量電圧の表示にバラツキが出てくる。
このように従来の方式は、高価で調整の多い方式
である。 本発明はこれらの欠点を除去するものである。 以下に本発明の実施例について図面とともに詳
細に亘つて説明する。尚、説明を簡略化するため
ここではバツテリ残量の分解能を２ビツト（bit）
で行なつたバツテリ残量検出の方式を１例として
挙げて説明する。 図はバツテリ残量の分解能を２ビツトで行なつ
たバツテリ残量検出方式の一例である。基準電圧
発生回路２は、バツテリ１から出力されるバツテ
リ電圧VBATTからUNDER CUT電圧VUCUTより低
い一定の基準電圧Vrefを発生するもので、例えば
図のように抵抗Ｒ１と順方向電圧がUNDER
CUT電圧より低いツエナーダイオードＤ１で構
成される。これにより装置が動作可能な状態にお
いては、基準電圧Vrefは一定のものとなる。カウ
ンタ６は、基準クロツク発生回路５より出力され
る基準クロツクを、制御回路１０からのUP指令
あるいはDOWN指令によつてカウントUPあるい
はカウントDOWNし、本実施例においては第１
表に示すように値が０のビツトはhighレベルの電
圧を出力し、値が１のビツトはlowレベルの電圧
を出力するものである。 なお、カウンタ６の上位ビツトはトランジスタ
Tr1，Tr2のベースに接続され、下位ビツトはト
ランジスタTr3，Tr4のベースに接続されている。 The present invention provides a device that uses a battery.
Detection of remaining battery voltage and minimum voltage at which the device can operate (hereinafter referred to as UNDER CUT voltage V UCUT )
Detection is performed by the same circuit, and high-quality battery remaining amount detection without variation is provided. A specific example of the present invention will be explained using a portable VTR. Conventional methods for detecting remaining battery power in portable VTRs include a needle meter method and a method in which battery voltage is detected by inputting it into a comparator with several different reference voltages. First of all, in the first needle-type meter method, a remaining battery level detection circuit is required in addition to the circuit that detects the UNDER CUT voltage.
Considering the variations in the parts used, two types of adjustment are required: adjustment of the needle-type meter and adjustment of the UNDER CUT voltage detection, which is expensive. The second method of using comparators with different reference voltages requires as many comparators as the number of reference voltages used to compare the remaining battery voltage. Adjustment of reference voltage is required. Or UNDER
If you adjust only the comparator that detects the CUT voltage,
There are variations in the battery remaining voltage display.
As described above, the conventional method is expensive and requires many adjustments. The present invention obviates these drawbacks. Embodiments of the present invention will be described in detail below with reference to the drawings. In order to simplify the explanation, the resolution of the remaining battery level is set to 2 bits (bit).
The method of detecting the remaining battery amount performed in the above will be explained as an example. The figure shows an example of a method for detecting the remaining battery amount in which the resolution of the remaining battery amount is 2 bits. The reference voltage generation circuit 2 generates a constant reference voltage V ref lower than the UNDER CUT voltage V UCUT from the battery voltage V BATT output from the battery 1. For example, as shown in the figure, the resistor R1 and the forward voltage are
It consists of a Zener diode D1 that is lower than the CUT voltage. As a result, the reference voltage V ref remains constant while the device is in an operable state. The counter 6 counts up or down the reference clock output from the reference clock generation circuit 5 in response to an UP command or a DOWN command from the control circuit 10.
As shown in the table, a bit with a value of 0 outputs a high level voltage, and a bit with a value of 1 outputs a low level voltage. Note that the upper bit of counter 6 is a transistor.
It is connected to the bases of transistors Tr 1 and Tr 2 , and its lower bit is connected to the bases of transistors Tr 3 and Tr 4 .

【表】 電圧変換回路４は、カウンタ６のカウント出力
をOVあるいは基準電圧Vrefに変換するもので、
例えば図のように四個のトランジスタTr1，Tr2，
Tr3，Tr4より構成されている。 Ｄ−Ａ変換回路７は、前記電圧変換回路４の出
力値をＤ−Ａ変換して電圧V2を発生するもので、
例えば図に示すように抵抗R3、R4、R5、R6を
はしご状に接続したものである。ただしこれらの
抵抗は、R3＝R5＝R6＝２×R4の抵抗値を有す
る。電圧発生回路８は、バツテリ電圧VBATTの変
化に応じた電圧V1を発生するもので、調整が可
能となる構成で、例えば図のように可変抵抗VR
１を用いた構成である。比較回路９は、電圧V1
と電圧V2の値を比較してその結果を出力するも
ので、図においては、電圧V1が電圧V2より大き
ければ、highの電圧、電圧V1が電圧V2より小さ
ければlowの電圧を出力するようになつている。
これと逆の電圧を出力する構成でもよい。制御回
路１０は、遅延回路３の出力電圧が制御回路１０
の中で設定するバツテリ残量検出開始電圧より大
きくなつたら、バツテリ残量検出を開始する。制
御回路１０は、バツテリ残量検出開始状態となつ
たら、カウンタ６をプリセツトし、比較回路９の
出力電圧を読み取り、その値からカウンタ６に
UP指令あるいはDOWN指令を送る。図の構成に
おいては、比較回路９の出力がhigh電圧ならUP
指令、low電圧ならDOWN指令を送るようにな
つている。すると、第１表に示すように制御回路
１０よりDOWN指令が出ている場合は電圧V2の
値は低くなり、UP指令が出ている場合は電圧V2
の値は高くなる。そして、比較回路９の出力電圧
が反転したら、バツテリ残量メモリ指令をメモリ
１１に送り、再びカウンタ６をプリセツトしバツ
テリ残量検出を行なつている。メモリ１１は、制
御回路１０よりバツテリ残量メモリ指令が送られ
てきたら、その時のカウンタ６の内容をメモリす
る。表示回路１２は、メモリ１１の内容を表示器
１５に表示する回路である。本実施例では分解能
を２ビツトで行なつている為、例えば４つのバー
表示を使うことでバツテリの残量電圧を４段階で
表示することができる。すなわち、電圧V2は４
段階の電圧を持ち、電圧V1がその４段階の電圧
のどのレベルにあるかを、比較回路９の出力電圧
の反転によつて検出し、その時のカウンタ６の値
をバー表示することでバツテリの残量電圧を４段
階表示できる。UNDER CUT指令回路１３は、
メモリ１１の内容がバツテリ電圧VBATTが
UNDER CUT電圧VUCUTより小さい値になつた
時に対応する値になつたらメカニズム・コントロ
ール回路１４に装置が動作するのを禁止する出力
を送つている。なお、遅延回路３を入れている理
由は、電源SW１がOFFからONになつた時、バ
ツテリ電圧VBATTに立上り時間があるため、バツ
テリ電圧VBATTがUNDER CUT電圧VUCUTになる
までにバツテリ残量検出を行なつてしまい、バツ
テリ電圧VBATTがUNDER CUT電圧VUCUTより低
いと誤判定してしまうのを禁止するためである。
だから、遅延回路３の回路素子Ｒ２，Ｃ１の値
は、電源SW１がOFFからONになつてから遅延
回路３の出力電圧が制御回路１０で設定されるバ
ツテリ残量検出開始電圧より大きくなるまでの時
間は、バツテリ電圧VBATTがUNDER CUT電圧
VUCUTまで立上がるまでの時間以上となるよう設
定する。 次にこのバツテリ残量検出方式におけるバツテ
リ残量値のバラツキを計算する。なお、図におい
ては、バツテリ残量検出の分解能は２ビツトとな
つているが、これをｎビツトの分解能にした検出
方式において計算を行なう。 本発明においては、バツテリ電圧VBATTが
UNDER CUT電圧VUCUTになつた時を基準にし
て行なう。よつて、バツテリ電圧VBATTがちよう
どUNDER CUT電圧VUCUTになつた事を検知す
る時のカウンタ６の値を10進数でＡとするとカウ
ンタ６が10進数でＡの時、V1とV2が同じ値とな
るよう電圧発生回路８の回路素子VR１を調整す
る。この時、回路素子Ｄ１のバラツキによる基準
電圧Vrefのバラツキをｒ％、Ｄ−Ａ変換回路４の
抵抗Ｒ３，Ｒ４，Ｒ５，Ｒ６のバラツキによる変
換電圧のバラツキをｑ％とするとUNDER CUT
電圧検知時のV2の値V2′は V2′＝Vref（１＋ｒ／100）Ａ／2n（１＋ｑ／100） …(1) 電圧発生回路８により、V1の値はバツテリ電
圧VBATTのｇ％となるとすると、UNDER CUT
電圧時のV1の値V1′は V1′＝VUCUT×ｇ／100 …(2) V2′の値とV1′の値は同じ値となるように電圧発
生回路８の回路素子VR１を調整しているため V1′＝V2′ …(3) (1)、(2)、(3)式より ｇ＝100／VUCUTVref（１＋ｒ／100）Ａ／2n（１＋ｑ
／ 100） …(4) ｇは(4)式で示した値となるよう調整される。 このように電圧発生回路８の回路素子VR１を
調整し、前述した方式によりバツテリ残量検出を
行なう。メモリ１１の内容が10進数でＡ＋ｍ（ｍ
＝０、１、２……）になつた時のバツテリ残量電
圧VBATTを計算する。この時次式が成立する。 VBATT×ｇ／100＝Vref（１＋ｒ／100）Ａ＋ｍ／2n（１
＋ｑ／100）…(5) (5)式に(4)式を代入すると VBATT＝VUCUT×Ａ＋ｍ／Ａ …(6) (6)式を見るとわかるように、検出されるバツテ
リ残量電圧はバラツキのない一定の値となる。 このように本発明のバツテリ残量検出方式を用
いれば、バツテリ残量検出とUNDER CUT電圧
検出を同一回路で行なうことができ、UNDER
CUT電圧検出のための調整を行なえば、バツテ
リ残量検出のための調整をせずにバラツキのない
バツテリ残量検出ができ、バツテリ残量検出の分
解能を高くすれば、非常に高品質のバツテリ残量
検出を行なうことができる。また、遅延回路３、
基準クロツク発生回路５、カウンタ６、制御回路
１０、メモリ１１をマイクロコンピユータを使用
して行なえばより簡易なバツテリ残量検出方式と
なる。[Table] The voltage conversion circuit 4 converts the count output of the counter 6 to OV or reference voltage V ref .
For example, as shown in the figure, four transistors T r1 , T r2 ,
It consists of T r3 and T r4 . The D-A converter circuit 7 converts the output value of the voltage converter circuit 4 into a D-A converter to generate a voltage V2 .
For example, as shown in the figure, resistors R3, R4, R5, and R6 are connected in a ladder shape. However, these resistors have a resistance value of R3=R5=R6=2×R4. The voltage generation circuit 8 generates a voltage V 1 according to changes in the battery voltage V BATT , and has a configuration that allows adjustment, for example by using a variable resistor VR as shown in the figure.
This is a configuration using 1. The comparator circuit 9 has a voltage V 1
It compares the value of voltage V 2 with voltage V 2 and outputs the result. In the figure, if voltage V 1 is larger than voltage V 2 , it is a high voltage, and if voltage V 1 is smaller than voltage V 2 , it is a low voltage. is now output.
A configuration that outputs a voltage opposite to this may also be used. The control circuit 10 is configured such that the output voltage of the delay circuit 3 is
When the battery level becomes larger than the battery level detection start voltage set in , battery level detection starts. When the control circuit 10 enters the state to start detecting the remaining battery amount, it presets the counter 6, reads the output voltage of the comparator circuit 9, and inputs the output voltage from that value into the counter 6.
Send UP or DOWN command. In the configuration shown in the figure, if the output of comparator circuit 9 is high voltage, UP
If the command is low voltage, it will send a DOWN command. Then, as shown in Table 1, when the DOWN command is issued from the control circuit 10, the value of the voltage V 2 becomes low, and when the UP command is issued, the voltage V 2 becomes low.
becomes higher. When the output voltage of the comparison circuit 9 is inverted, a remaining battery amount memory command is sent to the memory 11, the counter 6 is preset again, and the remaining battery amount is detected. When a battery remaining amount memory command is sent from the control circuit 10, the memory 11 stores the contents of the counter 6 at that time. The display circuit 12 is a circuit that displays the contents of the memory 11 on the display 15. In this embodiment, since the resolution is 2 bits, the remaining battery voltage can be displayed in four stages by using, for example, a four bar display. That is, the voltage V 2 is 4
The battery voltage is determined by detecting which level of the four voltage levels the voltage V1 is at by inverting the output voltage of the comparator circuit 9, and displaying the value of the counter 6 at that time as a bar. The remaining voltage can be displayed in 4 levels. The UNDER CUT command circuit 13 is
The contents of memory 11 are battery voltage V BATT
When the UNDER CUT voltage reaches a value smaller than VUCUT , an output is sent to the mechanism control circuit 14 to prohibit the device from operating. The reason why the delay circuit 3 is included is that when the power supply SW1 is turned on from OFF, there is a rise time for the battery voltage V BATT , so there is no remaining battery power until the battery voltage V BATT reaches the UNDER CUT voltage V This is to prevent erroneous determination that battery voltage V BATT is lower than UNDER CUT voltage V UCUT due to amount detection.
Therefore, the values of circuit elements R2 and C1 of the delay circuit 3 are determined from the time when the power supply SW1 is turned on from OFF to the time when the output voltage of the delay circuit 3 becomes larger than the battery remaining amount detection start voltage set by the control circuit 10. The time is when the battery voltage V BATT is the UNDER CUT voltage
Set it so that it is longer than the time it takes to rise to V UCUT . Next, the variation in the remaining battery amount value in this battery remaining amount detection method is calculated. Note that in the figure, the resolution for detecting the remaining battery amount is 2 bits, but calculations are performed using a detection method with a resolution of n bits. In the present invention, the battery voltage V BATT is
Perform this based on the time when the UNDER CUT voltage reaches V UCUT . Therefore, if the value of counter 6 when detecting that the battery voltage V BATT has reached UNDER CUT voltage V UCUT is A in decimal notation, then when counter 6 is A in decimal notation, V 1 and V 2 The circuit element VR1 of the voltage generating circuit 8 is adjusted so that the values are the same. At this time, if the variation in the reference voltage V ref due to the variation in the circuit element D1 is r%, and the variation in the converted voltage due to the variation in the resistors R3, R4, R5, and R6 of the DA conversion circuit 4 is q%, UNDER CUT
The value of V 2 at the time of voltage detection, V 2 ', is V 2 '=V ref (1+r/100) A/2 n (1+q/100)...(1) The voltage generation circuit 8 determines the value of V 1 as the battery voltage V. If it is g% of BATT , then UNDER CUT
The value of V 1 at voltage V 1 ′ is V 1 ′ = V UCUT × g/100 (2) The circuit elements of the voltage generation circuit 8 are adjusted so that the value of V 2 ′ and the value of V 1 ′ are the same value. Since VR1 is adjusted, V 1 ′=V 2 ′ …(3) From equations (1), (2), and (3), g=100/V UCUT V ref (1+r/100)A/2 n (1+q
/ 100) ...(4) g is adjusted to the value shown in equation (4). The circuit element VR1 of the voltage generating circuit 8 is adjusted in this manner, and the remaining battery amount is detected by the method described above. The contents of memory 11 are A+m (m
= 0, 1, 2...) Calculate the remaining battery voltage V BATT . This temporal formula holds true. V BATT ×g/100=V ref (1+r/100)A+m/2 n (1
+q/100)...(5) Substituting equation (4) into equation (5), V BATT = V UCUT ×A+m/A...(6) As you can see from equation (6), the detected battery remaining amount The voltage becomes a constant value without variation. In this way, by using the battery remaining amount detection method of the present invention, battery remaining amount detection and UNDER CUT voltage detection can be performed in the same circuit.
By making adjustments to detect the CUT voltage, it is possible to detect the remaining battery level without any variation without making any adjustments to detect the remaining battery level, and by increasing the resolution of the remaining battery level detection, it is possible to detect very high quality batteries. The remaining amount can be detected. In addition, the delay circuit 3,
If a microcomputer is used for the reference clock generation circuit 5, counter 6, control circuit 10, and memory 11, a simpler battery remaining amount detection method can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は、本発明の一実施例の構成を示すブロツ
ク図である。 １……バツテリ、２……基準電圧発生回路、３
……遅延回路、４……電圧変換回路、５……基準
クロツク発生回路、６……カウンタ、７……Ｄ−
Ａ変換回路、８……電圧発生回路、９……比較回
路、１０……制御回路、１１……メモリ、１２…
…表示回路、１３……UNDER CUT指令回路、
１４……メカニズム・コントロール回路、１５…
…表示器。 The drawing is a block diagram showing the configuration of an embodiment of the present invention. 1...Battery, 2...Reference voltage generation circuit, 3
...Delay circuit, 4...Voltage conversion circuit, 5...Reference clock generation circuit, 6...Counter, 7...D-
A conversion circuit, 8... Voltage generation circuit, 9... Comparison circuit, 10... Control circuit, 11... Memory, 12...
...Display circuit, 13...UNDER CUT command circuit,
14... Mechanism control circuit, 15...
…display.

Claims (1)

【特許請求の範囲】 １ 装置が動作可能な最低電圧より低い一定の基
準電圧を作る基準電圧発生回路と、バツテリ電圧
の変化に応じた電圧を発生する電圧発生回路と、
基準クロツクを発生する基準クロツク発生回路
と、その基準クロツクに同期して制御信号に応じ
て、UPあるいはDOWNするカウンタと、前記カ
ウンタのカウンタ値をOVあるいは基準電圧に変
換する電圧変換回路と、前記電圧変換回路から出
力されるデジタル量をアナログ量に変換するＤ−
Ａ変換回路と、前記電圧発生回路の出力電圧と前
記Ｄ−Ａ変換回路の出力電圧とを比較する比較回
路と、前記カウンタをUPあるいはDOWNする制
御信号を出力し、前記比較回路の出力が変化した
らバツテリ残量メモリ指令を発生した後カウンタ
をプリセツトする制御回路と、前記制御回路から
バツテリ残量メモリ指令が出力されたら、その時
の前記カウンタの値をメモリするメモリ回路と、
前記メモリ回路の値をバツテリ残量表示器に表示
する表示回路とを具備することを特徴としたバツ
テリの残量電圧検出装置。 ２ 基準電圧発生回路の出力電圧を遅延させて前
記制御回路の動作開始を遅らせる遅延回路を具備
することを特徴とする特許請求の範囲第１項に記
載のバツテリの残量電圧検出装置。 ３ 電圧発生回路の設定電圧を調整可能に構成
し、Ｄ−Ａ変換回路の回路素子のバラツキによる
変換電圧のバラツキと基準電圧発生回路の回路素
子のバラツキによる基準電圧のバラツキとによる
残量電圧検出のバラツキを、前記電圧発生回路の
設定電圧を調整することによつて補正することを
特徴とする特許請求の範囲第１項に記載のバツテ
リの残量電圧検出装置。[Scope of Claims] 1. A reference voltage generation circuit that generates a constant reference voltage lower than the lowest voltage at which the device can operate, and a voltage generation circuit that generates a voltage according to changes in battery voltage.
a reference clock generation circuit that generates a reference clock; a counter that goes up or down in response to a control signal in synchronization with the reference clock; a voltage conversion circuit that converts the counter value of the counter into an OV or reference voltage; D- converts the digital amount output from the voltage conversion circuit into an analog amount
an A conversion circuit, a comparison circuit that compares the output voltage of the voltage generation circuit and the output voltage of the D-A conversion circuit, and outputs a control signal for UP or DOWN the counter, so that the output of the comparison circuit changes. a control circuit that presets a counter after generating a battery remaining amount memory command when the remaining battery amount memory command is outputted from the control circuit; and a memory circuit that stores the value of the counter at that time when the remaining battery amount memory command is output from the control circuit.
A battery remaining voltage detection device comprising: a display circuit that displays the value of the memory circuit on a battery remaining amount display. 2. The battery remaining voltage detection device according to claim 1, further comprising a delay circuit that delays the output voltage of the reference voltage generation circuit to delay the start of operation of the control circuit. 3 The set voltage of the voltage generation circuit is configured to be adjustable, and residual voltage detection is performed based on variations in the converted voltage due to variations in the circuit elements of the DA conversion circuit and variations in the reference voltage due to variations in the circuit elements of the reference voltage generation circuit. 2. The battery residual voltage detecting device according to claim 1, wherein the variation in voltage is corrected by adjusting the set voltage of the voltage generating circuit.
JP56173510A 1981-10-28 1981-10-28 Detecting device for residual voltage of battery Granted JPS5873879A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP56173510A JPS5873879A (en) 1981-10-28 1981-10-28 Detecting device for residual voltage of battery
US06/436,351 US4521735A (en) 1981-10-28 1982-10-25 Battery voltage level detecting apparatus
KR8204831A KR860002001B1 (en) 1981-10-28 1982-10-27 Detecting device for resi dual voltage of battery

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56173510A JPS5873879A (en) 1981-10-28 1981-10-28 Detecting device for residual voltage of battery

Publications (2)

Publication Number Publication Date
JPS5873879A JPS5873879A (en) 1983-05-04
JPH0325751B2 true JPH0325751B2 (en) 1991-04-08

Family

ID=15961860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56173510A Granted JPS5873879A (en) 1981-10-28 1981-10-28 Detecting device for residual voltage of battery

Country Status (1)

Country Link
JP (1) JPS5873879A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5411088B2 (en) * 1972-12-11 1979-05-11

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5651204Y2 (en) * 1976-08-24 1981-11-30
JPS5726481Y2 (en) * 1977-06-24 1982-06-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5411088B2 (en) * 1972-12-11 1979-05-11

Also Published As

Publication number Publication date
JPS5873879A (en) 1983-05-04

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