JPH03254510A - Automatic gain controller - Google Patents

Abstract

PURPOSE:To attain automatic gain control even to a signal not subjected to waveform equalization by providing a control signal generating circuit comparing the level of an output signal of a square mean circuit with the level of a reference signal whose level is set in advance respectively, generating a control signal and applying the signal to a variable attenuator. CONSTITUTION:A square mean circuit 50 consists of a multiplier 51, a D/A converter 52 and an integration device 53. The multiplier 51 multiplies input digital signals, and generates and outputs a digital signal representing amplitude information of squared amplitude information of the input digital signal. After the output digital signal of the multiplier 51 is converted into an analog signal by the D/A converter 52, the result is fed to the integration device 53 composed of a resistor 54 and a capacitor 55, in which the signal is integrated and averaged. A voltage in response to a level difference between the output analog signal of the integration device 53 and a reference voltage (setting value) obtained by dividing a power voltage with resistors 66-68 is extracted from an operational amplifier 63 and the voltage is fed to a variable attenuator 20 as a control signal.

Description

[Detailed Description of the Invention] [Opportunity] II! in an interference compensator for a multilevel multiplexing radio device! II! S
Automatic interest rate that can be applied to 1! II Regarding the iIO device, the purpose is to perform automatic gain control without waveform equalization, and there is a variable attenuator that varies the amplitude of the input analog signal according to the control signal and outputs it, and the output of the variable attenuator. An A/D converter that converts a signal into a digital signal, an amplitude conversion circuit that converts amplitude information of an output digital signal of the A/D converter into amplitude information of an absolute value, and two output signals of the amplitude conversion circuit. A root mean square circuit takes the root mean, and the output signal of the root mean square circuit and a reference signal whose level is set in advance are compared in level to generate the I#JllI signal, and the tilJI
ll signal to the variable range 11! ! It consists of a control signal generation circuit that supplies the

[Industrial application field]

The present invention relates to an automatic gain control I device, and in particular to an automatic gain control I device that can be applied to a repeater in an interference compensator of a multilevel multiplex radio device. 1IIIll device.

In digital wireless relay transmission systems, multilevel modulation is used to perform highly efficient transmission in order to increase frequency utilization efficiency and obtain large transmission capacity. A receiving device used in such a digital radio relay transmission system has an automatic gain tIIIll device in the intermediate frequency stage. This automatic gain control device is required to be able to perform automatic gain control even when the radio receiving device described above has an interference compensator.

[Prior art] Figure 6 shows the conventional automatic row 1? A block diagram of an example of an ilJ control device is shown. In the figure, microwave bands received by antenna 1 (for example, 4, 5, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , as a microwave as microwave as a microwave band as a microwave band, for example, 4, 5 . . . .
The multilevel modulation radio digital signal of 6 GHz band is converted by the receiver 12 into a medium frequency signal of, for example, 11014 tlZ to 150 MHz. Here, as an example, the digital signal of the above multi-level modulation method is a 16-level orthogonal amplitude modulation signal.
1 (16QAM) signal.

The intermediate frequency signal from the received v12 is orthogonally detected by the quadrature detector 3, and the baseband 13MH2 to 14M) lz
After being converted into an analog signal, the signal is supplied to an A/D converter 4, and is also supplied to a clock regeneration circuit 5, where a clock signal is regenerated. The A/D converter 4 converts the input analog signal into a digital signal based on the clock from the clock reproduction circuit 5, and supplies the digital signal to the transversal equalizer 6.

The transversal equalizer 6 is provided to compensate for waveform distortion caused by fading that the received signal undergoes in the radio section, and performs RF domain waveform equalization.

A part of the waveform-equalized digital signal extracted from the transversal equalizer 6 is supplied as a carrier tlJm signal to a carrier oscillator 7 which outputs a carrier for detection to the orthogonal detector 3, The signals are supplied to the circuit 8 and the demodulation system, respectively.

The control O signal generation circuit 8 generates a gain control signal and supplies it to the A/D converter 4 to perform gain control of the signal attenuated due to fading.
A digital signal from which M attenuation of the digital value is substantially removed is output.

In this way, in this conventional automatic gain III control device, the gain*I is calculated from the output digital signal of the transversal equalizer 6.
Automatic gain is performed by generating a control signal.

By the way, the radio signal received by the receiver 2 inevitably undergoes fading and is a composite signal of a direct wave and an interference wave.

Therefore, in order to further reduce the influence of fading and improve line quality, it is necessary to reduce the interference wave component. FIG. 7 shows a block diagram of an example of a conventional automatic IJ m Ill III device having an interference compensator for reducing this interference wave component.

In the figure, the same components as those in FIG. 6 are denoted by the same reference numerals, and the explanation thereof will be omitted. In FIG. 7, the radio signal received by the antenna 11 is transmitted to the FM receiver 12 as FMI! I!
Then, the frequency is converted and the interference wave component in the intermediate frequency band is extracted.

This interference wave component is supplied to the orthogonal detector 13, where it is orthogonally detected, and then converted into a digital signal by the A/D converter 14. This digital signal is sent to the interference compensator 15.
Based on the interference compensation IIIm signal, it is converted into a digital signal having the same amplitude and opposite phase as the interference wave component contained in the output digital signal of the transversal equalizer 6, and then added. is supplied to the vessel 16. The adder 16 adds the output digital signal of the interference compensator 15 to the output digital signal of the transversal equalizer 6, thereby generating and outputting a digital signal in which the interference waves are substantially canceled. A part of the output digital signal of the adder 16 is branched and supplied to the interference compensator 15 as an interference compensation tI control signal.

Ru.

(Problem to be Solved by the Invention) However, in the conventional automatic gain control fMm shown in FIG. − Signal cannot be generated, so in interference compensation signal system, automatic gain −Ji
There was a problem that lt was not possible.

The present invention has been made in view of the above points, and an object of the present invention is to provide an automatic gain $1111 device that can perform automatic gain control without waveform equalization.

[Means to solve the problem]

FIG. 1 shows a block diagram of the present invention. In the same figure, 20
is a variable attenuator that reduces the amplitude of the input analog signal by $1111.
1. The output is varied according to the signal. 3o is an A/D converter that converts the output signal of the variable attenuator 20 into a digital signal. 40 is an amplitude conversion circuit which converts the amplitude information of the output digital signal of the A/D converter 830 into absolute value amplitude information.

A mean square circuit 50 calculates the mean square of the output signal of the amplitude conversion circuit 40. 60LtυIIO signal generation circuit, 2
The output signal of the mean circuit 50 and a reference signal whose level is set in advance are compared to generate the υ1W signal 8, and $
17911 Shingetsu is supplied to the variable reducer 20.

[Effect]

The output digital signal of the A/D converter 30 has amplitude information of the output analog signal of the variable attenuator 20 for each sampling period WAT, and since this 11 width information has a positive fj of 41%, the absolute value is converted by the amplitude conversion circuit 40. is converted into amplitude information. Assuming that an example of the amplitude information of the absolute value represented by the digital signal taken out from the amplitude conversion circuit 40 is schematically represented by an arrow in FIG. The signal is converted into a signal at the level shown by the dashed line in Figure 2. The output signal g of the mean square circuit 50 indicates a value corresponding to the average power (relative power) of the input analog signal.

The IIJwJ signal generation circuit 60 compares the output signal level of the mean square circuit 50 with the reference signal level (set value) shown by the broken line in FIG. 2, and generates a control signal such that the difference δ between them becomes zero. is generated and supplied to the variable attenuation B20, and its attenuation amount is variably controlled.

As described above, in the present invention, the level corresponding to the average power (relative value) of the input clock signal is calculated from the output digital signal of the A/D converter 30, and the difference δ between the level and the set value is calculated.
If the calculated level is higher than the set value, the attenuation amount of the variable attenuator 20 is increased, and on the other hand, when the calculated level is lower than the set value, the attenuation amount of the variable attenuator 20 is decreased. By doing this, the automatic profit 1? is set such that the above calculated level is always equal to the set value. IIJ II! l
I can do it.

〔Example〕

FIG. 3 shows a configuration diagram of an embodiment of the present invention. In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted. This embodiment is applied to the A/D converter 14 in the device shown in FIG. 7, and the variable attenuator 20 in FIG. A signal is input.

The A/D converter 30 performs analog-to-digital conversion on the output analog signal of the variable attenuator 20, as shown in FIG. The digital signal of
The signal is supplied to the interference compensator 15 shown in the figure, and also to the amplitude conversion circuit 40 shown in FIG.

This amplitude conversion circuit 40 has, for example, a @-path configuration as shown in FIG. In the figure, 41 is an inverter, 42+~
427 is the exclusive OR of two people ([(EX-OR@I
) F, 8/D [[130 (F) The most significant hit (MS8) among the 8-bit parallel output digital signals is a pass (Pat
h) 1 to the inverter 41, and the 2nd to least significant bits (LSB) are respectively input to Path 2~
8 separately to one input terminal f of each of the EX-OR circuits 42+ to 427, and is further input to the EX-OR circuits 421 to 427.
The output signals of the inverters 41 are commonly input to the other input terminals of the inverters 427, respectively.

Here, the MSB of the 8-bit parallel output digital signal of the A/D converter 3o is a polarity bit as shown in FIG. 5, and is "1" for positive amplitude information and O for negative amplitude information.
The 7 bits from the 2nd bit to the 8th bit represent amplitude information according to the rules shown as paths 2 to 8 in FIG. Therefore, at the maximum positive amplitude, all 8 bits are "1", and at the maximum negative amplitude, all 8 bits are "1".
O”.

Therefore, according to the amplitude conversion circuit shown in FIG.
When the bit digital signal represents positive amplitude information, the EX-OR circuits 421 to 427 output the values of the 2nd to 8th bits as they are as output data D.
Since the amplitude information is extracted as s''Do, the positive amplitude information indicated by α in FIG. 5 is extracted as is as positive amplitude information α1.

On the other hand, the input 8-bit digital signal is α
Tokiha, EX, which represents negative amplitude information as shown in 2.
0R11142+ ~427 h"E) Since the values of each bit from the hash bit to the 8th bit are inverted and taken out as output data 06~Do, the output data D6~Do is a positive value as shown by α2' in FIG. It is converted into amplitude information and extracted. Therefore, the amplitude information conversion circuit 4
0, a digital signal indicating the absolute value of the amplitude information of the 8-bit digital signal output from the A/D converter 30 is extracted, and the third rj! Multiplier 5 in the mean square circuit 50 shown in J
1.

As shown in FIG. 3, the mean square circuit 50 includes a multiplier 51.
It is composed of a D/A converter 52 and an integrator 53.

The multiplier 51 multiplies the input digital signal and generates and outputs a digital signal representing amplitude information obtained by squaring the amplitude information of the input digital signal g. Here, the amplitude information of the input digital signal of the multiplier 51 indicates the absolute value of the voltage, which is the amplitude information of the input analog signal of the A/D converter 30,
On the other hand, the power of the input analog signal (baseband signal) is proportional to the square of the absolute value of this voltage. Therefore, multiplier 5
1, a digital signal whose value is proportional to the power of the input analog signal is taken out.

The output digital signal of this multiplier 51 is a D/A conversion t! A
After being converted into an analog signal by B52, it is supplied to an integrator 53 consisting of a resistor 54 and a capacitor 55, where it is integrated and averaged. Therefore, an analog signal having a level corresponding to the average value of the power represented by the input analog signal q of the A/D converter 30 is taken out from the integrator 53 and supplied to the am signal generation circuit 60.

The tllWJ signal generation circuit 60 is composed of a control signal generator 61 and a reference voltage generator 62, as shown in FIG. 1111111 signal generator 61 is operational amplifier 16
3, resistors 64 and 65, and a reference voltage generator 6
2 has a configuration in which resistors 66 to 68 are connected in series between power supply terminals. As a result, a voltage corresponding to the level difference between the output analog signal of the integrator 53 and the reference voltage (the set value) obtained by dividing the power supply voltage by the resistors 66 to 68 is extracted from the amplifier 63. , are provided to variable attenuation 120 as a control signal.

Since the gain of the variable range II converter 20 is controlled by the control signal in a direction that reduces the above difference, the output digital signal of the A10 converter 30 that converts the output signal of the variable attenuator 20 into a digital signal is as follows. The average power (relative chain) obtained from the amplitude information is the base Ff-voltage (setting 11
1i) so that the profit is equal to 1? $17 w and taken out.

Therefore, according to this embodiment, automatic gain control can be performed on the input side of the interference compensator 15.

Note that the present invention is not limited to the above-described embodiments, and can be applied to all signal systems, including signal systems that do not perform waveform equalization.

(Effects of the Invention) As described above, according to the present invention, automatic gain control is performed so that the average power of the input analog signal is equal to a desired set value, and therefore automatic gain control is performed even for signals that are not subjected to waveform equalization. It has the advantage that it can be applied to any system and is highly versatile.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of the operation of the present invention, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is a block diagram of an embodiment of an amplitude conversion circuit. , FIG. 5 is an explanatory diagram of the operation of FIG. 4, FIG. 6 is a block diagram of an example of a conventional device, and FIG. 7 is a block diagram of an example of a conventional device with an interference compensator. In the figure, 20 is a variable attenuator, 30 is an A/D converter, 40 is an amplitude conversion circuit, 50 is a mean square circuit, and 51 uf! 11! ! . 52 is a D/A converter, 53 is an integrator, and 60 is a 1111+ signal generation circuit. Fig. 1 Block diagram of the principle of the present invention Fig. 2 An explanatory diagram of the operation of the invention Fig. 2 A configuration diagram of an embodiment of the amplitude conversion circuit Fig. 4 An explanatory diagram of the operation of Fig. 4 Fig. 5

Claims (1)

[Claims] A variable attenuator (20) that varies the amplitude of an input analog signal according to a control signal and outputs it, and an A/D converter that converts the output signal of the variable attenuator (20) into a digital signal. the A/D converter (30), and the A/D converter (30).
) for converting the amplitude information of the output digital signal into absolute value amplitude information; and 2 for taking the root mean square of the output signal of the amplitude conversion circuit (40).
a root-mean-square circuit (50), which generates the control signal by comparing the output signal of the root-mean-square circuit (50) with a reference signal whose level is set in advance, and transmits the control signal to the variable attenuator; (20) A control signal generation circuit (60) for supplying a control signal to the control signal generating circuit (60).