JPH03254240A - Cell transmitter-receiver - Google Patents

Abstract

PURPOSE:To reduce the buffer quantity required for a receiver equipment and the delay by the processing by applying coding in a small block, applying coding in a large block and allowing a receiver side to control an output of each small block depending on the propriety of abort and compensation in the unit of a small block. CONSTITUTION:A sender side equipment has a means 6 generating outputs of 1st coding means 2-5 to p-set of check bit cells, [N-p] sets of cells and p-sets of check bit cells form one small block and has means 10, 14, 15 generating outputs of 2nd coding means 7-9, 11-13 to qXN sets of cells. A receiver side equipment is provided with a 1st cell abort compensation means 23 applying cell abort compensation in a small block through decoding and a 2nd cell abort compensation means 24 applying cell abort compensation in a small block through decoding and discriminates whether or not cell abort compensation in a block is enabled with the 1st cell abort compensation means 23 and the 2nd cell abort compensation means 24 and stops the abort compensation when the discrimination is made to be disable and a cell output is restarted. Thus, the cell abort is compensated in a short signal processing time in average.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to information communication in units of cells or packets. In particular, the present invention relates to a cell transmitting/receiving device capable of correcting information loss.

The present invention performs coding within a small block, further performs coding within a large block, and controls the output of each small block depending on whether or not cell discard compensation can be performed in units of small blocks. This reduces the amount of buffer required for the device and the amount of delay due to processing.

[Conventional technology]

When communicating in units of cells or packets, information may be lost on the transmission path.

The applicant of this application has already filed a patent application for a communication device capable of compensating for such deficiencies in Japanese Patent Application No. 1-116.
No. 984, "Packet Communication Device", hereinafter referred to as "earlier application").

FIG. 12 shows the arrangement of parity cells in the earlier application.

On the transmitting side, for integers N and k greater than or equal to 2, Nx(k-
1,) cells are information cells, and N cells are parity cells. The parity cells are generated by the modulo-2 sum of each bit position of the information cells in each column in the matrix in FIG. This allows compensation for up to one cell discard for each column. Therefore, the entire matrix can compensate for up to N consecutive cell discards.

On the receiving side, if there is one discarded cell in a column, we can request 2 for each bit position of the remaining (k-1> cells in the column. matches discarded cells.

[Problem to be solved by the invention]

However, in the method shown in the previous application, it is necessary to temporarily store the entire matrix consisting of Nxk cells in order to compensate for cell discard, which has the problem of increasing signal processing delay on the receiving side.

An object of the present invention is to solve this problem and provide a cell transmitting/receiving device that can compensate for cell discard with an averagely short signal processing time.

[Means to solve the problem]

The cell transmitting/receiving device of the present invention is a cell transmitting/receiving device that transfers a cell constituted by a header section including a NXM type of sequence number and a data section for an integer N1M of 2 or more from a transmitting side device to a receiving side device. The sending device is 1 or more N
For each bit position of [N-p) cells for an integer p less than
a first encoding means for encoding bits; the output of this first encoding means is inserted into p check bit cells;
a means for generating [M-q) test bit cells for an integer q of 1 or more and less than M; a second encoding means for systematically encoding N sets of cells having the same small block cell position, with a data part of [M-q] bits and a check bit of q bits for each bit position; and means for inserting the output of the encoding means into the corresponding bit positions of the q cells of the same set to generate q×N sets of cells, the receiving device means for detecting the cell discard position from the sequence number of the cell and inserting a dummy cell at that position, and decoding the N cells in the small block by the first encoding means and inverse logic to a first cell discard compensation means for compensating for discard; and a second cell discard compensation means for compensating for cell discard by decoding by reverse logic with the second encoding means when cell discard compensation cannot be performed within a small block. the first cell discard compensation means includes means for detecting the first dummy cell in the small block and stopping cell output; and means for restarting cell output after the discard compensation is completed; The second cell discard compensation means is characterized in that it includes means for detecting the first dummy cell in the large block and stopping cell output, and means for restarting cell output after the discard compensation is completed.

The first cell discard compensation means includes a means for determining whether cell discard compensation is possible within a small block from the number of dummy cells inserted into the small block, and a means for determining whether cell discard compensation is possible within the small block, and when the means for determining is determined to be impossible. It is desirable to include means for canceling discard compensation and restarting cell output.

The second cell discard compensation means also includes means for determining whether discard compensation is possible within a column from the number of dummy cells in the column for each column within a large block, and compensation for discard when this means is determined to be impossible. It is desirable to include means for stopping the cell output and restarting the cell output.

C operation] A small block is formed by N cells, and a large block is formed by collecting M small blocks. Encoding is performed within a small block, and further encoding is performed within a large block. Furthermore, the transmission of each small block is controlled depending on whether cell discard compensation can be performed on a small block basis.

The transmitting device inserts information data into the data part of CN-p cells, and inserts the information bits [N-p] bits and the structure of the inspection pit for each bit position of the [N-pE cells. Perform encoding.

This encoding is hereinafter referred to as CN-p,p) encoding.

The check bits generated corresponding to each bit position by this encoding are inserted into p check bit cells. A small block is composed of a total of N cells, including these information cells CN-p and nine check bit cells.

Furthermore, the transmitting device encodes [M-q, q] for each bit position for N sets of [M-q 1 cells at each cell position of f: M-q] small blocks, and generates The check bits thus obtained are inserted into q×N cells to generate q check bit small blocks. As a result, information amount blocks [M-q] and q check bit small blocks are obtained,
A total of M small blocks constitute a large block.

In the receiving side device, a cell discard detection unit detects cell discard from the order number of the header section of the received cell, and inserts a dummy cell at the position where the cell was discarded.

If no dummy cell is detected, the discard compensation section of the receiving device outputs the received cell as is, and stores a copy of the received cell in the device. When a dummy cell is detected, output is stopped at that point and waits until reception of the small block to which the cell belongs is completed. Thereafter, the [N-p, p:] code is decoded for each bit position of the cell within the small block.

As a result, when cell discard compensation is completed within that small block, output is restarted at that point. If it is not possible to compensate for cell discard within the small block, the entire large block is accumulated without restarting output. Then, for each bit position, for M cells in each column of the large block, [:M
−q, q] encoding to compensate for discarded cells that could not be compensated within the small block. Thereafter, output is resumed from the cells that had stopped output.

In this way, if there is no cell discard or if it can be compensated within a small block, the signal processing delay associated with decoding on the receiving side can be shortened. Furthermore, cell discards that cannot be compensated for within a small block are compensated for if compensation is possible within a large block.

〔Example〕

1 to 6 are diagrams showing a first embodiment of the present invention, in which FIG. 1 is a block configuration diagram of a transmitting side device, FIG. 2 is a block configuration diagram of a receiving side device, and FIG. 3 is a block diagram of a receiving side device. FIG. 4 is a block diagram of the small block cell discard compensation circuit in the receiving side device. FIG. 5 is a block diagram of the large block cell discard compensation circuit in the receiving device. The configuration diagram, FIG. 6, is a configuration diagram of a large block.

This embodiment device has NXM for integers N and M of 2 or more.
This is a device that transfers a cell composed of a header section including a type sequence number and a data section from a transmitting side device to a receiving subdevice, and uses a parity check code as an error control code for both small blocks and large blocks. It is used.

In this example, the small blocks are as shown in FIG.
Normal data cells [constructed by adding one parity cell to N-IEs. The parity cell is [N-
1] by performing addition modulo 2 for each bit position for the data portion of the cell.

Further, as shown in FIG. 6, the large block includes normal small blocks [M-1] containing [N-1] data cells,
It is composed of parity and one small block. Parity - Each cell in the small block is generated by performing modulo-2 addition for each bit position of [M-1] cells in the same column in the large block.

As shown in FIG. 1, the transmitting side device uses a first code that performs encoding in which the data part is CN-1] bits and the check bit is 1 bit for each bit position of [N-1] cells. Buffer 2, [N-13 base counter 3, parity]
It includes a cell holding memory 4 and an adder circuit 5 that calculates a sum modulo 2 for each bit position in the cell, and inserts the output of this first encoding means into one test bit cell to perform one test. As a means for generating bit cells, a changeover switch 6 with two manual outputs is provided, and one small block is composed of [N-1] cells and one test bit cell, and [M-1]
For N sets of cells in which the cell positions of the small blocks are the same, the data part for each bit position is [A buffer 7 as a second encoding means that performs systematic encoding with M-IE bits and 1 check bit; An NX [M-1] base counter 8, an N base counter 9, a parity cell holding memory 12 that holds parity cells for N cells in the row direction, and a cell position to be accessed for this parity cell holding memory 12. It includes a selector 11 for specifying and an adder circuit 13 that calculates a sum modulo 2 for each bit position in the cell, and outputs the output of this second encoding means to the corresponding bit position of one cell in the same group. As a means of inserting and generating N sets of cells, two people and one
Output selector switch 10.14 and N-ary counter 15
Equipped with

To operate this transmitting side device, first, the values of the [N-1] base counter 3 and the parity cell holding memory 4 are all set to "0", and the changeover switch 6 is set to the buffer 2 side. Also, set all the values of NX [M-1: 1-ary counter 8, N-ary counter 9, N-ary counter 15, and parity cell holding memory 12 to "0", and switch the selector switch 10 to the N-ary counter 9 side. The switch 14 is set to the buffer 7 side.

Cells to be transmitted are input from input terminal 1 and sent to buffer 2.
It passes through and reaches the selector switch 6. During this time [N-1]
The forward counter 3 counts the number of cells output from the buffer 2 and reaching the changeover switch 6. The parity cell holding memory 4 and the addition circuit 5 calculate the sum (accumulation) modulo 2 for each bit position of the passed cells, and
Generate cells.

The changeover switch 6 is switched at the time when the [N-1] base counter 3 counts the number of cells [N-1] and returns to "0",
Output the generated parity cell. While outputting the parity cells, the cells manually input from the input terminal 1 are held in the buffer 2 and wait until the output of the parity cells is completed.

After the 17th cell is output, the selector switch 6 is returned to the buffer 2 side, the parity cell holding memory 4 is initialized, and the cell input to the input terminal 1 is output again as it is.

By the above operation, one parity cell is inserted for each input cell [N-1], and a small block is formed.

Subsequently, the cell passes through the buffer 7, reaches the changeover switch 14, and is output from the transmitting device.

During this time, Nx (M-1) base counter 8, N base counter 9
counts the number of cells passing through.

When the count value of the N-ary counter 9 is 1, the addition circuit 13
The first parity cell among the parity cells stored in the parity cell holding memory 12 and the buffer 7
2 can be specified for each bit position for the output cells. As a result, the cell is returned to the first cell position in the parity cell holding memory 12. As a result, parity cells corresponding to each column of the large block are stored in each cell position of the parity cell holding memory IJ12. Therefore, the parity cell holding memory 12 as a whole generates parity small blocks.

When NX [M-1] cells pass through and the NX [M-1] base counter 8 becomes "0", the changeover switches 10.14 switch the N-base counter 9 side and the parity cell holding memory respectively. It can be switched to the 12 side.

As a result, a parity small block is output.

The N-ary counter 15 counts the number of cells in the output parity small block, and specifies the output cell position of the parity cell holding memory 12 via the selector 11.

While outputting a parity-small block, the cells that have passed through the changeover switch 6 are accumulated in a buffer 7, and wait until the output of that block is completed.

Parity - When N values of cells in a small block are output, N
The base counter 15 returns to "D", and at that point, the changeover switch 14 is returned to the buffer 7 side, the changeover switch IO is returned to the N-base counter 9 side, and the value of the parity cell holding memory 12 is set to "0".

By the above operation, one parity small block is inserted for every [M-1] small blocks, and a large block is formed.

In this way, one parity cell is inserted for every [N-IE] input cells to form a small block, and one parity small block is inserted for every [:M-p] small blocks.
A large block is formed. The sending device is
This large block is the unit of transmission.

As shown in FIG. 2, the receiving device includes a cell discard detection and dummy cell insertion circuit 22 as a means for detecting the cell discard position from the sequence number of the cells in the received small block and inserting a dummy cell at that position. cells in a small block as a first cell discard compensation means for decoding N cells in a small block using logic inverse to the first encoding means of the transmitting side device and compensating for cell discard within the small block. The large block is equipped with a discard compensation circuit 23, and is used as a second cell discard compensation means for decoding by reverse logic to the second encoding means of the transmitting side device to compensate for cell discard for cells having the same cell position within the small block. An inner cell discard compensation circuit 24 is provided.

The received cells are input from an input terminal 21 to a cell discard detection and dummy cell insertion circuit 22 . The cell discard detection and dummy cell insertion circuit 22 detects cell discard from the sequence number of the header section of the cell, and inserts a dummy cell into the discarded cell position. The intra-small block cell discard compensation circuit 23 compensates for compensable cell discard using parity cells within the small block.

The intra-large block cell discard compensation circuit 24 compensates for compensable cell discard using parity-small blocks.

As shown in FIG. 3, the intra-small block cell discard compensation circuit 23 is configured to perform cell discard compensation within the small block by adjusting the N-ary counter 32. Addition circuit 35.37 that calculates the sum modulo 2 for each time, parity cell holding memory 36.38.2 manual 1 output changeover switch 39.40, buffer 41, N
Advance counter 42 and 2-manpower 1-output selector switch 43
A header identification circuit 44 is provided as a means for detecting the first dummy cell in a small block and stopping cell output, and a header identification circuit 44 is provided as a means for restarting cell output after discard compensation is completed. It is connected to the identification circuit 44. Furthermore, this small block cell discard compensation circuit 2
3 is provided with a header identification circuit 33 as a means for determining whether cell discard compensation is possible within a small block based on the number of dummy cells inserted in the small block, and when this determining means determines that it is impossible. The output of the header identification circuit 33 is connected to a header identification circuit 44 as a means for canceling discard compensation and restarting cell output.

At the time of initial setting, the N-ary counter is 32.42, the parity is
The values of the cell holding memories 36 and 38 are all set to "O", the header identification circuits 33 and 44 are initialized, and the changeover switch 34 is set to "O".
．． 39 is set to the addition circuit 35 side, the changeover switch 40 is set to the parity cell holding memory 36 side, and the changeover switch 43 is set to the buffer 41 side.

The cell input from the input terminal 31 is transferred to the selector switch 34
．． 39, a buffer 41, a changeover switch 43, and is output. During this time, the N-ary counter 32 counts the number of input cells.

When N cells constituting each small block are received, the count value of the N-ary counter 32 becomes "0". This count value is “
0'', the header identification circuit 33.44 is initialized and the changeover switch 34.39 is switched.

Addition circuits 35.37 perform modulo-2 addition for each bit position of each cell in the received small block, and parity cell holding memories 36.38 hold parity cells generated by the addition. Parity-cell holding memory 3
6.38, one of them holds the parity cell in progress corresponding to the small block currently being received, and the other holds the completed parity cell corresponding to the small block received immediately before.

The N-ary counter 42 counts the number of output cells, and switches the changeover switch 40 every time the count value reaches "0" upon receiving N cells forming a small block. As a result, the changeover switch 40 changes the parity cell holding memory 36.3.
8, the memory holding the parity cell corresponding to the small block currently being output is selected.

The header identification circuit 44 determines the header of the cell to be output, and distinguishes between normal cells and dummy cells.

When a dummy cell is detected, the selector switch 43 is temporarily set to a neutral state and cell output is interrupted. Cells input during this time are stored in the buffer 41.

The subsequent operation differs depending on whether the header identification circuit 33 detects two dummy cells in the same small block.

When reception of a small block is completed without detecting a dummy cell and a parity cell is completed, the count value of the N-ary counter 32 becomes "0", and upon receiving this signal, the header identification circuit 44 switches. Change switch 43 to switch 4
Switch to the 0 side and output a parity cell. At the same time, the changeover switch 43 discards the dummy cell. That is, the dummy cell is replaced with a parity cell, and cell discard compensation is completed. The changeover switch 43 is
After outputting one parity cell, the circuit switches to the buffer 41 side.

If the header identification circuit 33 detects two dummy cells while inputting a small block, it stops cell discard compensation for that small block and immediately returns the header identification circuit 44 to the header identification circuit 33.
sends a detection signal to. The header identification circuit 44 switches the changeover switch 43 to the buffer 41 side.

As a result of the above operations, (1) If there is no discarded cell within the small block, the input cell passes through as is. Therefore, in that case, the delay time is extremely small.

■ If there is one discarded cell in a small block, the cell that was manually input before that discarded cell is output as is, and then a dummy cell is output when the reception of the small block is completed and the parity cell is completed. Cell discard compensation is performed by replacing the parity cells with parity cells. Therefore, even with cell discard compensation, the time order of the cells is preserved.

■ If two or more cells are discarded in a small block, output them as dummy cells. Therefore, erroneous corrections will not be made.

Effects such as this can be obtained.

The intra-large block cell discard compensation circuit performs intra-large block cell discard compensation as shown in FIG.
Advance counter 51.1 Manual power 2 output selector switch 52, N
Advance counter 53.62, switch 54.63, selector 55.57.64.66 that specifies the cell position to be accessed for memory for N cells, parity for N cells.
Cell retention memo! J56.65, Addition circuit that calculates the sum modulo 2 for each bit position in a cell 80.81.2 Manually powered 1 output selector switch 71.73.1 Manually powered 2 output selector switch 72, N-ary counter 74 , (Equipped with an MXNI counter 75.2 a changeover switch 76.2 for a single human output output, and a buffer 78 for detecting the first dummy cell in a large block and stopping the output of the cell) [MXN
) The output of the advance counter 51 is connected to the header identification circuit 79.

In addition, as a means for determining whether or not discard compensation is possible within a column based on the number of dummy cells in each column in a large block, a correction prohibition flag holding memory that holds 2) XN correction prohibition flags is used. 59.68, selectors 58 and 60.6 that respectively designate the flag position to be accessed for this correction prohibition flag holding memory 59.68.
7 and 69, and a header identification circuit 61.70, and when it is determined that this means is impossible, the output of the correction prohibition flag holding memory 59.68 is connected to the changeover switch 73 as a means for canceling discard compensation and restarting cell output. The header identification circuit 79 is connected to the header identification circuit 79 via.

As an initial state, the [MXN] base counter 51.75, N
The values of the decimal counter 53, 62, 74, the parity cell holding memory 56.65, and the correction prohibition flag holding memory 59.68 are all set to "0", the header identification circuit 79 is initialized, and the changeover switch 52.77 is set to N digit. Set the changeover switch 71 to the counter 53 side, set the changeover switch 71 to the parity cell holding memory 56 side, set the changeover switch 73 to the correction prohibition flag holding memory 59 side, and set the changeover switch 76 to the buffer 78 side.

The cell input from the input terminal 50 is transferred to the selector switch 52.
．． 77, a buffer 78, and a changeover switch 76 before being output. During this time, the [MXN) base counter 51 counts the number of input cells.

When MxN cells forming a large block are received, [
MXN] The count value of the decimal counter 51 becomes "OJ". Each time this count value becomes "0", the changeover switch 52.77 is switched.

When the selector switch 52 is set to the N-ary counter 53 (62), the N-ary counter 53 (62) determines the cell position within the small block (column in the large block) of the received cell based on its count value. indicate.

When the count value of the N-ary counter 53 (62) is 1, the selector 55, 58 (64, 69) selects the parity cell holding memory 1J56 (6) as the access target.
5), the first element of the correction prohibition flag holding memo 'J 59 (68) is selected. The adder circuit 80 (81) stores the received cell and parity cell holding memory 56 (6
5) and the first parity cell of 5), calculate the sum modulo 2 for each bit position, and return the result to the first element of the parity cell holding memory 56 (65).

The header identification circuit 6H70) inspects the header part of the received cell, and if the received cell is a dummy cell, changes the flag of the first element of the correction prohibition flag holding memo 'J59 (68). This flag has a 2-bit structure; ■ If both bits are "0", the first bit is "1".
Make it.

■ If only the first bit is "1", the second bit is also set to "l".

■ If both bits are "1", do not change.

It is set as follows. As a result, if two or more cells are discarded in the same column within a large block, the correction prohibition flag is retained. Both two bits of the flag corresponding to that column of J59 (68) become "1".

Of the pair of parity cell holding memory 56 and correction prohibition flag holding memory 59, and the pair of parity cell holding memory 65 and correction prohibition flag holding memory 68, one has a set of a parity cell holding memory 56 and a correction prohibition flag holding memory 68, and one of them has a set of a parity cell holding memory 56 and a correction prohibition flag holding memory 68, and one has a set of A parity small block and a correction prohibition flag are held, and a completed parity small block and a correction prohibition flag corresponding to the large block that has just finished receiving are held.

The [MxN] digit counter 75 counts the number of cells output from the buffer 78, and every time the count value becomes "0" after transmission of one large block, the changeover switch 71.7 is turned on.
Switch 2.73. This makes it possible to access the parity cell holding memory 56 or 65 and the correction inhibition flag holding memory 59 or 68 corresponding to the large block being output.

By counting the number of output cells, the N-ary counter 74 identifies the column to which the cell belongs within the large block;
Corresponding elements of parity-cell holding memory 56.65 and correction inhibit flag holding memory 59.68 are made accessible.

The header identification circuit 79 discriminates between a normal cell and a dummy cell from the header of the cell to be output, and when detecting the first dummy cell in the large block, sets the changeover switch 76 to a neutral state and interrupts cell output. Cells input during this period are stored in a buffer 78. When reception of the large block is completed while cell output is interrupted, ['MX
The count value of the N]-adic counter 51 becomes "0". At this point, the header identification circuit 79 releases the output stop of the changeover switch 76.

After that, the header identification circuit 79 inspects the header part of the cell to be output, and if the cell is a dummy cell and the second bit of the correction prohibition flag for the corresponding column position is "0", the changeover switch 76 is switched. The switch 71 is switched to output the parity cell, and at the same time the dummy cell is discarded by the changeover switch 76. This replaces dummy cells with parity cells and compensates for cell discard.

If the cell to be output is a normal cell, or if both bits of the correction prohibition flag for the corresponding column position are "1", the selector switch 76 is set to the buffer 78 side, and the cell output from the buffer 78 is output as is. do.

As a result of the above operations, (1) If no cells are discarded within the large block, the received cells are output as they are, so the delay time is extremely small.

■ For each column in a large block, cells are not discarded for columns in which two or more cells are discarded, so erroneous compensation is not performed.

■ When performing cell discard compensation, buffering is performed from the position of the first dummy cell in a large block, so even when discard compensation is performed, the time order of cells is maintained.

■ Since it is possible to compensate for one cell discard within the column for each column, it is possible to compensate for a maximum of N consecutive cell discards.

Effects such as this can be obtained.

7 to 11 are diagrams showing a second embodiment of the present invention, in which FIG. 7 is a block diagram of a transmitting device, and FIG. 8 is a block diagram of a small block cell discard compensation circuit in a receiving device. 9 is a block diagram of a cell discard compensation circuit in a large block in the receiving side device, FIG. 10 is a diagram of a small block used in this embodiment, and FIG. 11 is a diagram of a large block. It is.

This embodiment device has NXM for integers N and M of 2 or more.
This is a device that transfers a cell composed of a header section including a type sequence number and a data section from a transmitting side device to a receiving side device, and transmits CN, N- as an error control code in a small block.
p] systematic code is used, and [M, M-q] systematic code is used as an error control code in the th block.

In this example, a small block is generated using CN, N-p) encoding for each bit position of each cell for normal data cells CN-p, as shown in FIG. Arrange the check bits of p bits in the corresponding bit positions and write p
A small block is formed by a total of N cells, including normal cells CN-p] and nine test pit cells.

Further, as shown in FIG. 11, the large block is composed of a small block consisting of data cells CN-pE and nine test bit cells. Regarding these small blocks [M-q],
For [M-q) cells belonging to the same column, perform [M, M-q:) encoding for each bit position, arrange the generated q check bits at the corresponding bit positions, and then Generate test bit cells. Since N test bit cells are roughly generated corresponding to each column, q test bit small blocks each consisting of N test bit cells are obtained.

A large block is constituted by a composite of M small blocks consisting of [M-q) normal small blocks and q check bit small blocks.

As shown in FIG. 7, the transmitter side device, for an integer p greater than or equal to 1 and less than N, the data part is [N-p] bits and the check bit is [N-p] bits for each bit position of [N-p] cells. As a first encoding means for encoding p bits, a buffer 102,
[N-p] base counter 103, address generation circuit 104
, [N-p) memory 105 for cells, CN, N-p) Hamming encoder 106 and p cells memory 107, and inserts the output of this first encoding means into p check bit cells. As a means for generating p test bit cells, an address generation circuit 108, a p-adic counter 109, and a changeover switch 110 with two inputs and one output are provided, [Np]
For N sets of cells in which one small block is composed of cells and p check bit cells, and the cell positions of [M-Q] small blocks are the same for an integer q of 1 or more and less than M,
As a second encoding means that performs systematic encoding in which the data part is [M-q] bits and the check bits are q bits for each bit position, a buffer 111, an N-ary counter 112, [M-q] bits are used as a second encoding means.
:] decimal counter 113, address generation circuit 114, N
x [M-q:] Memo for cells! 015, [M, M
-q:) Equipped with a Hamming encoder 116, a memory 117 for Nxq cells, and an NX[M-q) base counter 121,
An address generation circuit 118, an N-adic counter 119, and a q-adic counter are used as means for inserting the output of this second encoding means into corresponding bit positions of q cells of the same set to generate q×N sets of cells. It is equipped with a counter 120 and a two-manpower one-output changeover switch 122.

To operate this sending device, as an initial setting, C
N-p] base counter 103, p base counter 109,
N-ary counter 112.119, [M-q]-ary counter 1
13, the count values of the Q-ary counter 120 and the NX[:Mq]-ary counter 121 are set to "O", and the selector switch 11 is set to "O".
0 is set on the buffer 102 side, and the selector switch 122 is set on the buffer 111 side.

Cells to be transmitted are input from input terminal 101 and input to buffer 111 via buffer 102 and changeover switch 110. At this time, the [N-p] base counter 103 counts the number of cells output from the buffer 102, and switches the selector switch 110 when [N-p:] cells have passed. As a result, cell output from the buffer 102 is stopped, and cells from the input terminal 101 during that time are accumulated in the buffer 102.

The memory 105 stores data from the buffer 102 to the buffer 111.
Accumulate copies of cells sent to . This memory 105
The address specification of [
This is performed using the count value of the N-p) base counter 103.

[N, N-p) Hamming encoder 106 is stored in memory 10
5, when CN-p) cells are accumulated, CN, N-p] encoding is performed for each bit position. The p test bit cells generated as a result are stored in the memory 107, and
Following the data cells CN-p), a changeover switch 110
The data is input to the buffer 111 via.

The p-adic counter 109 counts the number of output test bit cells, and the address generation circuit 108 specifies the address of the memory 107. The output of the check bit small block is finished,
When the count value of the p-adic counter 109 reaches "0", the changeover switch 110 is switched to the buffer 102 side at that point.

In this way, one data cell [N-p] and nine check bit cells are sequentially output from the changeover switch 110 to form a small block.

The cells input from the changeover switch 110 to the buffer 111 further pass through the switch 122 and are output. At this time, the NX[M-ql base counter 121 counts the number of cells output from the buffer 111, and the cell
-q) Switch the selector switch 122 at the time of passing. As a result, cell output from the buffer 111 is stopped, and cells from the selector switch 110 during this period are accumulated in the buffer 111.

The memory 115 is connected from the buffer 111 to the changeover switch 1.
A copy of the cell sent to 22 is stored. [M.

M-q] Hamming encoder 116 determines whether the cell is NXI:M-
p] is accumulated in the memory 115.
A column is constructed for each cell position of M-91 small blocks, and encoding is performed for each bit position of [M-91 cells belonging to each column] [M, M-q]. As a result, q test bit cells Nu are obtained, which are stored in the memory 117 as q test bit small blocks. Memo 1J1
The check bit small blocks accumulated in the test bit block 17 are sequentially outputted via the changeover switch 122 following the normal small blocks [M-q).

The N-ary counter 119 and the Q-ary counter 120 count the number of cells in the output check bit small block, and address of the memory 117 is specified by the address generation circuit H8. Further, when the output of the check bit small block is completed and the count value of the q-ary counter 120 returns to "0", the changeover switch 122 is switched to the buffer 111 side.

In this way, large blocks are disciplined.

The basic configuration of the receiving side device used in this example is the second
This is equivalent to the embodiments shown in the figure. That is,
A received cell is input from the input terminal 21 to the cell discard detection and dummy cell insertion circuit 22, and the cell discard detection and dummy cell insertion circuit 22 detects cell discard from the sequence number of the cell header and inserts a dummy cell at the discarded cell position. is inserted, and the intra-small block cell discard compensation circuit 23 compensates for compensable cell discard using the parity cells within the small block. The intra-large block cell discard compensation circuit 24 compensates for compensable cell discard using parity-small blocks.

The intra-small block cell discard compensation circuit 23, as shown in FIG.
, N-ary counter 144.149.157, address generation circuit 145.150, memory for N cells 146.151
, CN, N-p) Hamming decoder 147.152, memory for N cells 148.153.1 manual power 2 output changeover switch 154, address generation circuit 155.2 manual power 1 output changeover switch 156.158.160, and buffer 1
62, and a header identification circuit 15 as means for detecting the first dummy cell in the small block and stopping output of the cell.
9, and the output of the N-ary counter 141 is connected to the header identification circuit 159 as means for restarting cell output after the discard compensation is completed.

Additionally, there is a means for determining whether cell discard compensation is possible within a small block based on the number of dummy cells inserted in that small block, and when this means for determining is determined to be impossible, discard compensation is stopped and cells are What is the means to resume output?
[N, N-p:] Hamming decoder 14? , 152.

In order to operate this intra-small block cell discard compensation circuit 23, first, as an initial setting, the N-ary counter 141.14
4. Set all the values of 149 and 157 to "0", set the changeover switch 143.15g to the N-ary counter 144 side, set the changeover switch 154.156 to the memory 148 side, and set the changeover switch 160 to the changeover switch 158 side. Set to .

The cell input from the input terminal 161 is transferred to the selector switch 1.
43.158, buffer 162 and changeover switch 1
60 and is output. During this time, the N-ary counter 14
1 counts the number of cells manually, and every time the reception of a small block is completed and the count value becomes "0", the changeover switch 143.15
Switch 8.

Memo 'J146.151 stores a copy of the cell that has passed from changeover switch 143 to changeover switch 158. The CN, N-pl Hamming decoder 147.152 decodes the small block when the storage of the small block in the memo IJ146.151 is completed.

At this time, if the number of dummy cells in the small block is within the correction capability, correction is performed, and if the number of dummy cells exceeds the correction capability, no correction is performed and the data is output as input.

Memo! One of the J146.151 stores the cells currently being received, and the other stores the cells of the small block whose reception was completed immediately before. [N, N-p] Hamming decoder 1
47.152 performs decoding when the reception of the small block is completed, and stores the corrected small block corresponding to the small block in the memo IJ 148.153.

The N-ary counter 157 counts the number of output cells, and the changeover switches 154 and 156 select the memory 148 or 153 corresponding to the small block currently being output.

When the header identification circuit 159 detects a dummy cell, it sets the changeover switch 160 to the middle position and stops the output from the buffer 162. After that, reception of the small block is completed and N
When the count value of the decimal counter 141 reaches "0", switch the selector switch 160 to the selector switch 156 side,
The corrected cells from memory 148 or 153 are output. At this time, since the position where the output was stopped due to the detection of the dummy cell is stored in the N-ary counter 157, the address generation circuit 155 generates an address based on this value and outputs from the memory 148 or 153. Among the cells stored in the buffer 162, Memo! J14
Cells corresponding to cells output from 8.153 are discarded.

As a result of the above operations, (1) If there is no discarded cell within the small block, the input cell passes through as is. Therefore, the delay time in that case is extremely small.

■ When performing cell discard compensation, buffering is performed from the position of the first dummy cell in a small block, so even when discard compensation is performed, the time order of cells is preserved.

■ If there is a cell discarded in a small block that exceeds the correction capability, it is output as a dummy cell. Therefore, erroneous corrections will not be made.

Effects such as this can be obtained.

As shown in FIG. 9, the intra-large block cell discard compensation circuit performs intra-large block cell discard compensation.
, N-ary counter 173.179 , N-ary counter 17
4.180, address generation circuit 175.184, N×M
Memory for cells 176.183, I:M, M-Q] Hamming decoder 177.181, Memory for NXM cells 1
78.182.2 Human power 1 output selector switch 185.1
86.192, address generation circuit 187, N-ary counter 188, N-ary counter 189, buffer 191.2, human power 21 output changeover switch 190, detects the first dummy cell in the large block and stops cell output. A header identification circuit 194 is provided as a means, and the output of the [NXM)-adc counter 171 is connected to the header identification circuit 194 as a means for restarting cell output after termination of discard compensation.

Additionally, for each column in a large block, there is a means for determining whether discard compensation is possible within the column based on the number of dummy cells in the column, and if this means is determined to be impossible, discard compensation is stopped and cell output is resumed. The means to do this is realized by [M, M-q] Hamming decoders 177 and 181.

In the initial state, CNXMNX counter 171, N-ary counter 173.179.189, N-ary counter 174
．． All values of 180 and 188 are set to "0", changeover switches 172 and 192 are set to the memory 176 side, changeover switches 185 and 186 are set to the memory 178 side, and changeover switch 190 is set to the buffer 191 side.

The cell input from the input terminal 193 is transferred to the selector switch 1.
72.192, buffer 191, and selector switch 190 before being output. If no dummy cell is detected from the manually inputted cells from the input terminal 193 and no discard compensation is performed, the manually inputted cells are output as they are. Therefore, the delay due to signal processing is extremely small.

[NXM] decimal counter 171 counts the number of human cells,
Each time the reception of a large block is completed and the count value becomes "0", the changeover switches 172 and 192 are switched.

The N-ary counter 189 counts the number of cells output from the changeover switch 190, and the N-ary counter 188 counts the number of times the count value of the N-ary counter 189 becomes "0." Therefore, when the output of the large block is completed, the count value of the N-ary counter 188 becomes "0".

The changeover switches 185 and 186 are the N-ary counter 188
The memo IJ is switched every time the count value of becomes "0".
178 and 182, the side that stores cells corresponding to the large block being output is selected.

Memories 176, 183 store copies of cells passing from transfer switch 172 to transfer switch 192.

[M, M-ql Hamming decoder 177.181, the entire large block is a memo! J 176.183 is stored, decoding is performed. At this time, the [M, M-q] Hamming decoder 177.181 counts the number of dummy cells for each column of the large block, and performs correction if it is within its correction capability, or if it exceeds the range. Output as is without doing anything.

The header identification circuit 194 monitors the header of the cell output from the buffer 191 and detects a dummy cell. Further, the header identification circuit 194 controls the selector switch 190 to stop cell output from the buffer 190 when a dummy cell is detected. Cells output during that time are accumulated in the buffer 191.

The reception of that large block ended while cell output was interrupted, and memo! When a corrected cell is generated at 7178.182, the count value of the I''N×M:) base counter 171 becomes "0". In response to this, the header identification circuit 194
switches the selector switch 190 to the selector switch 186 side, and outputs the corrected cell generated to the memory 178 or 182. At the same time, among the cells stored in the buffer 191, the cells corresponding to the corrected cells are discarded.

The position within the large block of the dummy cell detected by the header identification circuit 194 can be calculated from the count value of the M-ary counter 188 and the count value of the N-ary counter 189.

The address generation circuit 187 generates an address from these count values, and outputs a cell corresponding to the detected dummy cell among the cells generated in the memory 178 and 182.

When the output of the large block is completed, the count value of the M-ary counter 188 becomes "0", and the changeover switch 190 is thereby switched to the buffer 191 side.

As a result of the above operations, (1) If no cells are discarded within the large block, the received cells are output as they are, so the delay time is extremely small.

- For each column in a large block, cells are not discarded for columns in which the number of discarded cells exceeds the correction capability range, so erroneous compensation is not performed.

■ When performing cell discard compensation, buffering is performed from the position of the first dummy cell in a large block, so even when discard compensation is performed, the time order of cells is maintained.

- Since cell discard compensation is performed in the column direction, it is possible to compensate for N or more consecutive cell discards.

Effects such as this can be obtained.

〔Effect of the invention〕

As explained above, the cell transmitting/receiving device of the present invention can: ■ compensate for N consecutive cell discards; ■ almost have no signal processing delay on the transmitting side; There is almost no signal processing delay; ■ If cell discard compensation is possible only within a small block, then the signal processing delay is quite small; ■ When compensating for cell discard that cannot be compensated within a small block, the small block Cells before the first cell to which discard compensation is performed in the large block to which it belongs do not need to wait in the buffer (,■
Even if cell discard compensation is performed, the cell time order is preserved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a transmitting side device in a cell transmitting/receiving device according to a first embodiment of the present invention. FIG. 2 is a block diagram of the receiving side device. FIG. 3 is a block diagram of a small block cell discard compensation circuit in the receiving side device. FIG. 4 is a block configuration diagram of a large block intra-cell discard compensation circuit in the receiving side device. FIG. 5 is a configuration diagram of a small block. Figure 6 is a diagram showing the configuration of the large block. FIG. 7 is a block diagram of the transmitting side device in the cell transmitting/receiving device according to the second embodiment of the present invention. FIG. 8 is a block configuration diagram of a small block cell discard compensation circuit in the receiving side device. FIG. 9 is a block configuration diagram of a large block intra-cell discard compensation circuit in the receiving side device. FIG. 10 is a configuration diagram of a small block. FIG. 11 is a configuration diagram of the large block. FIG. 12 is a diagram showing the layout of conventional parity cells. 1.21.31.101.161.193...Input terminal, 2.41.78...Buffer, 3...[N-1
) advance counter, 4... parity cell holding memory, 5
．． 13.35.37.80, 81...addition circuit, 6.
10.14.34.39.40.44.52.71.7
2.73.76.77.110.122.143.14
3.154.156.158.160.172.185
．． 186.190.192...Selector switch, 7.1
02.111.162.191...Buffer, 8...
・Nx [M-1] base counter, 9.15.32.42
．． 53.74.112.119.141.144.14
9.157.173.179.189... N-ary counter, IL 55.57.58.60.64.66.67
．． 69...Selector, 12.36.38.56.65
... Parity cell holding memory, 22-- Cell discard detection and dummy cell insertion circuit, 23... Cell discard compensation circuit in small block, 24... Cell discard compensation circuit in large block, 33.61.70 .79.159.194・
...Header identification circuit, 51.75...[MXN] decimal counter, 54.63...Switch, 59.68...
Correction prohibition flag holding memory, 103...[N-p] base counter, 104.108.114.118.145.
150.155.175.184.187... Address generation circuit, 105.107.115.117.146
．． 148.151.153.176.178.182.
183...Memory, 106...CN, N-p) Hamming encoder, 109...p-adic counter, 113...
[M-q] Base counter, 116... [M, M-q:]
Hamming encoder, 120...Q-ary counter, 121...
・・NX (M-q) base counter, 147.152 ・・
・CN, N-p] Hamming decoder, 171 =-[N×
M) base counter, 174.180.188...M base counter, 177.181... [M, M-ql Hamming decoder. )1＼Frotufu

Claims (1)

[Claims] A cell for transferring a cell from a transmitting device to a receiving device, which is composed of a header section and a data section including N×M order numbers for integers N and M of 1, 2 or more. In the transmitting/receiving device, the transmitting side device is configured such that for each bit position of [N-p] cells, the data portion is [N-p] bits and the check bit is p bits, for an integer p that is greater than or equal to 1 and less than N. a first encoding means for encoding; a means for inserting the output of the first encoding means into p check bit cells to generate p check bit cells; A cell and the p check bit cells constitute one small block, and for an integer q of 1 or more and less than M, the cell positions of [M-q] small blocks are the same N
For each set of cells, the data part for each bit position is [M-q
] a second encoding means that performs systematic encoding with q check bits, and inserting the output of this second encoding means into the corresponding bit positions of q cells of the same set, and means for generating ×N sets of cells, the receiving device decoding the N cells in the small block using logic inverse to the first encoding means to compensate for cell discard within the small block. a first cell discard compensation means for performing cell discard compensation, and a second cell discard compensation means for performing cell discard compensation for a cell having the same cell position within a large block by decoding using an inverse logic to the second encoding means. The first cell discard compensation means includes means for detecting the first dummy cell in the small block and stopping cell output, and means for restarting cell output after the discard compensation ends, The second cell discard compensation means includes a means for detecting the first dummy cell in a large block and stopping cell output, and a means for restarting cell output after the discard compensation is completed. Device.