JPH0325419A - Electrode arrangement of ic chip - Google Patents
Electrode arrangement of ic chipInfo
- Publication number
- JPH0325419A JPH0325419A JP15951789A JP15951789A JPH0325419A JP H0325419 A JPH0325419 A JP H0325419A JP 15951789 A JP15951789 A JP 15951789A JP 15951789 A JP15951789 A JP 15951789A JP H0325419 A JPH0325419 A JP H0325419A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- pads
- output
- pad
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 abstract description 20
- 238000003491 array Methods 0.000 abstract 2
- 239000011521 glass Substances 0.000 description 17
- 239000004973 liquid crystal related substance Substances 0.000 description 17
- 238000000034 method Methods 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000001965 increasing effect Effects 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000012263 liquid product Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000004848 polyfunctional curative Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、ＴＡＢ （テープオートメイティドボンディ
ング）やガラス基板等に実装されるＩＣ（半導体集積回
路）チップの電極配置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrode arrangement of an IC (semiconductor integrated circuit) chip mounted on a TAB (tape automated bonding), a glass substrate, or the like.
アクティブ・マトリックス方式の液晶表示装置を例に挙
げて説明する。この方式の液晶表示装置のスイッチング
素子としては薄膜トランジスタ（ＴＰＴ）が用いられる
。この薄膜トランジスタと画素電極とを画素の一構成要
素とする液晶表示装置は、マトリクス状に複数の画素が
配置された液晶表示パネル（ＬＣＤ）を有する。液晶表
示パネルの各画素は、Ｔ Ｉ” Ｔの邸動配線、すなわ
ち隣接する２本の走査信号線と隣接する２本の映像信号
線との交差領域内に配置されている。走査信号線は、水
平方向に延在し、かつ垂直方向に複数本配置されている
。一方、映像信号線は、走査信号線と交差する垂直方向
に延在し、かつ水平方向に複数本配置されている。An example of an active matrix type liquid crystal display device will be described. A thin film transistor (TPT) is used as a switching element in this type of liquid crystal display device. A liquid crystal display device in which a thin film transistor and a pixel electrode are used as constituent elements of a pixel has a liquid crystal display panel (LCD) in which a plurality of pixels are arranged in a matrix. Each pixel of the liquid crystal display panel is arranged within the intersecting area of the T I "T's moving wiring, that is, two adjacent scanning signal lines and two adjacent video signal lines. The scanning signal line is , extend in the horizontal direction and are arranged in a plurality in the vertical direction.On the other hand, the video signal lines extend in the vertical direction intersecting the scanning signal lines and are arranged in a plurality in the horizontal direction.
液晶表示パネルは、下部透明ガラス基板上に薄膜トラン
ジスタおよび透明画素電極、配向膜等が順次設けられた
下部基板と、上部透明ガラス基板上にカラーフィルタ、
共通透明画素電極、配向膜等が順次設けられた上部基板
と、両基板の各配向膜の間に封入された液晶と、パネル
の周辺部に設けられた該液晶の封止部材とによって構或
される。A liquid crystal display panel includes a lower substrate in which a thin film transistor, a transparent pixel electrode, an alignment film, etc. are sequentially provided on a lower transparent glass substrate, and a color filter and a color filter on an upper transparent glass substrate.
It consists of an upper substrate on which a common transparent pixel electrode, an alignment film, etc. are sequentially provided, a liquid crystal sealed between each alignment film of both substrates, and a sealing member for the liquid crystal provided at the periphery of the panel. be done.
透明画素電極と薄膜トランジスタとは、画素ごとに設け
られている。A transparent pixel electrode and a thin film transistor are provided for each pixel.
液晶表示パネルは例えば、液晶表示パネルを郭動させる
ＩＣチップ（廃動ＩＣチップ）を実装したＴＡＢと、Ｔ
ＡＢを搭載したプリント配線基板（ＰＣＢ）を具備する
。上部ガラス基板の周辺部（上部ガラス基板より寸法の
大きい下部ガラス基板上）に設けられた酩動配線の入力
端子と、ＴＡＢの出力側アウタリードとが異方性導電膜
（面に対して垂直方向には電流が流れるが、水平方向に
は流れない性質を持った膜）によって電気的に接続され
ている．また、ＴＡＢの入力側アウタリードと，液晶表
示装置の外部の信号送出手段に接続されるＰＣＢの出力
端子とが半田付けにより電気的機械的に接続されている
。さらに、能動ＩＣチップの電極とＴＡＢのインナリー
ドとがボンディングされている。For example, the liquid crystal display panel is made of TAB, which is equipped with an IC chip (disposable IC chip) that moves the liquid crystal display panel, and TAB.
It is equipped with a printed wiring board (PCB) on which AB is mounted. The input terminals of the inductive wiring provided on the periphery of the upper glass substrate (on the lower glass substrate, which is larger in size than the upper glass substrate) and the output side outer lead of the TAB are connected to an anisotropic conductive film (perpendicular to the surface They are electrically connected by a membrane that allows current to flow through them, but not in the horizontal direction. Further, the input-side outer lead of the TAB and the output terminal of the PCB, which is connected to an external signal sending means of the liquid crystal display device, are electrically and mechanically connected by soldering. Furthermore, the electrodes of the active IC chip and the inner leads of the TAB are bonded.
また、ＴＡＢを使用せず，ａｉ動ＩＣチップをガラス基
板上に直接実装するいわゆるＣＯＧ （チップオングラ
ス）実装も提案されている。Also, so-called COG (chip-on-glass) mounting has been proposed in which an AI dynamic IC chip is directly mounted on a glass substrate without using TAB.
なお、ＴＰＴを使用したアクティブ・マＩ−リクス液品
表示装置は、例えば「冗！１＋Ｒ成を採用した１２。５
型アクティブ・マトリクス方式カラー液晶ディスプレイ
」、日経エレクトロニクス、１９３〜２１０頁、ｌ９８
６年１２月１５日、日経マグロウヒル社発行、で知られ
ている。In addition, an active matrix liquid product display device using TPT is, for example, "12.
"Active Matrix Color Liquid Crystal Display", Nikkei Electronics, pp. 193-210, l98
It is known for being published by Nikkei McGraw-Hill on December 15, 2006.
第２図は、従来のＴＡＢ実装用あるいはＣＯＧ実装用の
ＩＣチップの電極（パッド）配置の一例を示すＩＣチッ
プの平面図である．ｌはＩＣチップ、２ａ、２ｂはＩＣ
チップ１の出方側接続用パッド（電極、以下出力用バッ
ドと称す），３ａ，３ｂはＩＣチップｌの入力側接続用
パッド（以下入力用パッドと称す）である。工ｃチップ
１は液晶表示装置のモジュール寸法を小さくするため、
細長い長方形状をしている．出力用バッド２ａ、２ｂは
液晶表示パネル側の片側のｌ長辺に沿って配列されてい
る。なお、出力用バッド２ａ、２ｂは２列にｎ ／ ２
個ずつ千鳥配列されているが，これは出力用パッドは数
が多く．ピッチＰ．が小さいので、ＴＡＢのインナリー
ドへの接続やＣＯＧにおけるガラス基板上のパッドへの
ワイヤボンディングがし易いように接続部の面積を増す
対策である．３ａ、３ｂはＩＣＩへの入力信号、電源用
の入力用パッドであり、各々ｍ８個、ｍ２個設けられ、
そのピッチはＰ２である。従って、ＩＣチップｌの長辺
の長さｙは約ｎＸＰエ、短辺の長さＸは約ｍ，ＸＰ，ま
たはｍ，ＸＰ，の大きい方である。FIG. 2 is a plan view of an IC chip showing an example of the electrode (pad) arrangement of an IC chip for conventional TAB mounting or COG mounting. l is an IC chip, 2a and 2b are ICs
Output side connection pads (electrodes, hereinafter referred to as output pads), 3a and 3b of the chip 1 are input side connection pads (hereinafter referred to as input pads) of the IC chip 1. The engineering c-chip 1 is designed to reduce the module size of the liquid crystal display device.
It has an elongated rectangular shape. The output pads 2a and 2b are arranged along one long side on the liquid crystal display panel side. Note that the output pads 2a and 2b are arranged in two rows with n/2
They are arranged in a staggered arrangement, but this means that there are a large number of output pads. Pitch P. Since this is small, the area of the connection part is increased to facilitate connection to the inner lead of TAB and wire bonding to the pad on the glass substrate of COG. 3a and 3b are input pads for input signals to the ICI and power supply, and are provided with m8 pads and m2 pads, respectively.
Its pitch is P2. Therefore, the length y of the long side of the IC chip l is approximately nXP, and the length X of the short side is approximately m, XP, or the larger of m, XP.
しかし、従来は第２図に示すように千鳥配列を用いても
出力用パッド２ａ．２ｂのピッチＰユは７０〜１００μ
ｍと狭いので，ボンディングワイヤ同志のショート、ボ
ンデイングワイヤのオーブン不良（ボンディングワイヤ
の切断、剥離），ＴＡＢのインナーリードの不良（イン
ナーリード同志のショート、ボンディングが不町能）が
生じる確率が多くなる。However, conventionally, as shown in FIG. 2, even if a staggered arrangement is used, the output pads 2a. The pitch of 2b is 70~100μ
Since the width is narrow (m), there is a high probability of short-circuiting between bonding wires, oven failure of bonding wires (bonding wire cutting, peeling), and failure of TAB inner leads (short-circuiting between inner leads, poor bonding). .
本発明の目的は、信頼性の高い接続を可能とするＩＣチ
ップのパッド（電極）配置を提供することにある。An object of the present invention is to provide an IC chip pad (electrode) arrangement that enables highly reliable connections.
上記の課題を解決するために、本発明のＩＣチップのパ
ッド配置は、長方形状をしたＩＣチップの出力用パッド
が上記ＩＣチップの表面上で上記ＩＣチップの２長辺に
沿ってそれぞれ少なくとも１列に配列されていることを
特徴とする。In order to solve the above problems, the pad arrangement of the IC chip of the present invention is such that the output pads of the rectangular IC chip are arranged at least once each on the surface of the IC chip along two long sides of the IC chip. It is characterized by being arranged in columns.
また、本発明のＩＣチップの電極配置は、さらに上記２
長辺においてそれぞれ対応する上記パッド同志が配線で
接続されていることを特徴とする。Further, the electrode arrangement of the IC chip of the present invention is further improved by the above-mentioned 2.
It is characterized in that the pads corresponding to each other on the long sides are connected by wiring.
本発明のＩＣチップのパッド配置は、出力用パッドがＩ
Ｃチップの２長辺に沿って配置されているので，出力用
パッドのピッチを大きくすることができ、高信頼性の接
続を可能とする。The pad arrangement of the IC chip of the present invention is such that the output pad is I
Since the output pads are arranged along the two long sides of the C chip, the pitch of the output pads can be increased, allowing highly reliable connection.
また、２長辺の対応する上記パッド同志を配線で接続す
ることにより、どちらが一方の出力用パッドの接続が切
れても支障がないので、高信頼性の接続ができる。Furthermore, by connecting the corresponding pads on the two long sides with wiring, there is no problem even if one of the output pads is disconnected, so a highly reliable connection can be achieved.
本為硬の他の目的および特徴は図面を参照した以下の説
明から明らかとなるであろう。Other objects and features of this hardener will become apparent from the following description with reference to the drawings.
第３図（ａ）〜（ｃ）は、本発明によるＩＣチップのパ
ッド配置を従来と比較して示すＩＣチップの概略平面図
である。（ｃ）に示す従来のパッド配置では第２図にも
示したようにＩＣチップ１の一方の長辺のみに沿って出
力用バッド２が設けられ，ビッチＰｉが小さく、接続の
信頼性が低下する．（ａ）に示す本発明の第１の例のパ
ッド配置では，出力用パッド２がＩＣチップ１の２つの
長辺に沿って設けられているので、出力配線４の１本置
きの接続が可能であり、出力用パッド２のピッチを２倍
（２Ｐｉ）にすることができる。FIGS. 3(a) to 3(c) are schematic plan views of an IC chip showing a pad arrangement of an IC chip according to the present invention in comparison with a conventional IC chip. In the conventional pad arrangement shown in (c), the output pad 2 is provided along only one long side of the IC chip 1 as shown in FIG. 2, and the pitch Pi is small, reducing the reliability of the connection. do. In the pad arrangement of the first example of the present invention shown in (a), since the output pads 2 are provided along the two long sides of the IC chip 1, it is possible to connect every other output wiring 4. Therefore, the pitch of the output pad 2 can be doubled (2Pi).
（ｂ）に示す本発明の第２の例のパッド配置では，出力
用パッドが２長辺に設けられ（一方は検査用パッドとし
て使用可）、かつ２長辺の対応する出力用パッド同志が
図示しない配線で接続されているので、どちらか一方の
出力用パッドの接続が切れても支障がなく、ピッチはＰ
エと小さくなるが、出力配線４へのボンディングワイヤ
やＴＡＢのインナーリードがオーブンし易い場合は有効
である（この方式を両側リード接続方式と称す）。In the pad arrangement of the second example of the present invention shown in (b), output pads are provided on two long sides (one can be used as an inspection pad), and the corresponding output pads on the two long sides are Since they are connected by wiring not shown, there is no problem even if one of the output pads is disconnected, and the pitch is P.
Although it is smaller in size, it is effective if the bonding wire to the output wiring 4 or the inner lead of the TAB is easily exposed to heat (this method is referred to as the double-side lead connection method).
第１図は、本発明の一実施例のＴＡＢ実装用あるいはＣ
ＯＧ実装用のＩＣチップのパッド配置を示すＩＣチップ
の平面図である．１はＩＣチップ、２ａ．２ｂはＩＣチ
ップ１の出力用パッド、３ａ、３ｂはＩＣチップ１の入
力用パッド，５ａは出力用パッド２ａに接続された出力
用パッド．５ｂは出力用パッド２ｂに接続された出力用
パッド、６は出力用パッド２ａと５ａ、および２ｂと５
ｂを接続するパッド間接続用配線、Ｐ１は出力用バッド
２ａと５ｂのピッチ、２Ｐｉ（２ＸＰ，）は出力用パッ
ド２ａ（あるいは２ｂ）のピッチである。FIG. 1 shows the TAB mounting or C
FIG. 2 is a plan view of an IC chip showing the pad arrangement of an IC chip for OG mounting. 1 is an IC chip, 2a. 2b is an output pad of the IC chip 1, 3a and 3b are input pads of the IC chip 1, and 5a is an output pad connected to the output pad 2a. 5b is an output pad connected to output pad 2b, 6 is output pad 2a and 5a, and 2b and 5.
P1 is the pitch between the output pads 2a and 5b, and 2Pi (2XP,) is the pitch between the output pads 2a (or 2b).
すなわち、本実施例では、ＩＣチップの出力用パッドが
接続されるべき基板上の出力配線（あるいはＴＡＢのイ
ンナーリード）の偶数番目（あるいは奇数番目）に接続
される出力用パッド２ａ、２ｂがＩＣチップ１の表面上
で２長辺に沿って交互にそれぞれ１列に配列されている
。出力用パッドＡａに対応する出力用パッド５ａは２ａ
と反対側の長辺に沿って２ｂの内側に２ｂと千鳥配列さ
れている。出力用パッド２ｂに対応する出力用パッド５
ｂは２ｂと反対側の長辺に沿って２ａの内側に２８と千
鳥配列されている．２長辺において対応する出力用パッ
ド同志、すなわちパッド２ａと５ａ、および２ｂと５ｂ
が配線６によって接続されている。なお，配，１１Ｇは
ＩＣチップ１の表面に形威してもよいし、内部に形成し
てもよい。That is, in this embodiment, the output pads 2a and 2b connected to the even numbered (or odd numbered) output wiring (or TAB inner lead) on the board to which the output pad of the IC chip is connected are connected to the output pads 2a and 2b of the IC chip. They are arranged alternately in one row along the two long sides on the surface of the chip 1. The output pad 5a corresponding to the output pad Aa is 2a.
2b and 2b are arranged in a staggered manner along the long side opposite to 2b. Output pad 5 corresponding to output pad 2b
b is arranged in a staggered manner as 28 inside 2a along the long side opposite to 2b. Corresponding output pads on the two long sides, namely pads 2a and 5a, and pads 2b and 5b
are connected by wiring 6. Note that the wiring 11G may be formed on the surface of the IC chip 1, or may be formed inside.
第４図は、第１図に示した本発明によるＩＣチップをＴ
ＰＴを使用したアクティブ・マトリクス液晶表示装置の
下部透明ガラス基板７上にチップボンディング（ＣＯＧ
実装）した様子を示す平面図である。８は下部透明ガラ
ス基板７上に重ねて設けられた上部透明ガラス基板であ
る。第３図（ａ）の方式を用いる場合は、第１図のＩＣ
チップのパッド２ａ、２ｂが出力配線４の入力用パッド
４ａ、４ｂに接続される。また、第１図の入力用パッド
３ａ、３ｂは各々第４図の入力配線９ａ．９ｂにワイヤ
ボンディングにより接続される。FIG. 4 shows the IC chip according to the present invention shown in FIG.
Chip bonding (COG) is performed on the lower transparent glass substrate 7 of the active matrix liquid crystal display device using PT.
FIG. 8 is an upper transparent glass substrate provided overlappingly on the lower transparent glass substrate 7. When using the method shown in Figure 3(a), the IC shown in Figure 1
Pads 2a and 2b of the chip are connected to input pads 4a and 4b of output wiring 4. Further, the input pads 3a and 3b in FIG. 1 are connected to the input wirings 9a and 9b in FIG. 4, respectively. 9b by wire bonding.
１０ａ、１０ｂは、ｒｃチップ１と下部透明ガラス基板
７の配線４との接続終了後に接続状態やＩＣの不良をチ
ェックするための検査用パッドである。１１は下部透明
ガラス基板７上（ＩＣチップｌの下）に設けられた入力
用パッド４ａと検査用パッド１０ｂ、および４ｂと１０
ａとを接続するパッド間接続用配線、１２は液晶表示装
置の外部の信号送出手段に接続されるＦＰＣで、入力配
線９ａ、９ｂと接続される。10a and 10b are test pads for checking the connection state and IC defects after the connection between the rc chip 1 and the wiring 4 of the lower transparent glass substrate 7 is completed. Reference numeral 11 indicates an input pad 4a and an inspection pad 10b provided on the lower transparent glass substrate 7 (below the IC chip l), and 4b and 10.
An inter-pad connection wiring 12 connecting the pads 1 and 12 is an FPC connected to signal sending means outside the liquid crystal display device, and is connected to the input wirings 9a and 9b.
第５図（ａ）、（ｂ）は、第３図（ｂ）あるいは第１図
で示したパッド配置による両側リード接続方式の特長を
示す図である，（ａ）は平面図、（ｂ）は断面図である
。出力配線４の入力用パッド４ａに接続されたボンデイ
ングワイヤ１ ３ ａが断線しても，パッド１０ａにつ
ながるボンデイングワイヤ１３ｂがあるので、パッド２
ａと５ａとを接続する配線６を通してＩＣ内の出力段と
導通がとれ，冗長性がとれることになる。5(a) and 5(b) are diagrams showing the features of the double-side lead connection method using the pad arrangement shown in FIG. 3(b) or FIG. 1.(a) is a plan view,(b) is a sectional view. Even if the bonding wire 13a connected to the input pad 4a of the output wiring 4 is disconnected, there is a bonding wire 13b connected to the pad 10a, so the pad 2
Conductivity is established with the output stage within the IC through the wiring 6 connecting a and 5a, thereby providing redundancy.
以上本発明の実施例について説明したが、本発明は上記
実施例に限定されるものではなく，その要旨を逸脱しな
い範囲において種々変更可能であることは勿論である。Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and it goes without saying that various changes can be made without departing from the spirit of the invention.
以上説明したように、本発明のＩＣチップのパッド配置
によれば、ＩＣ内のパッド間隔が狭くなっても、出力配
線を土本置きに接続できるので、ピッチが倍となり、裕
度が増し、接続の信頼性を向上できる。また、両側リー
ド接続方式とすることにより、リード切れが心配される
耐環境下でも、冗長設計が可能となり、接続の｛ｉ頼性
が向上する。As explained above, according to the pad arrangement of the IC chip of the present invention, even if the pad spacing within the IC becomes narrow, the output wiring can be connected on a side-by-side basis, thereby doubling the pitch and increasing tolerance. Connection reliability can be improved. Furthermore, by using a double-sided lead connection method, a redundant design is possible even in environments where lead breakage is a concern, and connection reliability is improved.
第上図は、本発明のＩＣチップのパッド配置の一実施例
を示すＩＣチップの平面図、第２図は、従来のＩＣチッ
プのパッド配置の一例を示すＩＣチップの平面図、第３
図（ａ）〜（ｃ）は、本発明によるＩＣチップのパッド
配置を従来法と比較して示すＩＣチップの平面図，第４
図は、本発明によるＩＣチップを液晶表示装置のガラス
基板上にチップボンディングした様子を示す平面図、第
５図（ａ）、（ｂ）は、本発明による両側リード接続方
式の特長を示す図である。
？・・・ＩＣチップ ２ａ、２ｂ・・・出力用パッ
ド３ａ、３ｂ・・・人力用パッド
４・・・出力配線
５ａ、５ｂ・・・出力用パッド
６・・・パッド間接続用配線
７・・・下部透明ガラス基板
８・・・上部透明ガラス基板
４ａ、４ｂ・・・出力配線の入力用パッド９ａ、９ｂ・
・・入力配線
１０ａ、１０ｂ・・・検査用パッド
１１・・・基板上のパッド間接続用配線１ ２・・・Ｆ
ＰＣ
１３ａ、１３ｂ・・・ボンディングワイヤｎ・・・出力
用パッドの数
ｍ■，ｍ２・・・人力用パッドの数
Ｐ１・・・出力用パッドのピッチ
Ｐ２・・・入力用パッドのピッチ
Ｘ・・・ＩＣチップの短辺の長さ
ｙ・・・ＩＣチップの長辺の長さ
第１図
第２ｌｉ
Ｃｎ
Ｎ４
凶
第５図
（Ｑ）
（ｂ）
−−−−−−ＩＣ→りフ゜
２ａ， ５ａ−−−−二ｔニカ目１ノ’．， ｝．４−
−−−一一出力駈』某
＋２−−−−− ＦＰＣThe upper figure is a plan view of an IC chip showing an example of the pad arrangement of an IC chip of the present invention, FIG. 2 is a plan view of an IC chip showing an example of the pad arrangement of a conventional IC chip, and the third
Figures (a) to (c) are plan views of an IC chip showing the pad arrangement of an IC chip according to the present invention in comparison with the conventional method.
The figure is a plan view showing how an IC chip according to the present invention is chip-bonded onto a glass substrate of a liquid crystal display device, and FIGS. 5(a) and 5(b) are diagrams showing the features of the double-sided lead connection method according to the present invention. It is. ? ...IC chip 2a, 2b...Output pad 3a, 3b...Manpower pad 4...Output wiring 5a, 5b...Output pad 6...Wiring for connection between pads 7... - Lower transparent glass substrate 8... Upper transparent glass substrate 4a, 4b... Output wiring input pads 9a, 9b.
...Input wiring 10a, 10b...Inspection pad 11...Wiring for connection between pads on the board 1 2...F
PC 13a, 13b...Bonding wire n...Number of output pads m■, m2...Number of manual pads P1...Output pad pitch P2...Input pad pitch X. ...Length of the short side of the IC chip y...Length of the long side of the IC chip Fig. 1 Fig. 2li Cn N4 Fig. 5 (Q) (b) --------IC → Ref 2a , 5a----Second eye 1 no'. , }． 4-
---11 output cane'' certain +2-----FPC
Claims (1)
記ＩＣチップの表面上で上記ＩＣチップの２長辺に沿っ
てそれぞれ少なくとも１列に配列されていることを特徴
とするＩＣチップの電極配置。 ２、長方形状をしたＩＣチップの出力側接続用電極が上
記ＩＣチップの表面上で上記ＩＣチップの２長辺に沿っ
てそれぞれ少なくとも１列に配列され、かつ上記２長辺
においてそれぞれ対応する上記電極同志が配線で接続さ
れていることを特徴とするＩＣチップの電極配置。[Claims] 1. The output side connection electrodes of a rectangular IC chip are arranged in at least one row on the surface of the IC chip along two long sides of the IC chip. Electrode arrangement of IC chip. 2. The output side connection electrodes of a rectangular IC chip are arranged in at least one row on the surface of the IC chip along two long sides of the IC chip, and the electrodes for connecting the output side of the rectangular IC chip are arranged in at least one row along the two long sides of the IC chip, and An electrode arrangement of an IC chip characterized in that electrodes are connected to each other by wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15951789A JP2760846B2 (en) | 1989-06-23 | 1989-06-23 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15951789A JP2760846B2 (en) | 1989-06-23 | 1989-06-23 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0325419A true JPH0325419A (en) | 1991-02-04 |
| JP2760846B2 JP2760846B2 (en) | 1998-06-04 |
Family
ID=15695501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15951789A Expired - Fee Related JP2760846B2 (en) | 1989-06-23 | 1989-06-23 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2760846B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5473196A (en) * | 1993-02-02 | 1995-12-05 | Matra Marconi Space France | Semiconductor memory component comprising stacked memory modules |
| US5656550A (en) * | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
| KR100243914B1 (en) * | 1997-07-29 | 2000-02-01 | 구본준 | The structure of tap-pad part and its manufacturing method of lcd panel |
| US6025650A (en) * | 1994-08-24 | 2000-02-15 | Fujitsu Limited | Semiconductor device including a frame terminal |
| KR100590429B1 (en) * | 1997-09-29 | 2006-11-30 | 소니 가부시끼 가이샤 | Electronic and Batteries for Electronic Devices |
| US7459779B2 (en) | 2004-11-09 | 2008-12-02 | Samsung Electric Co., Ltd. | Pad arrangement of driver IC chip for LCD and related circuit pattern structure of TAB package |
-
1989
- 1989-06-23 JP JP15951789A patent/JP2760846B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5473196A (en) * | 1993-02-02 | 1995-12-05 | Matra Marconi Space France | Semiconductor memory component comprising stacked memory modules |
| US5656550A (en) * | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
| US6025650A (en) * | 1994-08-24 | 2000-02-15 | Fujitsu Limited | Semiconductor device including a frame terminal |
| KR100243914B1 (en) * | 1997-07-29 | 2000-02-01 | 구본준 | The structure of tap-pad part and its manufacturing method of lcd panel |
| US6281959B1 (en) | 1997-07-29 | 2001-08-28 | Lg Electronics Inc. | Connecting part of outer circuit in liquid crystal display panel and a fabricating method thereof having a pad covered with a transparent conductive layer |
| US6396558B1 (en) | 1997-07-29 | 2002-05-28 | Lg. Philips Lcd Co., Ltd. | Connecting part of outer circuit in liquid crystal display panel and a fabricating method thereof |
| KR100590429B1 (en) * | 1997-09-29 | 2006-11-30 | 소니 가부시끼 가이샤 | Electronic and Batteries for Electronic Devices |
| US7459779B2 (en) | 2004-11-09 | 2008-12-02 | Samsung Electric Co., Ltd. | Pad arrangement of driver IC chip for LCD and related circuit pattern structure of TAB package |
| US7652366B2 (en) | 2004-11-09 | 2010-01-26 | Samsung Electronics Co. Ltd. | Pad arrangement of driver IC chip for LCD and related circuit pattern structure of tab package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2760846B2 (en) | 1998-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5712493A (en) | Display device having driving circuits at the periphery of a substrate | |
| US6300997B1 (en) | Liquid crystal display device having an IC chip mounted on a narrow film wiring board | |
| US5945984A (en) | Display device and method of inspecting same | |
| KR19990025678A (en) | Printed Circuit Board Structure and LCD Module Using Same | |
| KR100293982B1 (en) | LCD panel | |
| JP2002090424A (en) | Matrix array board | |
| JPH0944100A (en) | Display device and ic chip used for the same | |
| JPH0325419A (en) | Electrode arrangement of ic chip | |
| JP2000137445A (en) | Flat display device | |
| JPH04184264A (en) | Method for high density wiring and probe for display panel | |
| JP2872274B2 (en) | Liquid crystal display | |
| JP2000081635A (en) | Liquid crystal display device | |
| JP3254230B2 (en) | LCD Display Panel Wiring Structure | |
| JP3199570B2 (en) | Display device | |
| JPH01130132A (en) | Active matrix substrate | |
| JP2507554B2 (en) | Flat panel display | |
| JPH11305250A (en) | Picture display device | |
| EP0508137A2 (en) | Liquid-crystal display device and process for producing the same | |
| JP2000276073A (en) | Plane display device | |
| KR200301797Y1 (en) | Electrode pad for tab bonding of liquid crystal display module | |
| JPH01152425A (en) | Structure of external fetching terminal | |
| JPH05173164A (en) | Liquid crystal display panel | |
| JPH09113562A (en) | Inspecting method for liquid crystal matrix display panel | |
| JPH08248432A (en) | Packaging structure of display panel | |
| KR100637058B1 (en) | Liquid Crystal Display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |