JPH03252885A - Section displaying system - Google Patents
Section displaying systemInfo
- Publication number
- JPH03252885A JPH03252885A JP5087690A JP5087690A JPH03252885A JP H03252885 A JPH03252885 A JP H03252885A JP 5087690 A JP5087690 A JP 5087690A JP 5087690 A JP5087690 A JP 5087690A JP H03252885 A JPH03252885 A JP H03252885A
- Authority
- JP
- Japan
- Prior art keywords
- pixel
- buffer memory
- outputs
- depth
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005764 inhibitory process Effects 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
Landscapes
- Image Generation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は３次元図形表示装置に関し、特に３次元図形の
切断面の表示方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a three-dimensional graphic display device, and particularly to a method for displaying a cut plane of a three-dimensional graphic.
従来、３次元図形切断面の表示においては、すべての描
画図形と切断平面との交点（交線）をソフトウェアによ
り計算し、図形の切断面によるクリッピングを行なった
後のデータを描画することにより切断面の表示を行なっ
ていた。Conventionally, when displaying a 3D figure cutting plane, the intersection points (intersection lines) between all drawn figures and the cutting plane are calculated by software, and the cutting plane is drawn by drawing the data after clipping with the cutting plane of the figure. It was displaying the surface.
上述した従来の切断面表示方式は描画前にすべての描画
図形の切断面でのクリッピングをソフトウェア的に行な
う必要があり、描画図形が多い場合には処理時間がかか
り表示がおくれるという欠点がある。The conventional cut plane display method described above requires software to perform clipping at the cut plane of all drawn figures before drawing, which has the disadvantage that it takes processing time and the display is delayed when there are many figures to draw. .
本発明の切断面表示方式は、描画すべき３次元図形の各
ピクセルアドレスを計算する描画制御手段と、前記ビク
セルアドレスのうちの２次元アドレスよりそのアドレス
に対応する３次元切断平面上の点の奥行きアドレスを計
重する演算手段と、表示情報を格納するフレームバッフ
ァメモリと、前記フレームバッファメモリ上の各ピクセ
ルの奥行きアドレスを格納するＺバッファメモリと、前
記描画制御手段、演寡手段、及びＺバッファメモリから
出力される奥行きアドレスを比較しその比較結果より前
もって設定された論理に従い描画の許可／禁止の判定を
行なう比較手段と、前記比較手段に判定論理をプログラ
ムより設定する手段とを有し、描画図形を１ピクセル毎
に切断平面との前後奥行き関係により描画／非描画制御
を行なうようにして構成される。The cutting plane display method of the present invention includes a drawing control means that calculates each pixel address of a three-dimensional figure to be drawn, and a point on the three-dimensional cutting plane corresponding to the two-dimensional address of the pixel addresses. arithmetic means for calculating depth addresses, a frame buffer memory for storing display information, a Z buffer memory for storing depth addresses of each pixel on the frame buffer memory, the drawing control means, the rendering means, and the Z buffer memory. Comparing means for comparing depth addresses output from the buffer memory and determining permission/prohibition of drawing based on the comparison result according to logic set in advance, and means for setting determination logic in the comparing means from a program. , the drawing figure is configured to be controlled for drawing/non-drawing for each pixel based on the front-back depth relationship with the cutting plane.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のブロック図である。描画制
御回路１はホストプロセッサより描画図形の座標パラメ
ータを受けとり、描画が必要なピクセル毎にｘ、ｙ、ｚ
の各座標値と描画データを出力する。このうち、Ｘ、Ｙ
は２次元平面上の座標であり２が奥行き座標である。FIG. 1 is a block diagram of one embodiment of the present invention. The drawing control circuit 1 receives the coordinate parameters of the figure to be drawn from the host processor, and calculates x, y, z for each pixel that needs to be drawn.
Output each coordinate value and drawing data. Of these, X, Y
is a coordinate on a two-dimensional plane, and 2 is a depth coordinate.
演算器２は平面方程式Ｚ＝ａｘ＋ｂｙ＋ｃより切断面上
の２値を計算するものであり、ＸとＹを入力しＺｓを出
力する。この時のパラメータａ。The calculator 2 calculates binary values on the cut plane from the plane equation Z=ax+by+c, inputs X and Y, and outputs Zs. Parameter a at this time.
ｂ、ｃはホストプロセッサより与えられる。b and c are given by the host processor.
ＺＢＦ （Ｚバッファメモリ）３は現在ＦＲＢ（フレー
ムバッファメモリ）６上の各ピクセルの奥行き座標が格
納されており、Ｘ、Ｙに対応した位置の奥行きに座標Ｚ
ｏを出力する。The ZBF (Z buffer memory) 3 currently stores the depth coordinates of each pixel on the FRB (frame buffer memory) 6, and the coordinate Z is stored in the depth of the position corresponding to X and Y.
Output o.
論理判定回路４はＺ、Ｚｓ 、Ｚｏ各値の大小判定を行
ない、ホストプロセッサから指定された判定論理に従い
、その描画ピクセルの描画許可／禁止信号を出力する６
例えば、Ｚｓ≦ＺかつｚくＺｏとホストプロセッサより
指定された場合、Ｚが前記論理を満足する場合は描画許
可、それ以外は描画禁止となる。A logic determination circuit 4 determines the magnitude of each value of Z, Zs, and Zo, and outputs a drawing permission/inhibition signal for the drawing pixel according to the judgment logic specified by the host processor 6
For example, when the host processor specifies that Zs≦Z and zxZo, drawing is permitted if Z satisfies the above logic, otherwise drawing is prohibited.
ＦＲＢ制御回路５は論理判定回路４より描画許可信号が
来た場合、ＦＲＢ６に対しＸ、Ｙ座標に対応するメモリ
アドレスと描画制御回路１からの描画データを出力し描
画を行ない、描画禁止信号が来た場合描画を行なわない
、ＦＲＢ６は表示データをビットマツプ形式で格納する
メモリであり、ＦＲＢ６より順次読み出された表示デー
タは表示部７に送られ表示される。When the drawing permission signal is received from the logic judgment circuit 4, the FRB control circuit 5 outputs the memory address corresponding to the X and Y coordinates and the drawing data from the drawing control circuit 1 to the FRB 6, performs drawing, and then receives the drawing prohibition signal. The FRB 6 is a memory that stores display data in bitmap format, and the display data sequentially read from the FRB 6 is sent to the display section 7 and displayed.
上記の切断面表示方式では演算器２を１つ有し１つの切
断面による切断表示処理が可能であるが、演算器２を複
数個有して上記と同様の動作により描画速度をおとすこ
となく複数の切断面による切断表示処理が可能である。The above cutting plane display method has one computing unit 2 and can perform cutting display processing using one cutting plane, but it has multiple computing units 2 and performs the same operation as above without slowing down the drawing speed. Cut display processing using multiple cut planes is possible.
以上説明したように本発明は、描画ピクセルの２次元座
標より切断面上の点のＺ値を毎回計算しその前後関係よ
り描画／非描画を行なうことにより、事前にソフトウェ
アによる切断面クリップ処理が不要となり高速化できる
効果がある。As explained above, the present invention calculates the Z value of a point on the cut plane from the two-dimensional coordinates of the drawing pixel every time, and draws/non-draws based on the context, thereby allowing cutting plane clipping processing by software to be performed in advance. This has the effect of making it unnecessary and speeding up the process.
第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
１・・・描画制御回路、２・−・演算器、３・・・ＺＢ
Ｆ、４・・・論理判定回路、５・・・ＦＲＢ制御回路、
６・・・ＦＲＢ、７・・・表示部。1... Drawing control circuit, 2... Arithmetic unit, 3... ZB
F, 4...Logic judgment circuit, 5...FRB control circuit,
6...FRB, 7...Display section.
Claims (1)
描画制御手段と、前記ピクセルアドレスのうちの２次元
アドレスよりそのアドレスに対応する３次元切断平面上
の点の奥行きアドレスを計算する演算手段と、表示情報
を格納するフレームバッファメモリと、前記フレームバ
ッファメモリ上の各ピクセルの奥行きアドレスを格納す
るＺバッファメモリと、前記描画制御手段、演算手段、
及びＺバッファメモリから出力される奥行きアドレスを
比較しその比較結果より前もって設定された論理に従い
描画の許可／禁止の判定を行なう比較手段と、前記比較
手段に判定論理をプログラムより設定する手段とを有し
、描画図形を１ピクセル毎に切断平面との前後奥行き関
係により描画／非描画制御を行なうことを特徴とする切
断面表示方式。a drawing control means for calculating each pixel address of a three-dimensional figure to be drawn; a calculation means for calculating a depth address of a point on a three-dimensional cutting plane corresponding to the two-dimensional address among the pixel addresses; a frame buffer memory for storing display information, a Z buffer memory for storing depth addresses of each pixel on the frame buffer memory, the drawing control means, the calculation means,
and comparison means for comparing depth addresses output from the Z buffer memory and determining permission/inhibition of drawing according to logic set in advance based on the comparison result, and means for setting determination logic in the comparison means from a program. A cutting plane display method characterized in that drawing/non-drawing of a drawing figure is controlled for each pixel based on the front-back depth relationship with a cutting plane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5087690A JPH03252885A (en) | 1990-03-02 | 1990-03-02 | Section displaying system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5087690A JPH03252885A (en) | 1990-03-02 | 1990-03-02 | Section displaying system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03252885A true JPH03252885A (en) | 1991-11-12 |
Family
ID=12870923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5087690A Pending JPH03252885A (en) | 1990-03-02 | 1990-03-02 | Section displaying system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03252885A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05274446A (en) * | 1991-12-23 | 1993-10-22 | General Electric Co <Ge> | Graphics work station and method for generating three-dimensional graphics picture |
| JPH05282465A (en) * | 1991-12-23 | 1993-10-29 | General Electric Co <Ge> | Graphics work station for handling polygonal model |
| JPH05290174A (en) * | 1991-12-23 | 1993-11-05 | General Electric Co <Ge> | Graphics work station for handling structure of 3-dimensional model and method for generating 3-dimensional graphics picture of structure of model |
-
1990
- 1990-03-02 JP JP5087690A patent/JPH03252885A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05274446A (en) * | 1991-12-23 | 1993-10-22 | General Electric Co <Ge> | Graphics work station and method for generating three-dimensional graphics picture |
| JPH05282465A (en) * | 1991-12-23 | 1993-10-29 | General Electric Co <Ge> | Graphics work station for handling polygonal model |
| JPH05290174A (en) * | 1991-12-23 | 1993-11-05 | General Electric Co <Ge> | Graphics work station for handling structure of 3-dimensional model and method for generating 3-dimensional graphics picture of structure of model |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4924414A (en) | Apparatus and method for obtaining priority numbers for drawing figures forming a display figure | |
| JPH0785290A (en) | Method and equipment for clipping of graphic polygon to clip region | |
| WO2000011562B1 (en) | Apparatus and method for performing setup operations in a 3-d graphics pipeline using unified primitive descriptors | |
| JP2541539B2 (en) | Graphic processing device | |
| EP2548176B1 (en) | Processing of 3d computer graphics data on multiple shading engines | |
| JPH0855239A (en) | Method and apparatus for judgment of visibility of graphicalobject | |
| CN109410213A (en) | Polygon pel method of cutting out, computer readable storage medium, electronic equipment based on bounding box | |
| GB2343601A (en) | Shading and texturing 3-dimensional computer generated images | |
| JPH03252885A (en) | Section displaying system | |
| JP3052839B2 (en) | Image processing apparatus and processing method thereof | |
| JPS60198690A (en) | High-speed graphic processing system | |
| JPS63251870A (en) | Graphic processor | |
| JP3718888B2 (en) | Three-dimensional polygon drawing method and apparatus | |
| JP2001092992A (en) | Three-dimensional shape processing method and recording medium recording program for executing the same | |
| JPH11203486A (en) | Translucent object display method and image display device using the method | |
| JPH10134204A (en) | Graphics display device | |
| TWI478094B (en) | Guard band clipping systems and methods | |
| JP2006048172A (en) | Clip processing system and clip processing method | |
| JPH0740310B2 (en) | Cross-section drawing device | |
| JP2623249B2 (en) | Parallelization of graphic operation processing circuit | |
| CN117453095A (en) | Three-dimensional object selection method, device, medium and equipment | |
| JP2538631B2 (en) | How to handle vector characters | |
| JP2001109911A (en) | Method and device for displaying three-dimensional graphic | |
| JPH04153786A (en) | Quadrilateral area filling device | |
| JPH03209580A (en) | Method and device for drawing graphic |