JPH03250971A - Picture processor - Google Patents

Abstract

PURPOSE:To generate a pattern picture in real time by binarizing an original picture data, applying thickening processing and thinning processing to the binarized data and applying the synthesis processing to the two processings. CONSTITUTION:A picture processing section 102 binarizes a range of a color with respect to a multi-value color resulting from separating the color of a color original. A line memory section 202 stores n-line of the result of the processing by a binarizing processing section 201. A picture processing section 203 applies framing processing to a data in the line direction of n-lines read from a memory 202. Then a coloring processing section 204 forms a pattern picture (framing character + thinning character) based on an output data of the processing processing section 203 and an input picture data to output an output picture data. Thus, the pattern picture is generated in real time with simple constitution without using a frame memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device for digitally performing special processing such as pattern images on characters.

[Conventional technology]

Conventionally, image processing devices such as copying machines process 1;
However, with the adoption of digital processing technology, processing of images and the like is being considered.

This processing includes, for example, edging.

Conventionally, to form a pattern image such as a border image, processing is performed by thinning or thickening the original image.
Specifically, necessary image data is read into the frame memory each time, and arithmetic processing is performed using a CPU (central processing unit).

[Problem to be solved by the invention]

However, in the conventional technology that has been improved, the device configuration becomes large-scale, the circuit configuration becomes complicated, and image processing cannot be performed in real time.

Furthermore, in real-time processing in black-and-white digital copying machines, conventionally only bordering images and shading have been processed.

The present invention has been made in view of the above, and an object of the present invention is to perform pattern image processing in real time with a simple configuration without using a frame memory.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a binarization processing means for binarizing input image data, a line memory for storing data for a plurality of lines by the means, and original image data read from the line memory. An image processing device is provided that includes an image processing section that performs thickening processing and thinning processing on the image, and a coloring processing section that combines the bordered characters and the thinned characters produced by the image processing section. .

[Effect]

In the image processing device according to the present invention, original image data is
After converting it into a value, it is subjected to thickening processing and thinning processing, and a pattern image (bordered characters + thinning characters) is obtained by performing compositing processing of these two processes. This makes it possible to create a pattern image in real time without using a frame memory.

[Examples] Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus according to the present invention, and FIG. 2 is a block diagram showing details of the image processing section 102 in FIG. 1.

In FIG. 1, the image processing apparatus includes an image reading section 101 that optically reads an image of a document or the like and outputs it as an electrical signal, an image processing section 102 that digitally processes the signal from the image reading section 101, and It consists of an image recording section 103 that makes a hard copy of the signal obtained by the image processing section 102 or stores it in a recording medium such as a magnetic disk.

As shown in FIG. 2, the image processing unit 102 includes a binarization processing unit 201 that binarizes the color range of multi-value data obtained by color-separating a color document, and a binarization processing unit 201 that binarizes the color range of multi-valued data obtained by color-separating a color original. A line memory section 202 that stores 9547 minutes, and an image processing section 20 that performs bordering processing on the line direction data of 9547 minutes read from this line memory section 202.
3, and based on the output data and input image data of the image processing unit 203, a pattern image (bordered characters + thinned characters)
The processing unit 20 performs coloring to form the image data and output the output image data.
4.

FIG. 3 shows details of the line memory section 202, including data input terminals I) oi, ~D1oin, and data output terminal D.
0°1~D-1. . 0, read clock terminal RDC
LK, write clock terminal WRCL K.

This is a one-chip IC equipped with a write enable input terminal WE, a read enable input terminal RE, a reset write input terminal RSTW, and a reset read input terminal R3TR.

In addition, in the figure, CLK is a data clock, and LSYN
C is a line synchronization signal.

In the configuration of FIG. 3, 1-bit data input D O
i X and data output D0゜□ as input data D I'i
, n. Input data D Ln using the same operation
- By repeating the process up to 11 inches, the line memory section 2
This means that we have 9547 minutes of output from 02.

Do. , ~D(II-11°), and outputs n+1 bits of data as a FIFO (first-in-first-out) output.

FIG. 4 is a circuit diagram showing details of the image processing section 203.

The FIFO output shown in FIG. 3 includes an OR gate 401,
An AND gate 402 and a shift register 403 are connected. The OR gate 4-01 has a shift register 4
04 is connected to the shift register 404, and an OR gate 405 is connected to the shift register 404.

In addition, an inverter 40 is connected to the output of the shift register 403.
6 is connected to the output of the inverter 406 and the output of the OR gate 405 is connected to a two-man powered computer gamer 407, which outputs the processing result (1).

Furthermore, the AND gate 402 includes a shift register 40
8 is connected to the shift register 408, and an AND gate 409 is connected to the shift register 408 to output the processing result (n).

Each of the shift registers may include, for example, an 8-bit parallel out/serial shift register 5N54164.5N74164 manufactured by Texas Instruments.
．． 5N74LS164 can be used.

In the configuration shown in FIG. 4, the OR gate 401, shift register 404, and OR gate 405 are used to
Perform "thickening processing" as in c). Further, in the shift register 403, as shown in (b), a shift operation is performed on the document (a) to correct the shift caused by the "thickening process".

Furthermore, the AND gate 402, shift register 408, and AND gate 409 convert (
Perform "thinning processing" as in d). Next, the AND gate 407 performs a logical product of the signal obtained by inverting the shift data from the shift register 403 by the inverter 406 and the "fattening process" by the orday 1-405, and (e)
Perform the "hollowing process" as shown below to obtain the processing result (1).

Next, the "thinning processing (i.e., processing result (I)" result) such as Cd obtained by the AND gate 409,
The coloring processing unit 204 combines the "hollowing processing (that is, processing result (■))" result of (e) obtained by the AND gate 407 to obtain the composite image of (f).

Note that the dotted line frame in FIG. 5 indicates the position of the original data, the diagonal line downward to the right indicates color data (I), and the diagonal line downward to the left indicates color data (If) or image data. Furthermore, blank areas indicate areas to be erased.

Furthermore, in Figure 4, nine signals are input to each gate, and "thinning processing" is performed in a 9x9 square pattern.
and "thickening processing", but this can be done arbitrarily.

FIG. 6 is a circuit diagram showing details of the processing section 204 in color.

The CPU (not shown) has a register 601 for erasing, a register 602 for the first specified color, a register 603 for the second specified color, and a register 6 for mode switching.
04 is connected.

Data selector 60 with input image data as input terminal A
The input terminal B of the register 602 is connected to the output terminal of the register 602 . Furthermore, the output of the register 604 is connected to the select terminal S of the data selector 605.

The input terminal A of the data selector 606 is connected to the output terminal Y of the data selector 605, and the input terminal B thereof is connected to the output terminal of the register 603 for the specified color.

Furthermore, the output signal of the AND gate 407 is applied to the select terminal S of the data selector 606 .

A data selector 607 is connected to the output terminal of the register 601.
, its input terminal B is connected to the output terminal Y of the data selector 606, and its select terminal S is connected to the output of the OR gate 608. In the OR gate 608, the processing result (1) is input to one input terminal, and the processing result (n) is input to the other input terminal.

Furthermore, the input terminal B of the data selector 609 is connected to the output terminal Y of the data selector 607, and input image data is applied to the input terminal A thereof.

Further, the output signal of the register 604 is applied to the select terminal of the data selector 609, and output image data is output from the data output terminal Y.

Note that each data selector in FIG. 6 is, for example, IC1SN54157.5N54 manufactured by Texas Instruments.
LS157.5N74157, SN74 LS 157
etc. can be used.

In the configuration of FIG. 6, the register 601,
Each of register 602, register 603, and register 604 is set. Mode switching register 604
uses the color information to select whether the thinning data should be a designated color or input image data, and also selects whether to execute processing.

When execution of a process is selected, the following process is performed depending on the selection.

■ Erase data AND gate 407 output crab (L level) AND gate 409 output crab (L level) ■ ■ ■ First designated color AND gate 407 output crab (L level) AND gate 409 output crab (H level) ) Second specified color AND gate 407 output signal (H level) AND gate 409 output signal (H level) Mode switching register 604 output specified color data image data Ant gate 407 output signal (H level) AND Output signal (H level) of gate 1409 Output image data of mode switching register 604 Also, when no processing is performed, data selector 609 always selects image data. Through the above operations, the composite image shown in FIG. 5(f) can be obtained.

[Effects of the Invention] As is clear from the above, according to the present invention, there is provided a binarization processing means for binarizing input image data, a line memory for storing data for a plurality of lines by the means, and a binarization processing means for binarizing input image data; The present invention includes an image processing section that performs thickening and thinning processing on the original image data read from the memory, and a coloring processing section that combines the bordered characters and thinned characters produced by the image processing section. , without using frame memory,
With a simple configuration, it is possible to create pattern images in real time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an image processing device according to the present invention, FIG. 2 is a block diagram showing details of the image processing section in FIG. 1, and FIG. 3 is a circuit diagram showing details of a line memory section. FIG. 4 is a circuit diagram showing details of the image processing section, FIG. 5 is an explanatory diagram showing the contents of image processing according to the present invention, and FIG. 6 is a circuit diagram showing details of the processing section in color. Explanation of symbols 101--Image reading section 102--Image processing section 103
---Image recording section 201-=Binarization processing section 202--
- Line memory unit 203 - Image processing unit 204 - Coloring processing unit 401.405.608 - OR gate 402.407
,401-and gate 403.404.408...-
Shift register 406...-inverter

Claims (1)

[Scope of Claims] Binarization processing means for binarizing input image data;
a line memory that stores data for a plurality of lines produced by the value conversion processing means; an image processing section that performs thickening processing and thinning processing on the original image data read out from the line memory; and border characters formed by the image processing section. and a coloring processing unit that synthesizes thinned characters.