JPH03250770A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to reduce the use area of a logical element or the like in the case the logical element or the like is formed of FETs by a method wherein a plurality of gate electrodes are formed on the outer periphery of a pillar-shaped body in the peripheral direction of the pillar-shaped body. CONSTITUTION:In a pillar-shaped body 4 with a straight line linking a source region 6 with a drain source 7 as an axis, a channel region is formed and a plurality of gate electrodes G1 to G4 are formed on the outer periphery of the body 4 in the peripheral direction of the body 4. These electrodes G1 to G4 are independently controlled, whereby channels can be independently formed on parts, which oppose to these electrodes G1 to G4, of the outer peripheral surface of the body 4. Thereby, field-effect transistors (FETs) of the number identical with the number of pieces of the electrodes G1 to G4 can be formed on the single body 4. The use area of a logical element or the like can be reduced by constituting the logical element or the like using the plurality of FETs formed on the single body 4 in such a way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and is particularly suitable for field effect transistors (FETs).

[Summary of the invention]

The present invention provides a semiconductor device in which a channel region is formed by a columnar body whose axis is a straight line connecting a source region and a drain region, and a plurality of gate electrodes are formed on the outer periphery of the columnar body in the circumferential direction of the columnar body. .

This makes it possible to reduce the area used when forming logic elements and the like using FETs.

The present invention also provides a semiconductor device in which a channel region is formed by a columnar body whose axis is a straight line connecting a source region and a drain region, and a gate electrode is formed on the outer periphery of the columnar body over the entire circumferential direction of the columnar body. There is. As a result, even when the channel region of the FET is formed of a polycrystalline Si film or the like, the on/off current ratio of the FET can be increased.

[Prior Art] In a semiconductor integrated circuit configured with MOSFETs and MESFETs, circuits such as logic elements are usually configured with planar FETs formed on a semiconductor substrate. In this planar FET, a channel is formed only on the upper or lower surface of the semiconductor forming the channel region. Therefore, when a logic element or the like is constructed using a plurality of FETs, the area of the semiconductor substrate used inevitably becomes large. On the other hand, MOSFET and ME
The easiest way to increase the drain current of an SFET is to increase its channel width, but even when the channel width is increased in this way, the area of the semiconductor substrate used also increases.

In addition, as an example of a three-dimensional structure of MOS FET,
S OI (silicon o
n 1nsulator) structure MOSFET (XM
O3FET) are known (for example, 19
Autumn 1985, Proceedings of the Japan Society of Applied Physics, p. 405). 1st
5, reference numeral 101 denotes a silicon (Si) substrate, 1
02 is a SiO□ film, and 103 is a lower gate electrode.

This lower gate electrode 103 is made of single crystal Si grown by recrystallizing the Si film using the Si substrate 101 as a seed in the opening 102a formed in the 5iOz film 102.
Formed by a membrane. Moreover, this lower gate electrode 103
An n-type polycrystalline St film 105 is formed thereon via a gate 5iOz film 104. At both ends of this p-type child crystal Si film 105, an n'-type source region 106 and a drain region 107 are formed. Further, on this P-type polycrystalline Si film 105, an upper gate electrode 109 is formed with a gate 5iOz film 108 interposed therebetween. code 11
0 indicates the glabella insulating film.

However, in the XMO3FET shown in FIG. 15, by forming an upper gate electrode 109 and a lower gate electrode 103 above and below a p-type child crystalline Si film 105 forming a channel region, the effect of the surrounding electric field on this XMO3FET is In addition to obtaining a shielding effect to prevent
The purpose is merely to suppress the short channel effect in MO3FET.

On the other hand, in a MOS static RAM that uses a p-channel thin film transistor (TPT) as a load transistor of a fully CMO3 type memory cell, in order to prevent an increase in the area of the memory cell, an n-channel In many cases, the above-mentioned p-channel TPT is stacked on the MO3FET. An example is shown in FIG. In FIG. 16, reference numeral 111 indicates an n-type or P-well formed in an n-type Si substrate, 112 indicates a gate 5in2 film, and 113 indicates a gate electrode formed from a polycrystalline Si film. Reference numerals 114 and 115 indicate n-type source and drain regions, respectively. Further, reference numeral 116 indicates a gate 5iOz film, and reference numeral 117 indicates a polycrystalline Si film. Furthermore, reference numerals 118 and 119 indicate, for example, P° type source and drain regions formed in this polycrystalline Si film 117.

Reference numeral 120 indicates an interlayer insulating film such as a phosphosilicate glass (PSG) film.

In the MOS static RAM shown in FIG. 16, the gate electrode 113, the n-type source region 114, and the drain region 115 form an n-channel MO3FET as a driver transistor of the memory cell, and the gate electrode 113 and the p-type A source region 118 and a drain region 119 form a P-channel TPT as a load transistor of the memory cell. In this case, the p-channel TPT is stacked on the n-channel MO3FET with the gate electrode 113 in common.

(Problem to be solved by the invention) As mentioned above, in the past, it has been difficult to configure logic elements, etc.
In order to increase the drain current of the ET, it has been necessary to make the sacrifice of increasing the area of the semiconductor substrate used.

On the other hand, in order to obtain low current consumption and stable data retention ability, the load transistor of the memory cell of the MOS static RA, M has a ratio of the drain current when the load transistor is on to the drain current when the load transistor is off (hereinafter referred to as The on/off current ratio) must be large. However, in the p-channel TPT used as a load transistor of a memory cell in the conventional MOS static RAM shown in FIG. Due to electrical conduction by carriers through grain boundaries in the film 117, the source region 11
8 and the drain region 119 of the MOSFET whose channel region is formed of single-crystal Si.
The disadvantage is that it is larger than . For this reason, it has been difficult to obtain a large on/off current ratio with this p-channel TPT.

Therefore, an object of the present invention is to provide a semiconductor device that can reduce the area used when logic elements and the like are formed using FETs.

Another object of the present invention is to provide a semiconductor device that can increase the on/off current ratio of the FET even when the channel region of the FET is formed of a polycrystalline Si film or the like.

[Means to solve the problem]

To achieve the above object, the present invention provides a semiconductor device in which a channel region is formed by a columnar body (4) whose axis is a straight line connecting a source region (6) and a drain region (7); 4) A plurality of gate electrodes (01-
G,) are formed in the circumferential direction of the columnar body (4).

Further, the present invention provides a source region (6) in a semiconductor device.
) and the drain region (7). A channel region is formed by the columnar body (4) whose axis is a straight line connecting the drain region (7), and a gate electrode (G) is formed on the outer periphery of the columnar body (4) over the entire circumferential direction of the columnar body (4) is formed.

Here, as the columnar body (4), for example, a polygonal column or a cylinder can be used. Examples of polygonal prisms include square prisms such as rectangular parallelepipeds, triangular prisms, and the like.

[Effect]

According to the semiconductor device of the present invention, the channel region is formed by the columnar body (4) whose axis is a straight line connecting the source region (6) and the drain region (7), and the columnar body (4) has a plurality of Since the gate electrodes (01 to 04) are formed in the circumferential direction of the columnar body (4), these multiple gate electrodes (C
By independently controlling the columnar bodies (+~G4), the columnar bodies (
Channels can be formed independently on the outer peripheral surface of 4). Therefore, the gate electrode (
It is possible to form the same number of FETs as the number of FETs (at to Ga). By configuring a logic element or the like using a plurality of FETs formed on this single columnar body (4), the area used can be reduced compared to the conventional method.

Further, according to the semiconductor device of the present invention, the source region (6)
A columnar body (
4), a channel region is formed, and a gate electrode (
By controlling the gate electrode (G), a channel can be formed on the entire outer peripheral surface of the columnar body (4) in the portion facing the gate electrode (G). Therefore, the channel width in this case is columnar (4)
It is possible to obtain a channel width larger than the diameter of the columnar body (4). Therefore, since the drain current during on-time can be increased by an amount corresponding to the increased channel width, the on/off current ratio becomes larger for the same leakage current. As a result, polycrystalline Si
Even when the channel region of the FET is formed of a film or the like, the on/off current ratio of the FET can be increased. However, in this case, an increase in the area used can be suppressed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 are MOSFETs according to a first embodiment of the present invention.
Indicates ET. Here, FIG. 1 shows M according to this first embodiment.
FIG. 2 shows a cross section parallel to the channel length direction of the OSFET, and FIG. 2 shows a cross section perpendicular to the channel length direction of the MOSFET according to the first embodiment. Further, FIG. 3 shows an equivalent circuit of the MOSFET according to the first embodiment.

As shown in FIGS. 1 and 2, in the MOSFET according to the first embodiment, a 5i02 film 2 is formed on a Si substrate 1.
is formed. A rectangular first gate electrode G1 is embedded in this SjO□ film 2. Reference numeral 3 indicates a gate SiO□ film. On this SiOz film 3, an n-type polycrystalline Si film 4 having a rectangular parallelepiped shape, for example, is formed. Here, this n-type child crystal S
The width and thickness of the T film 4 in the direction perpendicular to the channel length direction are:
A first gate electrode C0, a second gate electrode G7, which will be described later.
The size of the space charge region is selected to be sufficiently larger than the size of the space charge region formed inside this n-type child crystalline Si film 4 by the action of the electric field applied by the third gate electrode G3 and the fourth gate electrode G4. .

The SiO□ film 3 is formed not only on the lower surface of the n-type polycrystalline 5illQ4 but also on both sides and the upper surface of this n-type child crystal Si film 4. Then, a second gate electrode G2 is formed on one side surface of the n-type child crystal Si film 4 through this gate SiO□ film 3, and a second gate electrode G2 is formed on the upper surface of the n-type child crystal Si film 4 through this gate SiO third gate electrode G3
is formed, and a fourth gate electrode G4 is formed on the other side of the n-type child crystal Si film 4 via this gate SiO2 film 3. Here, these first gate electrodes GI,
The second gate electrode G2, the third gate electrode G3, and the fourth gate electrode G2.
The gate electrode G4 includes a polycrystalline Si film doped with an impurity such as phosphorus (P), and a polycrystalline Si film doped with phosphorus (P), for example, tungsten silicide (W).
It is formed of a polycide film, a high melting point metal silicide film, a high melting point metal film, etc., which is a layered layer of high melting point metal silicide films such as Siz) film. Note that a 5iOz film 5 is formed on the surfaces of the second gate electrode G2 and the fourth gate electrode G4.

Further, at both ends of the n-type child crystalline Si film 4, for example, a p-type source region 6 and a p-type drain region 7 are formed. and a first gate electrode G, a second gate electrode G
2, the third gate electrode G and the fourth gate electrode G4 and their source region 6 and drain region 7
A p-channel MO3FET with a PT structure is formed.

Note that normally, the source region 6 is grounded, and the drain region 7
Power supply voltage VCC is applied to.

Reference numeral 8 indicates an interlayer insulating film such as a PSG film. Further, CI to C6 indicate contact holes. Then, the electrode 9 contacts the first gate electrode G through the contact hole C1, the electrode 10 contacts the second gate electrode G2 through the contact hole C2, and the electrode contacts the third gate electrode G through the contact hole C3. 1
1 is the contact hole, and the fourth one is connected through the contact hole C4.
The electrode 12 is in contact with the gate electrode G4.

Further, an electrode 13 is in contact with the source region 6 through the contact hole C2, and an electrode 14 is in contact with the drain region 7 through the contact hole C6. These electrodes 9 to 14 are made of aluminum (AI), for example.

Next, M according to this first embodiment configured as described above.
A method for manufacturing an OSFET will be explained.

Here, the first gate electrode GI, the second gate electrode G
2. A case where the third gate electrode G3 and the fourth gate electrode G4 are formed from a polycrystalline Si film will be described.

First, C was placed on a Si substrate (not shown) different from the Si substrate 1.
Polycrystalline sin! by VD method This polycrystalline S
After doping the i film with an impurity such as P to lower its resistance, the polycrystalline Si film is patterned into a predetermined shape by etching to form the first gate electrode G1.

Next, a 5iOz film 2 is formed over the entire surface by CVD.

Note that this 5iOz film 2 can also be formed by a thermal oxidation method. Next, the S on which this 5iOz film 2 was formed
The Si substrate on which this SiO□ film 2 is formed and the Si substrate 1 are bonded together by heat treatment at a high temperature in an oxygen atmosphere, for example, while the i-substrate is brought into close contact with the Si substrate 1 so that the 5iOz film 2 is in contact with the Si substrate 1. Paste together. Thereafter, the Si substrate on which the 5iOz film 2 was first formed is ramped from the back side until the 5in2 film 2 is exposed. As a result, as shown in FIGS. 4 and 5, the Si substrate 1
A structure is formed in which the first gate electrode G is embedded in the Sin film 2 formed above. Here, FIGS. 4 and 5 are cross sections corresponding to FIGS. 1 and 2, respectively. Next, a gate 5ioz film 3 is formed on the entire surface by, for example, the CVD method. Note that this gate 5ioz film 3 can also be formed by a thermal oxidation method. Next, a polycrystalline Si film is formed on the entire surface by the CVD method, and this polycrystalline Si film is doped with, for example, P to make it n-type, and then this n-type polycrystalline S
The t film is patterned by etching to form a rectangular parallelepiped n-type child crystal Si film 4. Next, a gate 5ic)z film 3 is formed on both side surfaces and the top surface of this n-type child crystalline Si film 4 by, for example, thermal oxidation. Next, a polycrystalline Si film 15 is formed over the entire surface by CVD, and then an impurity such as P is doped into the polycrystalline Si film 15 to lower its resistance. Next, this polycrystalline Si film 15 is
A 5iO7 film 5 is formed thereon.

Next, a resist pattern (not shown) having a shape corresponding to the second gate electrode G2 and the fourth gate electrode G4 is formed on this SiO□ film 5, and using this resist pattern as a mask, the SiO□ film is first After etching the 5i02 film 5, the polycrystalline Si film 15 is subsequently etched using the 5i02 film 5 as a mask.

As a result, the second gate electrode G2 and the fourth gate electrode G4 are formed, as shown in FIGS. 6 and 7. Next, the gate Si0g film 3 formed on the upper surface of the n-type child crystal Si film 4 is removed by etching, and the n-type child crystal Si film 4 is etched away.
The top surface of membrane 4 is exposed. Next, after removing the resist pattern, a 1-5iO□ film 3 is again formed on the exposed upper surface of the n-type polycrystalline Si4 by, for example, thermal oxidation.

Next, a polycrystalline Si film (not shown) is applied to the entire surface using the CVD method.
After doping this polycrystalline Si film with an impurity such as P to lower its resistance, a resist pattern (not shown) having a shape corresponding to the third gate electrode G3 is formed on this polycrystalline Si film. ) is formed by lithography. next,
This polycrystalline Si film is etched using this resist pattern as a mask. As a result, the third gate electrode G is formed as shown in FIGS. 1 and 2. After that, for example, using this third gate electrode G3 as a mask, n
By ion-implanting P-type impurities such as boron (B) into the polycrystalline Si film 4, this n-type polycrystalline S
For example, a p-type source region 6 and drain region 7 are formed at both ends of the t-film 4. Next, after forming an interlayer insulating film 8 over the entire surface by CVD, predetermined portions of the interlayer insulating film 8 and the gate 5ioz film 3 are removed by etching to form contact holes C2 to C6. Next, for example, an AI film is formed on the entire surface by sputtering, and this AI film is patterned into a predetermined shape by etching to form the electrodes 9 to 9.
14 to complete the desired MOSFET.

As described above, according to the first embodiment, the first gate electrode G1 and the second gate electrode G2 are formed on the outer peripheral surface parallel to the channel length direction of the n-type child crystal Si film 4 having the shape of a rectangular parallelepiped.
, a third gate electrode G3, and a fourth gate electrode G4 are formed, so that these first gate electrode G1, second gate electrode G2, third gate electrode G3, and fourth gate electrode G4 are formed. By independently controlling the first gate electrode G1, the second gate electrode G2, and the third gate electrode G1,
A channel can be formed independently on the outer circumferential surface of the n-type child crystal Si film 4 in the portion facing the gate electrode G3 and the fourth gate electrode G4. As a result, four p-channel MO3FETs can be formed from a single n-type child crystal Si film 4, so the p-channel MO3FET can be
It is possible to achieve high integration density of ET.

As described above, the first gate electrode Gl, the second gate electrode G2, the third gate electrode G, and the fourth gate electrode G4
By independently controlling these first gate electrode G1, second gate electrode G2, and third gate electrode G3.
The drain current 1di can be changed stepwise as shown in FIG. 8 according to the number of turned-on fourth gate electrodes G4. , it can be used as a current-type multi-value element as it is.

As shown in FIG. 9, a MOSFET with a parallel multiple gate electrode structure according to the first embodiment is used as a current type multi-value element.
A four-man power NAND element can be formed by combining this with normal n-channel MO3FETs Q, ~Q4. In FIG. 9, the portion surrounded by a broken line corresponds to the MOSFET according to the first embodiment. In addition, INI~IN
4 indicates the input of this 4-person NAND element, and OUT indicates the output of this 4-person NAND element.

The four-man power NAND device shown in FIG. 9 has the following advantages. That is, normal P channel MOS
When forming such a 4-man NAND device using FETs and n-channel MOS FETs, a total of 8 FETs, 4 P-channel MO3FETs and 4 n-channel MOS FETs, are required. This ninth
In the case of the four-power NAND device shown in the figure, four p-channel MO3FETs are formed in a single n-type child crystal Si film 4, so in terms of the area used, the area is equivalent to practically five FETs. A NAND device can be formed by four people alone. Therefore, it is possible to increase the integration density of the four-man power NAND element accordingly.

Note that the above-mentioned first gate electrode GI, second gate electrode G2, third gate electrode G, and fourth gate electrode G4
are electrically connected to each other, or these first gate electrode G2, second gate electrode G2, and third gate electrode G3
If the gate electrode G4 and the fourth gate electrode G4 are controlled by the same signal, a normal MOSFET can be used for the same usage area.
The drain current 14s is, for example, several times larger than M
OSFET can be realized.

Next, a second embodiment of the present invention will be described.

FIGS. 10 and 11 show an MO according to a second embodiment of the present invention.
Indicates S FET. Here, FIG. 10 shows a cross section parallel to the channel length direction of the MOSFET according to the second embodiment.
FIG. 11 shows a cross section perpendicular to the channel length direction of the MOSFET according to the second embodiment.

As shown in FIGS. 10 and 11, in the MOSFET according to the second embodiment, n
A gate electrode G is formed on the outer circumferential surface of the molded crystal Si film 4 parallel to the channel length direction over the entire circumferential direction. In this case, the gate electrode G consists of a portion buried in the SiO□ film 2 and a portion formed on both side surfaces and the top surface of the n-type child crystal Si film 4.

According to this second embodiment, by controlling the gate electrode G, a channel can be formed on the entire outer peripheral surface of the n-type child crystal Si film 4 in the portion facing the gate electrode G. This makes it possible to use normal MO for the same area of use.
Drain current Id compared to SFET! For example, it is possible to realize a MOSFET that is several times larger.

Next, a third embodiment of the present invention will be described.

This third embodiment is an embodiment in which the present invention is applied to a MOS static RAM using completely CMO3 type memory cells.

FIGS. 12 and 13 show an MO according to a third embodiment of the present invention.
S static RAM is shown. Here, FIG. 2 shows a cross section parallel to the channel length direction, and FIG. 11 shows a cross section perpendicular to the channel length direction.

As shown in FIGS. 12 and 13, in this third embodiment, a field insulating film 22 such as a 5in2 film is formed on the surface of a p-well 21 formed on a p-type or n-type Si substrate, for example. This provides isolation between elements. Reference numeral 23 indicates a P'' type channel stop region, for example.

A gate S+Oz film 24 is formed on the surface of the active region surrounded by the field insulating film 22.

G indicates a gate electrode. Reference numerals 25 and 26 indicate, for example, an n-type source region and drain region, which are formed in the p-process 21 in a self-aligned manner with respect to the gate electrode G, respectively. These gate 'H pole G, r+° type source region 25 and drain region 26 form an n-channel MO3FE as a driver transistor of the memory cell.
A T is formed. On the other hand, code 27 is the gate sio□
The film 28 indicates a polycrystalline St film. In this case, the gate electrode G is formed on the outer peripheral surface of the polycrystalline Si film 28 over the entire circumferential direction. This polycrystalline Si film 28 includes, for example, a P1 type source region 29 and a drain region 3.
0 is formed. The gate electrode G, p'' type source region 29 and drain region 30 form a p-channel MO3FET as a load transistor of the memory cell.
is formed.

That is, in this case, the gate electrode G is a common gate electrode for these n-channel MO3FET and p-channel MO3FET.

As described above, according to the third embodiment, a P-channel MO3FET having a structure in which a gate electrode G is formed on the outer peripheral surface of a polycrystalline Si film 28 over the entire circumferential direction is used as a load transistor of a memory cell. Therefore, this p
Since the drain current when the channel MO3FET is on can be increased, the on/off current ratio can be increased for the same leakage current. As a result, current consumption can be reduced and stable data retention capability can be obtained.

Furthermore, since this P-channel MO3FET has an offset gate structure in which the gate electrode G is formed offset from the drain region 30, the channel resistance when off is increased, and accordingly, the source region 29 and drain region 30 are separated from each other when off. It is possible to reduce leakage current flowing between the two. Due to this and the large on/off current ratio as described above, when the p-channel MO3FET as a load transistor of the memory cell is turned on, sufficient current supply capability is ensured for the memory cell, while when it is turned off, the p-channel MO3FET is The leakage current can be reduced.

Note that the width and thickness in the direction perpendicular to the channel length direction of the polycrystalline Si film 28 forming the channel region of the p-channel MO3FET are changed inside the polycrystalline Si film 28 by the action of the electric field applied by the gate electrode G. If the size is the same as or smaller than the space charge region to be formed, it becomes possible to control the entire area inside the polycrystalline St film 28 by the electric field applied by this gate electrode G. , it becomes possible to obtain an even larger on/off current ratio.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-mentioned embodiments (various modifications based on the technical idea of the present invention are possible).

For example, the first gate electrode G in the first embodiment described above
, and the lower part of the gate electrode G in the second embodiment do not necessarily have to be embedded in the Si film 2, and may simply be formed on this SiO□lW2.

Further, in the second embodiment described above, the gate electrode G formed over the entire circumferential direction of the n-type child crystal Si film 4 is
s+o, JI! 2 and the part embedded in n-type polycrystalline 5
1M4, and as shown in FIG.
It is also possible to form it integrally over the entire circumferential direction of the mold crystal Si film 4.

Further, in the first, second and third embodiments described above, the case where the present invention is applied to a p-channel MO3FET formed of a polycrystalline Si film is explained, but the present invention
n-channel MO3FET formed from polycrystalline Si film
It is also possible to apply it to Furthermore, these p-channel MO3FET and n-channel MO3FET can also be formed from a single crystal Si film, an amorphous Si film, or the like.

Furthermore, the present invention provides an MES in which a channel region is formed of a compound semiconductor such as gallium arsenide (GaAs).
It is also possible to apply it to FET.

For example, in the case of GaAsMESFET,
Forming a plurality of Schittky gate electrodes in the circumferential direction on the outer peripheral surface of GaAs having a rectangular parallelepiped shape formed on a semi-insulating GaAs substrate, or forming a single Schottky gate electrode over the entire circumferential direction. It is possible to create a structure with

〔Effect of the invention〕

As described above, according to the present invention, a channel region is formed by a columnar body whose axis is a straight line connecting a source region and a drain region, and a plurality of gate electrodes are formed on the outer periphery of the columnar body in the circumferential direction of the columnar body. Therefore, the area used when forming a logic element or the like using an FET can be reduced.

In addition, a channel region is formed by a columnar body whose axis is a straight line connecting the source region and drain region, and a gate electrode is formed on the outer periphery of the columnar body over the entire circumferential direction of the columnar body. Even when the channel region of the FET is formed using the above method, the on/off current ratio of the FET can be increased.

[Brief explanation of drawings]

1 and 2 are MOSFETs according to a first embodiment of the present invention.
A cross-sectional view showing the ET, FIG. 3 is the M shown in FIGS. 1 and 2.
A circuit diagram showing an equivalent circuit of an OSFET, FIGS. 4 to 7 are cross-sectional views for explaining the manufacturing method of the MOSFET shown in FIGS. 1 and 2, and FIG. Show M
A graph showing the characteristics of an OSFET, FIG. 9 is a circuit diagram showing a configuration example of a logic element using the MOSFET shown in FIGS. 1 and 2, and FIGS. 10 and 11 are according to a second embodiment of the present invention. 12 and 13 are cross-sectional views showing a MOS static RAM according to a third embodiment of the present invention; FIG. 14 is a cross-sectional view showing another configuration example of the MOSFET; and FIG. 15 is a cross-sectional view showing a MOSFET. is a cross-sectional view showing a conventional XMO3FET, and Fig. 16 is a conventional MOS static RA.
It is a sectional view showing M. Explanation of main symbols in the drawings 1: Si substrate, 2: SjO□ film, 3°Sin□ film, 4: N-type polycrystalline Si film, 9: Source region, 7
, 30: Dray 28: Polycrystalline Si film, G, ~G, ,G
:27:Gain region, Ga[・electrode. 1゛芙'lQ1row(+Yaolshilong5Khihiparallelf'r
, fi) Fig. 1 Heron 1° fi 4 h 1 row (+ ~ Kill length right side and fully straight tA plane) Fig. 2 Equivalent 1 angle on 7...ru η-to tJ-1 > ri 1 芙 5a noble work Village 1 (
Winter of J.] 9 Kuitago Figure 9 g Construction J (÷ Yarnel long Zai simple Hi parallel t stamp face) t 51 Wa person (+ Yakarushi Nagako Ichi straight R face) t ) Seon Zaita (+Yanel Naga Right Ai Hi Hitake Na l Shii) Tube 2・I′朕L I Row (+Ya 1 Lu Cho Sa Moe and + Takena ttrh>Shu 2 Guestbetsu L1 Row (+- f-net
Nagazai f bow! JLQf汀1) v3゛【Wandering 5 i row (+Yanel long na f''Hikozai1 na M)Fig.
)Fig.

Claims (4)

[Claims] (1) A channel region is formed by a columnar body whose axis is a straight line connecting the source region and the drain region, and a plurality of gate electrodes are formed on the outer periphery of the columnar body in the circumferential direction of the columnar body. semiconductor device. (2) A channel region is formed by a columnar body whose axis is a straight line connecting the source region and the drain region, and a gate electrode is formed on the outer periphery of the columnar body over the entire circumferential direction of the columnar body. semiconductor devices. (3) The semiconductor device according to claim 1, wherein the columnar body is a rectangular parallelepiped, and the gate electrode is formed on each of four side surfaces around the axis of the rectangular parallelepiped. (4) The semiconductor device according to claim 2, wherein the columnar body is a rectangular parallelepiped, and the gate electrode is formed on four side surfaces around the axis of the rectangular parallelepiped.