JPH03250324A - Data processing system, integer/floating point data converter, and floating point/integer data converter - Google Patents

Abstract

PURPOSE:To attain the fast working of both an integer-only processor and a floating point-only processor by providing the integer/floating point data converter and a floating point/integer data converter to the data transfer paths of both processors. CONSTITUTION:An integer-only processor 11 and a floating point-only processor 12 are connected to each other via a bidirectional conversion means 20 for both integer and floating data. Thus both processors are not required to perform the conversion processing for data expression forms of both processors 11 and 12. Therefore both processors can spare the time for execution of other arithmetic operations and ensure the fast working performance. In addition, both processors 11 and 12 are not required to program the conversion processing instructions and can simplify their program production tasks since the necessary conversion processing can be carried out with both processors just by designating the data transfer destinations.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system, and particularly to a data processing system in which a processor that handles integer data and a processor that handles floating point data coexist.

[Conventional technology]

In order to have a processor that handles integer data handle floating point data, it is necessary to convert the floating point data into an integer data representation format.

Conversely, the same applies when a processor that handles floating point data is made to handle integer data. Such expression format conversion processing includes means for processing using software and means for processing using hardware. Conventionally, processing using software has been widely adopted because it simplifies the hardware configuration.

However, since software processing takes time to execute, there is a problem in that it hinders speeding up the overall data processing.

Therefore, a hardware-based data representation format conversion means has been proposed as described in Japanese Patent Application Laid-Open No. 63-223825. This is a data-driven processing device equipped with means for converting integer data into floating point data.

[The problem that the invention attempts to solve]

However, in the prior art of the above-mentioned publication, in other words, in a data-driven processing device, one processor handles multiple data expression formats, so the data format conversion means included in the processor means is A means of determining the expression format is required. Therefore, there is a problem that the configuration of the data format conversion means becomes complicated.

Further, although the data-driven processing device has the advantage of being able to handle both integer and floating point data, it may be advantageous to specify a data representation format that is exclusively handled by each processor from the system configuration perspective. In conventional data processing systems such as this, where integer-only processors and floating-point processors coexist, there was no means for an independent hardware configuration to convert these data representation formats, so processing was performed by each processor. In the current situation where the processing speed of floating point operations has improved and is approaching the processing speed of integer operations, there is a problem that the proportion of time occupied by the conversion processing becomes relatively large. Furthermore, it is necessary to insert into the program an instruction for instructing the execution of data representation format conversion, resulting in a problem that the program length becomes long.

An object of the present invention is to provide a data processing system in which a processor dedicated to integer numbers and a processor dedicated to floating point numbers coexist.
It is an object of the present invention to provide a data processing system that can improve the computing power of each processor by eliminating the load on each processor related to data representation format (integer-floating ordinal point) conversion.

[Means to solve the problem]

In order to achieve the above object, the present invention connects an integer-only processor and a floating-point processor through a bidirectional conversion means for integer/floating-point data.

[Effect]

With this configuration, according to the present invention, the above object is achieved through the following actions.

That is, since a bidirectional conversion means for integer/floating point data is provided, each processor does not need to perform conversion processing of data representation formats, and can perform arithmetic processing of values accordingly, thereby enabling high-speed processing. Further, since each processor performs the necessary conversion processing simply by specifying the data transfer destination, there is no need to program conversion processing instructions, which simplifies the program creation work.

〔Example〕

Hereinafter, the present invention will be explained based on examples.

FIG. 1 shows an overall configuration diagram of an embodiment of a data processing system to which the present invention is applied. Data representation formats handled by this system include signed integers, unsigned integers,
Data includes floating point real numbers, characters, etc., and includes data with different data lengths, but only the parts related to integer and floating point data will be explained here.

As shown in FIG. 1, the processors include an integer-only processor (eprocessor) 11 and a floating IJX several-point processor (F processor) 12. These processors 11 and 12 each have an integer (I) data bus 13.
and a floating point (F) data bus 14.

Further, an integer (I) register 15 and a floating point (F) register 16 are connected to these data buses 13 and 14, respectively. ■The data bus 13 and the F data bus 14 are connected by an I/F conversion device 17 having a hardware configuration that converts integer data into floating point data, and an F/I conversion device 18 having a hardware configuration that performs the reverse conversion. connected.

In the data processing system configured as described above, integer data is stored in the I register 15 and processed by the processor 11. Also, floating point data is stored in the F register 16.
and processed by the F processor 12. When data on the F data bus 14 is processed by the eprocessor 11, the F/I conversion device 18 converts floating point data into integer data. Also, when data on the data bus 13 is processed by the F processor 12, the I/F exchange device 17 converts integer data into floating point data.

Furthermore, in the system of this embodiment, (1) the processor 11 and the F processor 12 do not need to have a special instruction for converting the data representation format, and each processor 11 and 12 has a register 15 or 16 for storing the operation result. By specifying this, data is converted according to the data representation format of the specified register. That is, each processor 11, 12 is configured to transfer data via each register 15, 16, and is connected to a different data bus 13 and 1.
When data is transferred between the four, it is always done via one of the conversion devices 17 or 18. Therefore, programming of each processor 11 and 12 becomes simple. This will be explained using FIG. 2.

The programs shown in FIGS. 2(a) and (b) both add the integer data stored in the integer register r1 and the floating point data stored in the floating point register f1, and calculate the operation result. It is stored in the floating point register f1.

FIG. 4(a) shows the case where the software-based conventional technology is used, and FIG. As can be seen from these figures, according to this embodiment, an instruction (mov r
l, f2) becomes unnecessary, and the register f2 for storing intermediate calculation results can be omitted. Therefore, in the data processing system according to the present embodiment, the program length can be shortened compared to the conventional system, and the frequency of register occupancy is reduced, thereby improving utilization efficiency.

FIG. 3 shows an internal configuration diagram of the I/F conversion device 17 that converts signed 32-bit integer data into double precision floating point data. As shown in the figure, an absolute value converter 40, a digit number encoder 41, a shifter 42 . It consists of (0) decider 43, (1) decider 44, (0) generator 45, hexadecimal integer (IF) generator 46, hexadecimal integer (20) generator 47, and multiplexer 48°49.

Figure 4(a) shows the representation format of data handled by this device.
Shown in (b). The 31st bit of integer data 121 is a sign bit. Furthermore, the Oth to 51st bits of the floating point data 122 are the mantissa part f, the 52nd to 62nd bits are the exponent part e, and the 63rd bit is the sign bit, and the real number represented is -IS×1. fX2e″1023. The most significant bit “1” of the short mantissa is omitted.

However, when e=o and f=o, it means rQJ. This is a format defined by the IEEE (IEEE).

The input integer data is 32-bit data, and is first converted into an absolute value by an absolute value converter 40. That is, when the sign bit (31st bit) is positive LLO11, the contents of the Oth bit to the 30th bit are output as they are to the digit number encoder 41, and the contents of the Oth bit to the 29th bit are output to the shifter 42. When it is negative 11117, it is converted into the complement of the contents of the Oth bit to the 30th bit and outputted. Further, the sign bit of the input integer data is output as the sign bit (63rd bit) of the output floating point data. (0) The determiner 43 determines whether the content of the input integer data is equal to (0) or not, and when equal to (0), outputs sr 1 n to the P terminals of the multiplexers 48 and 49. (1) The determiner W44 determines whether the content of the input integer data is (1) or not, and when it is (1), 111 II
, otherwise di OII to multiplexer 4
Output to q terminals of 8 and 49.

The digit number encoder 41 outputs digit number data (N-2) obtained by subtracting 2 from the actual number of digits N of the input integer data value as an exponent part e to the W terminal of the multiplexer 49, and also outputs it to the shifter 42. Output. The shifter 42 shifts the input 30 bits of data by (30 bits - number of digits data) = (30 - (N - 2)), discards that bit data and uses it as the mantissa part f to convert the floating point data. It outputs from the 22nd bit to the 51st bit. (0) The generator 45 outputs a signal in which all bits are lI OII, and the Oth to 22nd bits of floating point data
Outputs KIO71 to the bit. This means that when converting 32-bit integer data to floating point data, the floating point data's Oth bit to 21st bit are always 1.
This is because it becomes 1071.

Further, the floating point data is outputted to the U terminals of multiplexers 48 and 49 as data of the 57th bit to the 62nd bit and the 52nd bit to the 56th bit. (1) The generator 46 outputs a signal of 5 bits, all of which are 111 II, to the W of the multiplexers 48 and 49. (2o)
The generator 47 has bit data contents of “l, O, O, O,
O, O'' signals are output to the V terminal of the multiplexer 48.The multiplexers 48 and 49 output the output y expressed by the following logical formula according to the P+ q terminal and the contents of the input vectors U, V, and W. Output each.

Note that there are two components of the vector: 0" or "1".

y=pqu+pqv+pqw The operation of the I/F conversion device 17 configured as described above will be explained. When the value of input integer data is (0), (0) determiner 43 to 1 (I II is multiplexer 48 and 49
is input to the p terminal of This allows multiplexer 48
and the contents of the 49 beam terminal, that is, all bits are 1゛o′″
signals from the 57th bit to the 62nd bit of the floating point data.
bit and rr Ot from 52nd bit to 56th bit
Output r. As a result, when the input integer data is (0), the bit (52nd
to 62nd bit) becomes I/OII. On the other hand, the contents of the mantissa part f (22nd bit to 51st bit) are all bits IIO# because the output of the shifter 42 is all bits 110''.

Next, when the value of the input integer data is (1), (1) the output of the determiner 44 becomes 41111, which is input to the q terminals of the multiplexers 48 and 49.

When It I II is input to the q terminals of the multiplexers 48 and 49, all the bit signals input from the (IF) generator 46 are It I II, and output them from the 52nd bit to the 61st bit of the floating point data. do.

That is, the exponent part e is set to (1023).

In addition, since all bits of the output of the shifter 42 are 0'', the mantissa part f of the output floating point data is II Ojj
become.

Next, a case where the value of input integer data is an integer of two or more digits will be explained. The input integer is converted into an absolute value by an absolute value converter 40 and then input to a shifter 42 and a digit number encoder 41. The number of digits encoder 41 is the input 3
A number obtained by subtracting 2 from the number of digits N of a 1-bit integer is given to the multiplexer 49. At this time, the multiplexer 49 inputs 1 from the 52nd bit to the 56th bit of the output floating or several point data.
The output of the digit number encoder 41 is output. Also, at this time, the multiplexer 48 outputs the value of the (20) generator 47, so the 62nd bit of the output floating point data is
" is output, and 0" is output from the 57th to 61st bits. As a result, the exponent part e of the floating point data corresponding to the output of the absolute value converter 40 is generated. The mantissa part f is generated by the output of the shifter 42. In other words, the data of the Oth to 29th bits of the input integer data is shifted to the left by (N-2) bits, thereby starting from the high-order digit (N-2).
The bits are discarded and the remainder is output as the mantissa part f.

Figure 5 shows F for converting floating point data to integer data.
2 is an internal configuration diagram of the /I conversion device 18. FIG.

Data in which il 171 is concatenated with the 21st to 51st bits of the floating point data is provided to the shifter 61. What is the reason for concatenating “1” here?

The most significant “1” in the mantissa, which was omitted in floating-point representation,
The 52nd to 62nd bits of the floating point data are given to the exponent encoder 62. The exponent encoder 62 is used to control the shifter 61. Depending on the combination, the number of digits represented by the exponent part is 1IIF.
51. ．． 21 is set in the approximate value converter 63. The approximate value converter 63 performs processing such as rounding down, rounding up, and rounding off the input data, and outputs the results to the complement converter 64. The complement converter 64 converts the data given when the sign bit (63rd bit) of the floating point data is tt117 "negative" into a complement. Note that the sign bit of the floating point number is used as it is as the sign bit of the output integer data.

As described above, according to the embodiment of FIG. 1, in a data processing system in which integer-only processors and floating-point-only processors coexist, these two types of processors are connected to registers of the same representation format via data buses. When connecting the data bus through the hardware configuration I/F conversion device and F/I conversion device, and transferring data from one processor to the other processor, the data representation format of the other processor is Since data is transferred to the register via a conversion device that performs the corresponding conversion, each processor does not need to perform conversion processing between integer and floating point data. This reduces the load on each processor, speeds up other processing, and eliminates the need for the processors to provide dedicated instructions for conversion processing, making it easier to create programs.

FIG. 6 shows another embodiment of the invention. This embodiment is an example in which a register 15 connected to an internal bus 21 in integer data format is used in a system in which one processor 11 and an F processor 12 share, and the external bus 22 is in floating point data format.

As shown in the figure, the processor 11 is connected to an external bus 22 via a bidirectional integer/floating point data converter 20, and the F processor 12 is connected via a similar 1/F data converter 20. connected to an internal bus.

The I/F data conversion device 20 has a configuration including both the I/F data conversion device and the F/I data conversion device shown in FIGS. 3 and 5 described above. According to this embodiment, (1) the I/F conversion device 20 acts as an I/F conversion device in response to a command to output data from the processor 11 to the external bus 22; When transferred (or captured), it acts as an F/I data conversion device. The same applies to the F data conversion device 20 related to the F processor 12.

According to this embodiment, the data representation format of the internal bus 70 can be unified to integers, whereas the hardware configuration
F processor 73 simply via F data converter 76
can be combined.

FIG. 7 shows a configuration diagram of another embodiment of the present invention.

This embodiment is similar to the embodiment shown in FIG.
The data representation format is unified to floating point,
Further, the data representation format of the external bus 24 may be either integer or floating point.

Note that the register 16 is of floating point format.

FIG. 8 shows a configuration diagram of another embodiment of the present invention.

The feature of this embodiment is that the data stored in register 25 and F register 26 are shared via I/F data conversion device 17 and F/I data conversion device 18.

That is, when the (1) processor 11 writes data to the (2) register 25, data is simultaneously written to the F register 26 via the I/F data conversion device 17. Also, F
When the processor 12 writes data to the F register 26, the data is simultaneously written to the I register 25 via the F/I data conversion device 18. As a result, I/
Even while the F data conversion device 17 is writing data to the F register 26, the F processor 12 can execute processing using another F register 16.

Next, FIG. 9 shows an embodiment in which the system described in FIG. 7 is applied to an electronic computer system having a display device 28.

According to this embodiment, ■ processor 11 and F processor 1
By increasing the processing speed of the system No. 2, it is possible to cause the display device W2B to perform high-speed display.

Note that the reference numeral 27 indicates a memory. Furthermore, if a printer 29 is used in place of the display device 28, as shown in FIG. 10, high-speed printing can be performed.

〔Effect of the invention〕

As explained above, the present invention has the following effects.

In a data processing system that includes a mixture of integer-only processors and floating-point processors, bidirectional conversion means for integer and floating-point data is provided in the data transfer path between the two, allowing each processor to perform data representation format conversion processing. This eliminates the need to perform arithmetic operations on the public domain, enabling high-speed processing. Further, since each processor performs the necessary conversion processing simply by specifying the data transfer destination, there is no need to program conversion processing instructions, which simplifies the program creation work.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram of an embodiment of the present invention, Fig. 2 is a diagram showing an example of a program of the embodiment of Fig. 1, and Fig. 3 is a detailed configuration of the I/F converter of the embodiment of Fig. 1. 4 is a data frame configuration diagram of integer data and floating point data, FIG. 5 is a detailed configuration diagram of the F/I converter of the embodiment shown in FIG. 1, and FIG.
10 through 10 are system configuration diagrams of other embodiments of the present invention. 11...Integer-only processor (1) processor, 12
...Floating point dedicated (F) processor. 15... Integer (I) register, 16... Floating point (F) register, 17... Integer/floating point data (I/F) converter,
18...Floating point/integer data (F/I) converter, 2
0: Integer/floating point data bidirectional converter.

Claims (1)

[Scope of Claims] 1. A data processing system in which an integer-only processor and a floating-point processor are connected via bidirectional conversion means for integer/floating-point data. 2. an integer-only processor; a first storage means connected to the integer-only processor via a first data bus;
a floating point dedicated processor; a second storage means connected to the floating point dedicated processor via a second data bus; an integer/floating point data conversion means for outputting onto the second data bus; and a floating point/integer data conversion means for converting the floating point data on the second data bus into integer data and outputting the converted data onto the first data bus. A data processing system comprising means. 3. An integer-dedicated processor, a floating-point-dedicated processor, a data bus to which the floating-point-dedicated processor is connected, a storage means connected to the data bus, and a connection between the integer-dedicated processor and the data bus; A data processing system comprising: bidirectional conversion means for integer/floating point data. 4. an integer-only processor; and a first integer-only processor connected to the integer-only processor via first and second data buses, respectively.
and a second integer-only storage means; a floating-point-only processor; and third and fourth floating-point storage means connected to the floating-point-only processor via third and fourth data buses; A data processing system comprising bidirectional conversion means for integer/floating point data, which is formed by connecting a second and a fourth data bus. 5. The integer/floating point data conversion means receives an input terminal for integer data, an absolute value conversion means for converting the integer data input from the terminal into an absolute value, and inputs the integer converted to the absolute value. A digit encoder that calculates the number of digits and outputs the digit data obtained by subtracting 2 from the digit row, and a digit encoder that inputs the integer converted to the absolute value and the digit data and changes the integer to the upper bit side by the digit number data. a shifter that outputs a shift signal, a (0) determiner that outputs a determination signal "1" when the value of the input integer data is (0), and a (0) determiner that outputs a determination signal "1" when the value of the input integer data is (1). (1) a determiner that outputs a determination signal "1" when Output all “1” to the output bits (1
) generator, a base generator that outputs the base bit data of the exponent part of the output floating point data, inputting the outputs of the (0) generator, the (1) generator, and the base generator; (
0) When the output of the determiner is “1”, the output of the (0) generator is determined, and when the output of the (1) determiner is “1”, the output of the (1) generator is
) A first multiplexer that selects and outputs the output of the base generator when neither the output of the (0) determiner nor the output of the (1) determiner is "1";
0) The output of the generator and the (1) generator and the digit number encoder are input, and when the output of the (0) determiner is "1", the output of the (0) generator is input as described in (1). When the output of the determiner is "1", the output of the (1) generator is used; when the output of the (0) determiner and the output of the (1) determiner are both not "1", the output of the digit number encoder is determined. The second to select and output
a multiplexer, an output terminal for outputting the output of the shifter as the mantissa part of the output floating point data, and the first multiplexer;
and an output terminal that outputs the output of the second multiplexer as an exponent part, and an output terminal that is connected to the sign bit of the input integer data and outputs the sign of the output floating point data, and the floating point/integer The data conversion means includes an input terminal into which floating point data is input, an exponent encoder which inputs the exponent part of the input floating point data and calculates the number of digits of the output integer data, and A shifter that inputs the mantissa and shifts it to the upper bit side by the number of digits determined by the exponent encoder and adds "1" to the most significant bit and outputs it; and a shifter that inputs the output of the shifter and performs a predetermined rounding process. an approximate value converter that inputs the output of the approximate value converter and performs complement conversion based on the contents of the sign bit of the input floating point data; Claims 2, 3, and 4 further comprising an output terminal for adding a sign bit and outputting the resultant as integer data.
Data processing system as described. 6. An input terminal for integer data, an absolute value conversion means for converting the integer data input from the terminal into an absolute value, input the integer converted to the absolute value, calculate the number of digits, and calculate 2 from the number of digits.
a digit encoder that outputs digit number data obtained by subtracting , and a shifter that inputs the integer converted to the absolute value and the digit number data, shifts the integer to the upper bit side by the digit number data, and outputs the result. The value of the input integer data is (0)
a (0) determiner that outputs a determination signal “1” when the value of the input integer data is (1);
(1) a determiner that outputs “0”; a (0) generator that has a plurality of output bits and outputs all “0” to the output bits;
(1) a generator that has a plurality of output bits and outputs all "1" to the output bits; a base generator that outputs the base bit data of the exponent part of output floating point data; and (0)
Input the outputs of the generator and the (1) generator and the base generator, and when the output of the (0) determiner is "1", the (0)
When the output of the generator (1) is "1", the output of the (1) generator is "1", and the output of the (0) determiner and the (1) determiner are both "1". a first multiplexer that selects and outputs the output of the base generator when the base generator is not ``; The output of the device is “
When the output of the (1) determiner is "1", the output of the (1) generator is determined by the (0) determiner and the (1) determiner. The output of the device is “
a second multiplexer that selects and outputs the output of the digit number encoder when the number of digits is not 1'', an output terminal that outputs the output of the shifter as the mantissa part of the output floating point data, and the first and second multiplexers. An integer/floating point data conversion device comprising an output terminal that outputs an output as an exponent part, and an output terminal that is connected to the sign bit of the input integer data and outputs the sign of the output floating point data. 7. Floating point an input terminal into which data is input; an exponent encoder which inputs the exponent part of the input floating point data and calculates the number of digits of output integer data; and an exponent encoder which inputs the mantissa part of the input floating point data and calculates the number of digits of the output integer data; A shifter that shifts to the upper bit side by the number of digits determined by the partial encoder and adds "1" to the most significant bit and outputs it, and an approximate value that inputs the output of the shifter, performs predetermined rounding processing, and outputs it. a converter, a complement converter inputting the output of the approximate value converter and converting it to a complement based on the contents of the sign bit of the input floating point data; A floating point/integer data conversion device comprising an output terminal for outputting data.